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FD0404
TOP MLB
PCBF, X891
820-00863-09
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT
TITLE
DRAWING NUMBER
1:1
SCALEDATE
03/31/17
APPLE
DESIGNER
KEN KIPLINGER
THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR
062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.
ORIG DIV
TOP SIDE ASSEMBLY
8
2 1
124567
B
D
6 5 4 3
C
A
C
A
D
7
B
3
1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA
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MLB BOT
PCBF, X893
820-00869-06
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT
TITLE
DRAWING NUMBERSCALE
1:1
DATE
04/06/17
APPLE
DESIGNER
TIM REID
THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR
062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.
ORIG DIV
TOP SIDE ASSEMBLY
PCB 820-00869-06 X893 Intel Edition TOP MLB
BOM:639-04583 (Ultimate)
BOM:639-03409 (Extreme)
MCO:056-04077
X891/X893 MLB Top: EVT
1 OF 51
LAST_MODIFICATION=Mon Apr 3 13:03:06 2017
40
49 AUDIO: Speaker Amp Bottom
AUDIO: CODEC (2/2)
PEARL: B2B Rosaline + Misc
PEARL: B2B Romeo + Juliet
CAMERA: B2B Strobe + Hold Button
CAMERA: Strobe Drivers
CAMERA: B2B Tele (MT)
CAMERA: B2B Wide (WY)
CAMERA: PMU (2/2)
CAMERA: PMU (1/2)
SYSTEM POWER: B2B Cyclone + Button
SYSTEM POWER: Iktara
SYSTEM POWER: Charger
SYSTEM POWER: B2B Battery
SYSTEM POWER: Boost
SYSTEM POWER: PMU (4/4)
14
41
56
CG: B2B Orb & Touch
I/O: Overvoltage Cut-Off Circuit
58
42
39
38
40
38
37
SOC: Power (3/3)
SOC: Power (2/3)
SYSTEM: Mechanical Components
SENSORS
test_mlb
31
30
test_mlb
17
26
SOC: Power (1/3)
test_mlb
test_mlb
SYSTEM POWER: PMU Bucks (2/4)
SYSTEM POWER: PMU LDOs (3/4)
08/25/2015
10/13/2016
10/17/2016
10/13/2016
10/17/2016
CG: Power Supplies - Touch & Display
CAMERA: B2B FCAM
SOC: GPIO & UART
SOC: LPDP
SOC: MIPI & ISP
BOOTSTRAPPING
SYSTEM: Testpoints (Top)
16
8
9
11
12
10/13/2016
10/13/2016
15
16
13
test_mlb
NAND
7
14
test_mlb
10/13/2016
10/13/2016
1
2
4
21
45
test_mlb
test_mlb
47 test_mlb
19
32
10/13/2016
28
30
27
39
22
50
CG: B2B Display
ARC: Driver
10/13/2016
08/25/2015
15
17
10/13/2016
33
06/04/2015
10/13/2016
10/13/2016
10/13/2016
10/13/2016
10/17/2016
10/13/2016
10/13/2016
10/13/2016
11/01/2016
10/13/2016
10/13/2016
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
80
65
64
63
62
61
46
44
35
51
50
49
47
46
45
43
28
23
18
6
5
4
2
RADIOS
I/O: Interposer (Bottom)
I/O: B2B Dock
I/O: Hydra
I/O: USB PD
I/O: Accessory Buck
10/13/2016
5
1
10/17/2016
10/13/2016
57
10/13/2016
48
10/13/2016
10/17/2016
10/17/2016
10/17/2016
10/17/2016
10/13/2016
test_mlb 10/13/2016
test_mlb
36
48
19
36
4333
34
32
12
10
test_mlb
test_mlb
59
44
sync
SOC: Serial
SOC: PCIE
6
3
51
37
35
18
13
10/13/2016
PEARL: Power
29
10/13/2016
test_mlb
27
34
26
test_mlb
10/13/2016
10/13/2016
01/10/2017
08/25/2015
test_mlb
41
SYSTEM:BOM Tables
TABLE OF CONTENTS
10/13/2016
42
10/13/2016
10/13/2016
AUDIO: CODEC (1/2)
10/13/2016
10/13/2016
10/13/2016
SOC: JTAG,USB,XTAL
11
25
24
31
20
AUDIO: Speaker Amp Top
29
test_mlb
test_mlb
test_mlb
test_mlb
SYSTEM POWER: PMU Bucks (1/4)
SOC: AOP
10
SCH,MLB,TOP,X891
051-02221
2017-04-0500084097609 ENGINEERING RELEASED
1 OF 80
evt-1
9.0.0
NO
COMMONNOPCB
TABLE OF CONTENTS
820-00863 1 PCB,MLB_TOP,X891
1 SCH051-02221 SCH,MLB_TOP,X891 COMMON
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CK
APPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
D
SIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
 IV ALL RIGHTS RESERVED
 II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE
EEEE Codes
SOC
XTAL Alternate
Multi-Vendor Criticals
Global R/C Alternates
RCAM B2Bs
CODEC
Ansel
Acorn
Pearl B2B
Audio
Strobe B2B
Agnes Input
Agnes Output
Global Ferrites
Sensors
Soft-Term Cap Sub BOMs
NAND
Ultimate
Global Capacitors
Extreme
Global Inductors
2 OF 51
9.0.0
evt-1
2 OF 80
051-02221
EEEE FOR (MLB_TOP,639-04583,ULTIMATE)
EEEE FOR (MLB_TOP,639-03409,EXTREME) EXTREME
ULTIMATE
NO
NO
EEEE_HP26
U1000
SKYE+3GB, B0, M, DEV
825-7691
825-7691
BOM_TABLE_ALTS
138S00144
138S00140
138S00142
138S00166
152S00720
BOM_TABLE_ALTS
CAP,CER,X5R,0.1UF,10%,16V,0201
CAP,CER,X5R,470PF,10%,10V,01005
CAP,CER,X7R,220PF,10%,10V,01005
339S00358
339S00358
339S00358
U2600BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
0402,5.1uF@3V, Taiyo
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS BOM_TABLE_ALTS
BOM_TABLE_ALTS BOM_TABLE_ALTS
BOM_TABLE_ALTS BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTSBOM_TABLE_ALTS
BOM_TABLE_ALTSBOM_TABLE_ALTS
BOM_TABLE_ALTSBOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
BOM_TABLE_ALTS
138S00049
152S00622
U1000
1
RES, 3.92K, 0.1%, 0201
CAP,X5R,4.7UF,6.3V,0.65MM,0402
CAP,CER,X5R,0.22UF,20%,6.3V,20%
118S0717
FERR BD, 150OHM, TY
CAP,CER,X5R,0.22UF,20%,6.3V,01005
CAP,CER,X5R,2.2UF,20%,6.3V,0201IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608
IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012
IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012
IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012
IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012
IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016
IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012
IND,1.2UH, 3A, 2016, 0.65Z
IND,0.47UH,6.6A,3225,0.8Z
IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012
152S00620
152S00651
152S00650
138S0652
138S0706
132S0400
138S0831
152S00712 ALL IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012152S00620
152S00713 ALL IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012152S00621
IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016ALL152S00632152S00718
152S00631 IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012ALL152S00717
152S00626 IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012ALL152S00716
152S00714 ALL IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012
152S00631
152S00632
152S00640
IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012152S00641
152S00710 152S00617 IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608ALL
IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012ALL152S00640
U2600335S00285 335S00287 TOSHIBA, BICS3, ULTIMATE
335S00284 335S00287 TOSHIBA, 1Z, ULTIMATE
TYPICAL_CAPCRITICALC3602,C36222138S0831 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA
0402,16uF@1V, Kyocera138S00143 ALL138S00144
ALL138S00148 138S00149 0402-3T,10.5uF@1V, Kyocera
SUBBOM_CAP CRITICAL COMMONSUBBOM,MLB,TOP,CAP,TYPICAL,X8911685-00155
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA TYPICAL_CAPCRITICALC2970,C2971,C2980,C2981138S0831 4
SOFT_CAPCRITICALC4303CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA1138S00159
CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA SOFT_CAPCRITICALC46131138S00159
TYPICAL_CAPCRITICALC5641,C5653CAP,TYPICAL,10UF,10V,0402,MUR/KYO2138S0979
SOFT_CAPCRITICALC3710CAP,SOFT-TERM,10UF,10V,0402,MURATA1138S00160
ALL IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016152S00623152S00715
C4811,C4808 SOFT_CAPCRITICALCAP,SOFT-TERM,10UF,10V,0402,MURATA2138S00160
TYPICAL_CAPCRITICALC4303CAP,TYPICAL,2.2UF,6.3V,0201,MURATA1138S0831
SOFT_CAPCRITICALC4809,C4805CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA2138S00159
TYPICAL_CAPCRITICALC4809,C4805CAP,TYPICAL,2.2UF,6.3V,0201,MURATA2138S0831
152S00626
152S00622
152S00621
152S00617
155S0610 FERR BD, 150OHM, TDKALL155S00194
XTAL, 24M, 1612197S0446
138S00159 SOFT_CAPCRITICALC3602,C3622CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA2
CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA SOFT_CAPCRITICALC2970,C2971,C2980,C29814138S00159
155S0610 FERR BD, 150OHM, 01005
ALL155S0610155S00200
138S0831 TYPICAL_CAPCRITICALC3909,C3925,C4025CAP,TYPICAL,2.2UF,6.3V,0201,MURATA3
CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA3 SOFT_CAPCRITICALC3909,C3925,C4025138S00159
9 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA SOFT_CAPCRITICALC2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914138S00159
138S0831 TYPICAL_CAPCRITICALC2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914CAP,TYPICAL,2.2UF,6.3V,0201,MURATA9
IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012ALL152S00641152S00721
1
EEEE_J2WJ
SUBBOM_CAP685-00155685-00156 SUBBOM,MLB,TOP,CAP,SOFT,X891
TYPICAL_CAPC3710CAP,TYPICAL,10UF,10V,0402,MUR/KYO1138S0979 CRITICAL
ALL152S00651152S00653 IND,1.2UH,3A,2016,0.65Z
SANDISK, BICS3, ULTIMATEU2600335S00286 335S00287
TYPICAL_CAPCRITICALC4811,C4808CAP,TYPICAL,10UF,10V,0402,MUR/KYO2138S0979
SOFT_CAPCRITICALC5641,C5653CAP,SOFT-TERM,10UF,10V,0402,MURATA2138S00160
TYPICAL_CAPCRITICALC4613CAP,TYPICAL,2.2UF,6.3V,0201,MURATA1138S0831
IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016152S00623
IND,0.47UH,6.6A,3225,0.8ZL3340,L3341152S00649 152S00650
138S00144 0402,16uF@1V
ALL 0402,16uF@1V, Taiyo138S00163
138S00150 138S00149 ALL 0402-3T,10.5uF@1V, SEMCO
335S00247 335S00240 SANDISK, BICS3, EXTREMEU2600
ALL 0201,1.1uF@3V, SEMCO138S00141
0201,1.1uF@3V, TaiyoALL138S00141
0201,1.1uF@3V, KyoceraALL138S00141
ALL138S00146138S00165
138S00145 138S00146 ALL 0402,5.1uF@3V, Kyocera
138S00164 ALL138S00139 0201,3uF@1V, Taiyo
138S00139138S00138 ALL 0201,3uF@1V, Kyocera
132S0288
CAP,CER,X5R,0.01UF,10%,6.3V,01005132S0245
132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005
132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402
CAP,CER,NP0/C0G,15PF,5%,16V,01005131S0225
CAP,CER,NP0/C0G,27PF,5%,16V,01005131S0223
117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD
107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005
U1000339S00361 DDR-S-18,3G, B0
CRITICAL ULTIMATE1335S00287 HYNIX, 3DV3, ULTIMATE U2600
1335S00240 EXTREMECRITICALHYNIX, 3DV3, EXTREME U2600
132S0249
132S0275
138S00149 0402-3T,10.5uF@1V
RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201118S00068
CAP,CER,NP0/C0G,12PF,5%,16V,01005131S0220
339S00358 CRITICAL1 COMMON
118S0717 RES, 3.92K, 0.1%, 0201ALL118S0764
138S0652 ALL138S0648 CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO
CAP,CER,X5R,0.22UF,20%,6.3V,20%ALL138S0706138S0739
132S0436 ALL132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005
ALL138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201
DDR-S-20,3G, B0U1000339S00360
339S00359 DDR-H,3G, B0
SYSTEM:BOM Tables
SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb
138S00151 0402-3T,10.5uF@1V, TYALL138S00149
335S00276 335S00240 SAMSUNG, 3DV4, EXTREMEU2600
335S00228 335S00240 TOSHIBA, BICS3, EXTREMEU2600
335S00287335S00288 U2600 SAMSUNG, 3DV4, ULTIMATE
197S0612 197S0446 XTAL, 24M, 1612Y1000
132S00093 CAP,X5R,0.022UF,20%,6.3V,01005
377S0106 SUPPR,TRANS,VARISTOR,12V,33PF,01005
197S0446 XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612
155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005
155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605
138S0979 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM
131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201
CAP,CER,27PF,5%,C0G,25V,0201131S0804
CAP,CER,NP0/C0G,100PF,5%,16V,01005131S0307
CAP,CER,X5R,1000PF,10%,6.3V,01005132S0296
CAP,CER,X5R,820PF,10%,10V,01005132S0318
138S00141 0201,1.1uF@3V
138S00146 0402,5.1uF@3V
132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201
132S0316 CAP,CER,X5R,0.1UF,20%,6.3V,01005
132S0396 CAP,CER,X5R,1000PF,10%,10V,01005 CAP,CER,C0G,220PF,5%,10V,01005131S00053
131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005132S0436 CAP,CER,X5R,0.22UF,20%,6.3V,01005
132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201
132S0663 CAP,CER,X5R,1UF,10%,25V,0402
132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201
138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM
138S00070 CAP,X5R,4.7UF,20%,25V,0402
138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402
138S0683 CAP,CER,X5R,1UF,10%,25V,0402
138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201
138S00139 0201,3uF@1V
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
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3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
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 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEADTABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_5_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEADTABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENT
TABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEMTABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
FIDUCIALS
3 OF 51
9.0.0
evt-1
4 OF 80
051-02221
1
SB0402
1
FD0420
1
SH0401
1
FD0412
1
FD0401
1
FD0402
1
FD0403
1
FD0404
1
FD0405
1
FD0410
1
FD0411
1
SH0400
1
CL0400
1
CL0402
1
CL0401
1
CL0403
1
SB0400
1
SB0401
SYSTEM: Mechanical Components
2.10R1.60-NSP
2.10R1.60-NSP
2.10R1.60-NSP
2.10R1.60-NSP
STDOFF-MLB-TUBE
CRITICAL
0P5SQ-CROSS-NSP
FID
ROOM=ASSEMBLY
SM
CRITICAL
SHLD-EMI-HARD-X891
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSP
FID
FID
0P5SQ-CROSS-NSP
ROOM=ASSEMBLY
FID
0P5SQ-CROSS-NSP
ROOM=ASSEMBLY
CRITICAL
STDOFF-2.9OD1.4ID-0.77H-SM
FID
0P5SQ-CROSS-NSP
ROOM=ASSEMBLY
ROOM=ASSEMBLY
0P5SQ-CROSS-NSP
FID
FID
0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
FID
0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
FID
SM
SHIELD-EMI-TOP-X891
CRITICAL
STDOFF-2.9OD1.4ID-0.77H-SM
CRITICAL
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
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PAGE
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REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
Probe Points
Sensors
Rigel
Hydra VBUS
NAND CCG2
SOC I2C1_AOP
SOC Debug
PCIE Refclk
PMU
SOC CPU/GPU
POWER
Test Points
4 OF 51
9.0.0
evt-1
5 OF 80
051-02221
1
PP0506
1
PP0592
1
PP0590
1
PP0591
1
PP0583
1
PP0586
1
PP0587
1
PP0582
1
PP0505
1
TP0543
1
TP0540
1
PP0547
1
PP0546
1
PP0545
1
PP0544
1
PP0571
1
PP0570
21
XW0511
21
XW0510
1
PP0504
1
PP0564
1
PP0563
1
PP0522
1
PP0562
1
PP0521
1
PP0516
1
PP0515
1
PP0514
1
PP0561
1
PP0560
1
PP0550
1
PP0542
1
PP0541
1
PP0540
1
PP0531
1
PP0530
1
PP0520
1
PP0513
1
PP0512
1
PP0503
1
PP0502
1
PP0501
1
PP0500
PP_ROMEO_DENSE_ANODE
ROOM=TEST
ROOM=TEST
SM
P2MM-NSM
SM
P2MM-NSM
PP_ROMEO_CATHODE
SM
P2MM-NSM
ROOM=TEST
P2MM-NSM
20 
SPI_AOP_TO_IMU_SCLK
AP_BI_CCG2_SWDIO
SPI_AOP_TO_IMU_MOSI
SPI_IMU_TO_AOP_MISO
RIGEL_TO_ISP_INT
CAMPMU_TO_RIGEL_ENABLE
NAND_ANI1_VREF
NAND_ANI0_VREF
PDM_CODEC_TO_ARC_CLK
PDM_CODEC_TO_ARC_DATA
ACCEL_GYRO_TO_AOP_INT
ACCEL_GYRO_TO_AOP_DATARDY
COMPASS_TO_AOP_INT
PHOSPHORUS_TO_AOP_INT
HYDRA_TO_TIGRIS_VBUS1_VALID_L
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
SWD_AOP_TO_MANY_SWCLK
SWD_AP_BI_NAND_SWDIO CCG2_TO_SMC_INT_L
I2C1_AOP_SDA
I2C1_AOP_SCL
AP_TO_CCG2_SWCLK
BOARD_ID0
AP_TO_PMU_TEST_CLKOUT
PP_GPU
AP_CPU_PCORE_SENSE
PP_CPU_PCORE_LVCCPP_CPU_PCORE
AP_VDD_GPU_SENSE
TP_SOC_SENSE
TP_VSS_CPU_SENSE
TP_VSS_SENSE
AOP_TO_DDR_SLEEP1_READY
SPMI_PMU_BI_PMGR_SDATA
PMU_TO_AP_HYDRA_ACTIVE_READY
90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N
PP_GPU_LVCC
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_SOCHOT_L
DFU_STATUS
AP_TO_FCAM_SHUTDOWN_L
AP_DEBUG3
SYSTEM: Testpoints (Top)
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
20 6 
ROOM=TEST
SM
P2MM-NSM
47 10 
P2MM-NSM
SM
ROOM=TEST
50 49 41 25 12 
50 49 41 25 12 
ROOM=TEST
SM
P2MM-NSM
ROOM=TEST
P2MM-NSM
SM
41 37 
P2MM-NSM
SM
ROOM=TEST
47 10 
ROOM=TEST
SM
P2MM-NSM
47 10 
ROOM=TEST
SM
P2MM-NSM
P2MM-NSM
SM
ROOM=TEST
41 37 
11 6 
P2MM-NSM
SM
ROOM=TEST
26 12 
ROOM=TEST
P2MM-NSM
SM
49 25 12 
ROOM=TEST
P2MM-NSM
SM
26 12 
ROOM=TEST
SM
P2MM-NSM
26 12 
ROOM=TEST
SM
P2MM-NSM
ROOM=TEST
P2MM-NSM
SM
34 20 8 
34 28 
P2MM-NSM
SM
ROOM=TEST
SHORT-10L-0.05MM-SM
SHORT-10L-0.05MM-SM
11 
16 
ROOM=TEST
P2MM-NSM
SM
SM
P2MM-NSM
ROOM=TEST
16 
P2MM-NSM
ROOM=TEST
SM
48 20 6 
16 10 5 
SM
ROOM=TEST
P2MM-NSM
20 10 
SM
P2MM-NSM
ROOM=TEST
15 
P2MM-NSM
ROOM=TEST
SM
P2MM-NSM
ROOM=TEST
SM
15 
13 
P2MM-NSM
ROOM=TEST
SM
50 16 12 
16 12 
48 23 
26 12 
26 12 
26 12 
16 7 
16 7 
14 12 
20 13 
20 13 
8 
32 8 
11 5 
20 6 
P2MM-NSM
ROOM=TEST
SM
ROOM=TEST
P2MM-NSM
SM
P2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
P2MM-NSM
SM
P2MM-NSM
ROOM=TEST
SM
SM
ROOM=TEST
P2MM-NSM
P2MM-NSM
SM
ROOM=TEST
SM
P2MM-NSM
ROOM=TEST
SM
ROOM=TEST
P2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SM
P2MM-NSM
ROOM=TEST
SM
ROOM=TEST
SM
P2MM-NSM
34 35 
34 35 
17 13 
50 17 13 
50 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCEOR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN PP
IN PP
IN
IN PP
PP
IN PP
IN PP
IN PP
PPIN
IN PP
PP
PP
IN PP
IN PP
IN PP
IN PP
PPIN
IN PP
IN
IN PP
PPIN
PPIN
IN PP
IN PP
IN PP
PPIN
IN PP IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
BOARD ID
BOOT CONFIG
No connect
On mlb_bot
No connect
D221 Baseband Selected on RF Board
BOOTSTRAPPING:BOARD REV
SELECTED -->
SELECTED -->
SELECTED -->
No connect
5 OF 51
PP1V8_IO
PP1V8_IO
CKPLUS_WAIVE=SINGLE_NODENET
9.0.0
evt-1
6 OF 80
051-02221
21
R0623
21
R0622
21
R0600
21
R0601
21
R0620
21
R0621
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
BOARD_REV0
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
BOARD_REV1
BOARD_REV2
BOARD_REV3
BOARD_ID3
BOARD_ID0
PP1V8_IO
MAKE_BASE=TRUE
BOARD_ID4
CKPLUS_WAIVE=SINGLE_NODENET
BOOTSTRAPPING
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
NOSTUFF
01005
4.7K
ROOM=SOC
MF
1/32W
1%
01005
4.7K
ROOM=SOC
1/32W
MF
1%
5%
MF
1/32W
01005
ROOM=SOC
1.00K
1.00K
MF
01005
ROOM=SOC
1/32W
5%
1.00K
01005
ROOM=SOC
5%
MF
1/32W
NOSTUFF
5%
1/32W
1.00K
ROOM=SOC
MF
01005
16 10 
16 10 
16 10 4 
11 4 
11 
11 
50 10 
11 
11 
11 
11 
11 
43 35 34 32 
30 29 28 27 17 16 14 10 8 7 6 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
USB Reference
(Analog)
0.765V - 0.84V @ 5mA MAX
VDD18_USB: 1.62V - 1.98V @ 20mA MAX
VDD11_XTAL:1.06-1.17V @ 2mA MAX
3.14-3.46V @ 12mA MAX
SOC - USB, JTAG, XTAL
evt-1
10 OF 80
6 OF 51
051-02221
9.0.0
MAKE_BASE=TRUE GND
GND
GND
MAKE_BASE=TRUE
21
R1020
2
1 C1093
21
FL1092
2
1 C1090
2
1 C1092
2
1 C1095
BA27
BA28
AW5
AN
15
AN
14
AU
28
AP
14
AT
7
AV7
AU8
AW6
AY6
BA6
AY4
BA4
V2
W4
AF34
AG38
A30
AV6
AT10
AT9
AT12
AT13
AT8
W5
AD3
AD2
B31
AW21
AT22
AU7
AV5
AT34
AT27
U1000
2
1R1000
2
1 C1010
2
1R1010
21
R1011
31
42
Y1000
2
1 C1011
AP_USB_REXT
PMU_TO_AP_HYDRA_ACTIVE_READY
AP_TO_PMU_TEST_CLKOUT
PMU_TO_SYSTEM_COLD_RESET_L
SWD_DOCK_TO_AP_SWCLK
SWD_DOCK_BI_AP_SWDIO
PMU_TO_SYSTEM_COLD_RESET_R_L
AP_TO_NAND_FW_STRAP
AP_TO_PMU_AMUX_OUT
90_USB_AP_DATA_N
90_USB_AP_DATA_P
USB_VBUS_DETECT
PMU_TO_AP_THROTTLE_GPU1_L
PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_THROTTLE_ECORE_L
AP_TO_PMU_WDOG_RESET
AP_TO_PMU_SOCHOT_L
PMU_TO_AP_PRE_UVLO_L
AP_USB_REXT
PMU_TO_AP_THROTTLE_PCORE_L
PP0V8_SOC_FIXED_S1
PP3V3_USB
PP1V8_IO
PP1V8_XTAL
AP_TO_NAND_RESET_L
SOC_24M_O
XTAL_AP_24M_OUT
XTAL_AP_24M_IN
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
SOC: JTAG,USB,XTAL
01005
10K
MF
1/32W
5%
0201
4UF
ROOM=SOC
CER-X5R
6.3V
20%
240-OHM-25%-0.20A-0.9DCR
01005
ROOM=SOC
0.1UF
X5R-CERM
01005
20%
6.3V
ROOM=SOC
X5R-CERM
01005
ROOM=SOC
20%
6.3V
0.1UF
0.1UF
6.3V
X5R-CERM
ROOM=SOC
20%
01005
20 
20 
20 
16 
20 4 
20 
20 11 4 
20 
20 
23 
48 
48 
20 
16 
20 4 
48 20 4 
48 
48 
WLCSP
TMIT78B0-C4
ROOM=SOC
CRITICAL
OMIT_TABLE
ROOM=SOC
1/32W
1%
01005
MF
200
16V
ROOM=SOC
5%
01005
CERM
12PF
NOSTUFF
1/32W
01005
1%
MF
511K
ROOM=SOC
5%
1.00K
ROOM=SOC
01005
MF
1/32W
ROOM=SOC
1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
CERM
ROOM=SOC
16V
5%
01005
12PF
6 
6 
17 14 13 9 8 7 
19 
43 35 34 32 
30 29 28 27 17 16 14 10 8 7 5 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
OUT
NC
NC
NC
NC
NC
OUT
IN
IN
IN
OUT
IN
BI
BI
OUT
OUT
OUT
IN
IN
BI
SYM 1 OF 16
VD
D1
2_
UH
1_
HS
IC
0
VD
D1
8_
XT
AL
VD
D1
8_
US
B
VD
D3
3_
US
B
VD
D_
FI
XE
D_
US
B
XO0
XI0
CPU_TRIGGER0
USB_REXT
DROOP
SOCHOT1
WDOG
CPU_TRIGGER1
GPU_TRIGGER0
GPU_TRIGGER1
USB_ID
USB_VBUS
USB_DP
USB_DM
ANALOGMUX_OUT
SSD_BFH
TESTMODE
HOLD_RESET
COLD_RESET*
JTAG_TMS
JTAG_TCK
JTAG_TDI
SSD_RESET*
CFSB_AON
TST_CLKOUT
CFSB
UH1_HSIC0_STB
UH1_HSIC0_DATA
JTAG_SEL
JTAG_TDO
JTAG_TRST*
NC
VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX
(Analog)
PC
IE
 L
IN
K 
0
PCIe Reset Pull-Downs
PC
IE
 L
IN
K 
2
PC
IE
 L
IN
K 
3
SOC - PCIE INTERFACES
(Analog)
1.62V - 1.98V @ 81mA MAX
VDD_FIXED_PCIE_REFBUF:0.765V - 0.84V @ 9mA MAX
VDD_FIXED_PCIE_ANA:0.765V - 0.84V @ 131mA MAX
PCIe BB CLKREQ PU on BB domain
PCIe Clock Request Pull-Ups
7 OF 51
9.0.0
evt-1
11 OF 80
051-02221
2
1 C1124
2
1 C1125
2
1 C1191
2
1 C1192
2
1 C1193
21
R1194
2
1 C1194
2
1 C1199
2
1 C1198
21
R1198
2
1R1121
2 1 C1102
2 1 C1103
2 1 C1100
2
1R1130
2 1 C1101
21C1122
21C1121
21C1120
21C1123
AP
27
AM
27
AP
31
AP
29
AN
30
AM
31
AM
29
AP
26
AN
26
AV35
AW35
AV33
AW33
AY32
BA32
AY30
BA30
BA36
AY36
BA34
AY34
AV31
AW31
AV29
AW29
AU32
AY24
BA24
AV25
AW25
AW26
AY26
AW27
AV27
AH36
AJ38AK38
AJ37
AU30
AT30
AJ36
AK37AL37
AL38
U1000
2
1R1100
2
1R1101
2
1R1150
2
1R1131
21C1133
21C1132
21C1131
21C1130
PP1V8_IO
90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P
PCIE_AP_TO_NAND_RESET_L
PCIE_NAND_BI_AP_CLKREQ_L
PCIE_AP_TO_WLAN_RESET_L
PCIE_WLAN_BI_AP_CLKREQ_L
PCIE_AP_TO_BB_RESET_L
90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N
90_PCIE_NAND_TO_AP_RXD_N 90_PCIE_WLAN_TO_AP_RXD_N
PP1V2_SOC
PCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_WLAN_TO_AP_RXD_C_N
PCIE_AP_TO_WLAN_RESET_L
90_PCIE_WLAN_TO_AP_RXD_C_P
90_PCIE_AP_TO_BB_TXD_C_N
90_PCIE_AP_TO_BB_TXD_C_P
PCIE_AP_TO_BB_RESET_L
PCIE_NAND_BI_AP_CLKREQ_L
90_PCIE_AP_TO_NAND_REFCLK_P
90_PCIE_AP_TO_NAND_REFCLK_N
90_PCIE_AP_TO_NAND_TXD_C_N
90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_NAND_TO_AP_RXD_C_N
90_PCIE_NAND_TO_AP_RXD_C_P
PCIE_AP_TO_NAND_RESET_L
PP0V8_SOC_FIXED_PCIE_REFBUF
PP0V8_SOC_FIXED_S1
PP1V8_IOPP1V2_SOC_PCIE_REFBUF
90_PCIE_AP_TO_WLAN_TXD_C_N
90_PCIE_AP_TO_WLAN_TXD_C_P
90_PCIE_BB_TO_AP_RXD_C_P
AP_PCIE_RCAL
90_PCIE_BB_TO_AP_RXD_C_N
90_PCIE_BB_TO_AP_RXD_P
90_PCIE_AP_TO_BB_REFCLK_N
90_PCIE_AP_TO_BB_REFCLK_P
PCIE_BB_BI_AP_CLKREQ_L
SOC: PCIE
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
+/-0.1PF
4.7PF
NP0-C0G
01005
16V
ROOM=SOC
NP0-C0G
4.7PF
01005
16V
+/-0.1PF
ROOM=SOC
4UF
CER-X5R
ROOM=SOC
0201
6.3V
20%
1.0UF
20%
6.3V
X5R
ROOM=SOC
0201-1
20%
6.3V
X5R-CERM
ROOM=SOC
01005
0.1UF
1/32W
MF
01005
ROOM=SOC
0%
0.00
6.3V
20%
01005
X5R-CERM
0.1UF
ROOM=SOC
4UF
CER-X5R
ROOM=SOC
0201
20%
6.3V
0.1UF
6.3V
20%
ROOM=SOC
X5R-CERM
01005
ROOM=SOC
01005
MF
1/32W
0%
0.00
100K
1/32W
5%
MF
01005
ROOM=SOC
50 
50 
50 
50 7 
50 
50 
50 
50 
50 7 
50 
50 
50 
50 
50 
50 7 
50 
16 7 
16 7 
16 4 
16 4 
16 
16 
16 
16 
GND_VOID
01005
0.22UF
ROOM=SOC
6.3V 20%
X5R
GND_VOID
0.22UF
20%
X5R
6.3V
ROOM=SOC
01005
ROOM=SOC
X5R
GND_VOID20%
01005
0.22UF
6.3V
1/32W
5%
MF
ROOM=SOC
01005
100K
0.22UF
01005
6.3V 20%
X5R
GND_VOID
ROOM=SOC
GND_VOID
X5R-CERM
20%
ROOM=SOC
01005
6.3V
0.1UF
20%
X5R-CERMROOM=SOC
GND_VOID 6.3V
01005
0.1UF
20%
X5R-CERM
ROOM=SOC
01005
6.3VGND_VOID
0.1UF
GND_VOID
X5R-CERM
6.3V
01005
0.1UF
20%
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
MF
1/32W
01005
5%
100K
ROOM=SOC
1/32W
5%
100K
MF
ROOM=SOC
01005
ROOM=SOC
1%
1/32W
MF
200
01005
100K
1/32W
5%
MF
01005
ROOM=SOC
0.1UF
01005
6.3V20%GND_VOID
ROOM=SOC
X5R-CERM
X5R-CERM
6.3V
01005
0.1UF
20%GND_VOID
ROOM=SOC
GND_VOID
X5R-CERM
ROOM=SOC
6.3V
01005
0.1UF
20%
GND_VOID
X5R-CERM
20%
ROOM=SOC
6.3V
01005
0.1UF
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
16 7 
16 7 
50 7 
50 7 
50 7 
19 14 13 9 
17 14 13 9 8 6 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
BI
OUT
OUT
OUT
IN
IN
OUT
IN
IN
OUT
OUT
OUT
BI
OUT
OUT
BI
OUT
OUT
OUT
OUT
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
SYM 2 OF 16
LINK1 LINK2
LINK3LINK0
PCIE_CLKREQ3*
PCIE_REF_CLK3_N
PCIE_REF_CLK3_P
PCIE_CLKREQ2*
PCIE_RX3_N
PCIE_REF_CLK2_P
PCIE_REF_CLK2_N
PCIE_PERST3*
PCIE_TX3_P
PCIE_TX3_N
PCIE_RX3_P
PCIE_TX2_N
PCIE_TX2_P
PCIE_PERST2*
PCIE_RX2_N
PCIE_RX2_P
PCIE_REXT
PCIE_CLKREQ0*
PCIE_REF_CLK0_P
PCIE_REF_CLK0_N
PCIE_TX0_N
PCIE_TX0_P
PCIE_RX0_N
PCIE_RX0_P
PCIE_REF_CLK1_P
PCIE_CLKREQ1*
PCIE_PERST0*
PCIE_REF_CLK1_N
PCIE_RX1_N
PCIE_RX1_P
PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N
PCIE_PERST1*
PCIE_TX1_P
PCIE_TX1_N
VD
D_
FI
XE
D_
PC
IE
_R
EF
BU
F
VD
D_
FI
XE
D_
PC
IE
_R
EF
BU
F
VD
D_
FI
XE
D_
PC
IE
_A
NA
VD
D_
FI
XE
D_
PC
IE
_A
NA
VD
D_
FI
XE
D_
PC
IE
_A
NA
VD
D1
8_
PC
IE
VD
D1
8_
PC
IE
VD
D1
2_
PC
IE
_R
EF
BU
F
VD
D1
2_
PC
IE
_R
EF
BU
F
MIPI Reference
Di
sp
la
y 
MI
PI
(Analog)
1.62V - 1.98V @ 10mA MAX
ISP I2C1
ISP I2C2
ISP I2C0
ISP I2C3
FC
AM
 M
IP
I
Ju
li
et
 M
IP
I
MIPI Lane & Polarity Swapping
SOC - MIPI & ISP INTERFACES
0.765V - 0.84V @ 40mA MAX
8 OF 51
90_MIPI_AP_TO_DISPLAY_CLK_N
90_MIPI_AP_TO_DISPLAY_CLK_P
90_MIPI_FCAM_TO_AP_DATA0_N
90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_FCAM_TO_AP_CLK_N
90_MIPI_FCAM_TO_AP_DATA1_N
90_MIPI_FCAM_TO_AP_DATA0_P
90_MIPI_JULIET_TO_AP_DATA0_P
90_MIPI_JULIET_TO_AP_DATA0_N
90_MIPI_JULIET_TO_AP_DATA1_P
90_MIPI_JULIET_TO_AP_DATA1_N
90_MIPI_JULIET_TO_AP_CLK_N
90_MIPI_JULIET_TO_AP_CLK_P
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA3_N
90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA1_N
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_FCAM_TO_AP_DATA1_P
9.0.0
evt-1
12 OF 80
051-02221
21
R1243
21
R1241
2
1R1251
2
1R1231
2
1R1232
2
1R1222
2
1R1221
2
1R1212
2
1R1211
2
1R1201
2
1R1202
G
14
G
12
F1
3
F1
1
AB36
AA35
AC37
AB34
R37
T37
U35
U36
R38
U37
V34
V36
U38
D11
A6
A7
B9
A10
A8
B6
B7
A9
B10
B8
D13
B15
B17
A16
A15
A17
B16
D12
B14
B12
A13
A14
A12
B13
AB38
AA37
Y38
Y34
Y36
W36
V38
W35
AB6
AB4
AA3
Y4
AA5
AA4
U1000
21
R1242
21
R1240
2
1 C1296
2
1C1290
2
1 C1295
2
1R1252
2
1R1250
2
1C1291
MIPID_REXT
MIPI1C_REXT
MIPI0C_REXT
AP_TO_FCAM_JULIET_CLK
PP1V8_IO
I2C3_ISP_SCL
AP_TO_WIDE_CLK
AP_TO_TELE_CLK
I2C2_ISP_SDA
I2C0_ISP_SDA
PP1V8_IO
I2C3_ISP_SDA
PP1V8_IO
I2C1_ISP_SDA
PP1V8_IO
I2C2_ISP_SCL
I2C1_ISP_SCL
I2C0_ISP_SCL
AP_TO_RIGEL_CLK
90_MIPI_AP_TO_DISPLAY_DATA1_P MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA2_N MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA3_P MAKE_BASE
90_MIPI_FCAM_TO_AP_DATA1_P MAKE_BASE
90_MIPI_JULIET_TO_AP_DATA0_P MAKE_BASE
90_MIPI_JULIET_TO_AP_DATA1_P MAKE_BASE
90_MIPI_FCAM_TO_AP_DATA1_N MAKE_BASE
MAKE_BASE90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_AP_TO_DISPLAY_CLK_P MAKE_BASE
90_MIPI_AP_TO_DISPLAY_CLK_N MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA2_P MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA3_N MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA1_N MAKE_BASE
MAKE_BASE90_MIPI_FCAM_TO_AP_CLK_N
90_MIPI_JULIET_TO_AP_DATA1_N MAKE_BASE
90_MIPI_JULIET_TO_AP_DATA0_N MAKE_BASE
90_MIPI_JULIET_TO_AP_CLK_N MAKE_BASE
90_MIPI_JULIET_TO_AP_CLK_P MAKE_BASE
90_MIPI_FCAM_TO_AP_DATA0_N MAKE_BASE
PP1V8_IO
MIPID_REXT
DISPLAY_TO_AP_ALIVE
AP_TO_MANY_BSYNC
MIPI1C_REXT
MIPI0C_REXT
AP_DEBUG3
ISP_TO_DISPLAY_FLASH_INT
AP_TO_TELE_CLK_R
AP_TO_WIDE_CLK_R
RIGEL_TO_ISP_INT
I2C3_ISP_SDA
I2C0_ISP_SCL
I2C1_ISP_SCL
I2C0_ISP_SDA
I2C2_ISP_SCL
I2C2_ISP_SDA
I2C1_ISP_SDA
I2C3_ISP_SCL
AP_TO_FCAM_SHUTDOWN_L
AP_TO_WIDE_SHUTDOWN_L
AP_TO_TELE_SHUTDOWN_L
AP_TO_JULIET_SHUTDOWN_L
AP_TO_FCAM_JULIET_RIGEL_CLK_R
PP0V8_SOC_FIXED_S1
90_MIPI_AP_TO_DISPLAY_DATA0_N
90_MIPI_AP_TO_DISPLAY_DATA0_P
MAKE_BASE90_MIPI_FCAM_TO_AP_DATA0_P
SOC: MIPI & ISP
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
35 
30 
29 
43 
34 20 4 
34 
1%
1/32W
01005
MF
33.2
ROOM=SOC
50 28 21 20 12 
32 4 
4 
30 
33.2
MF
01005
1%
1/32W
ROOM=SOC
32 
32 
32 
32 
32 
32 
43 
43 
43 
43 
43 
43 
43 
43 
35 
35 
29 
35 32 
1%
1/32W
200
01005
ROOM=SOC
MF
43 
35 34 31 28 8 
35 34 31 28 8 
32 8 
32 8 
30 8 
30 8 
29 8 
29 8 
43 
43 
35 
35 
35 
35 
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
1.00K
MF
01005
5%
1/32W
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
1/32W
ROOM=SOC
1%
01005
33.2
MF
33.2
MF
1%
1/32W
ROOM=SOC
01005
0.1UF
X5R-CERM
01005
20%
6.3V
ROOM=SOC
X5R-CERM
01005
20%
6.3V
ROOM=SOC
0.1UF 2.2UF
X5R-CERM
0201
20%
6.3V
ROOM=SOC
MF
01005
1%
1/32W
ROOM=SOC
200
MF
01005
1%
1/32W
ROOM=SOC
200
2.2UF
0201
20%
6.3V
ROOM=SOC
X5R-CERM
8 
8 
8 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
35 34 31 28 8 
32 8 
29 8 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
35 34 31 28 8 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
30 8 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
32 8 
30 8 
29 8 
43 35 34 32 
30 29 28 27 17 16 14 10 8 7 6 5 
8 
8 
8 
17 14 13 9 7 6 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
IN
IN
OUT
NC
NC
NC
OUT NC
OUT
OUT
NC
OUT
IN
IN
BI
IN
BI
IN
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
IN
IN
OUT
OUT
OUT
BI
OUT
BI
OUT
BI
OUT
BI
OUT
OUT
OUT
IN
IN
BI
BI
SYM 3 OF 16
ISP_I2C3_SCL
ISP_I2C1_SDA
ISP_I2C2_SDA
ISP_I2C2_SCL
ISP_I2C0_SDA
ISP_I2C1_SCL
ISP_I2C0_SCL
ISP_I2C3_SDA
SENSOR_INT
SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK
SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST
SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN
SENSOR1_ISTRB
SENSOR0_ISTRB
MIPI0C_DNCLK
MIPI0C_REXT
MIPI0C_DPCLK
MIPI0C_DNDATA1
MIPI0C_DPDATA1
MIPI0C_DNDATA0
MIPI0C_DPDATA0
MIPI1C_REXT
MIPI1C_DNDATA0
MIPI1C_DNDATA1
MIPI1C_DPDATA1
MIPI1C_DNCLK
MIPI1C_DPCLK
MIPI1C_DPDATA0
MIPID_DPDATA0
MIPID_DNDATA0
MIPID_DPDATA1
MIPID_DNDATA1
MIPID_DPDATA2
MIPID_DPDATA3
MIPID_DNDATA2
MIPID_DNDATA3
DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1
DISP_TOUCH_EB
MIPID_DNCLK
MIPID_REXT
MIPID_DPCLK
DISP_I2C_SDA
DISP_POL
DISP_I2C_SCL
VD
D1
8_
M
IP
I
VD
D_
FI
XE
D_
M
IP
I
NC
NC
VDD12_LPDP 1.14V - 1.26V @ 72mA MAX
VDD12_PLL_LPDP 1.14V - 1.26V @ 10mA MAX
VDD_FIXED_PLL_LPDP 0.765V - 0.84V @ 3mA MAX
VDD_FIXED_LPDP_TX 0.765V - 0.84V @ 16mA MAX
VDD_FIXED_LPDP_RX 0.765V - 0.84V @ 30mA MAX
(Analog)
SOC - LPDP
Desensefor Wifi frequencies
9 OF 51
MAKE_BASE=TRUE
GND
GND
9.0.0
evt-1
13 OF 80
051-02221
R9 P9 G
18
G
16
T9M
9
F1
6
F1
7
F1
5
A19
B19
A20
B20
A21
B21
A24
B24
A25
B25
A26
B26
B23
A23
D18
A22
B22
D15
D16
D17
D19
D20
D21
J4
J5
K3
K4
L4
L5
M3
M4
H6
H3
G4
G5
Y6
Y2
U1000
2
1 C1390
2
1 C1395
2
1 C1396
2
1C1301
2
1R1300
2
1 C1394
2
1 C1393
2
1 C1391
2
1 C1392
PP0V8_SOC_FIXED_S1
90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D2_N
LPDP_TELE_BI_AP_AUX
AP_LPDPRX_RCAL_NEG
PP0V8_SOC_FIXED_S1
90_LPDP_WIDE_TO_AP_D2_N
90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_WIDE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D0_N
90_LPDP_TELE_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_TELE_TO_AP_D1_P
90_LPDP_TELE_TO_AP_D1_N
LPDP_WIDE_BI_AP_AUX
90_LPDP_WIDE_TO_AP_D1_N
90_LPDP_TELE_TO_AP_D2_P
PP1V2_SOC
SOC: LPDP
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
30 
30 
29 
29 
29 
29 
29 
29 
5%
16V
100PF
ROOM=SOC
01005
NP0-C0G
1%
ROOM=SOC
MF
1/32W
300
01005-1
ROOM=SOC
5%
16V
01005
NP0-C0G-CERM
15PF2.2UF
X5R-CERM
ROOM=SOC
0201
20%
6.3V
0.01UF
ROOM=SOC
01005
10%
6.3V
X5R
01005
20%
ROOM=SOC
6.3V
X5R-CERM
0.1UF
WLCSP
TMIT78B0-C4
X5R-CERM
6.3V
20%
0201
ROOM=SOC
2.2UF
ROOM=SOC
2.2UF
6.3V
X5R-CERM
20%
0201
X5R-CERM
ROOM=SOC
6.3V
20%
2.2UF
0201
30 
29 
30 
30 
30 
30 
17 14 13 9 8 7 6 
17 14 13 9 8 7 6 
19 14 13 7 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
SYM 4 OF 16
VD
D_
FI
XE
D_
LP
DP
_R
X
VD
D_
FI
XE
D_
LP
DP
_T
X
LPDP_TX0N
LPDP_TX0P
LPDP_TX1P
LPDP_TX1N
LPDP_TX2P
LPDP_TX2N
LPDP_TX3P
LPDP_TX3N
LPDP_CAL_DRV_OUT
LPDP_AUX_P
LPDP_AUX_N
LPDP_CAL_VSS_EXT
EDP_HPD
DP_WAKEUP
LPDPRX_RX_D0_P
LPDPRX_RX_D1_N
LPDPRX_RX_D1_P
LPDPRX_RX_D0_N
LPDPRX_RX_D2_N
LPDPRX_RX_D3_N
LPDPRX_RX_D3_P
LPDPRX_RX_D2_P
LPDPRX_RX_D4_P
LPDPRX_RX_D5_N
LPDPRX_RX_D5_P
LPDPRX_RX_D4_N
LPDPRX_AUX_D0_P
LPDPRX_BYP_CLK_P
LPDPRX_BYP_CLK_N
LPDPRX_AUX_D2_P
LPDPRX_AUX_D1_P
LPDPRX_AUX_D4_P
LPDPRX_AUX_D3_P
LPDPRX_AUX_D5_P
LPDPRX_RCAL_P
LPDPRX_RCAL_N
LPDPRX_EXT_C
VD
D_
FI
XE
D_
PL
L_
LP
DP
VD
D1
2_
PL
L_
LP
DP
VD
D1
2_
LP
DP
_R
X
VD
D1
2_
LP
DP
_T
X
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
IN
IN
IN
IN
AP I2C4
AP I2C3
SMC I2C
AP I2C1
Place series terminations close to SoC Pins
SPI: Route as Daisy-Chain. No T's Allowed
SOC - SERIAL INTERFACES
. 
AP I2C0
AP I2C2
10 OF 51
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
9.0.0
evt-1
14 OF 80
051-02221
2
1R1471
2
1R1470
B2
A1
A2B1
U1490
2
1 C1490
21
R1465
21
R1482
21
R1464
2
1R1451
2
1R1450
21
R1481
2
1R1431
2
1R1430
2
1R1441
2
1R1440
AW20
AV21
AE37
AF38
AE35
AE38
AE6
AD5
AE2
AE4
AT23
AW22
AY22
AU23
AU22
BA22
BA21
AV22
AW15
AW19
AU20
AT20
AW16
AY16
AL6
AM4
AM5
AM3
AL2
BA20
AG4
AH2
AH4
AH6
AG5
AT35
AR36
AR35
AR34
AT36
AH34
AG35
AG37
AH38
AG36
AV23
AT24
AT26
AT25
AW23
AC38
AC36
B34
A34
AD36
AD38
AG2
AG3
AF36
AE36
AV19
U1000
2
1R1420
2
1R1421
2
1R1410
2
1R1411
2
1R1400
2
1R1401
21
R1461
21
R1462
21
R1480
21
R1460
335S00234
335S00234
WLCSP U1490
BOM_TABLE_ALTS
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SPI_CODEC_TO_AP_MISO
SPI_AP_TO_CODEC_MOSI
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_BCLK
I2C2_AP_SDA
I2C1_AP_SDA
I2C0_AP_SDA
I2C0_AP_SCL
SPI_AP_TO_CODEC_SCLK_R
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
PP1V8_IO
I2C0_AP_SDA
PP1V8_IO
I2S_AP_TO_CODEC_MCLK1
I2S_CODEC_ASP3_TO_AP_DIN
I2S_AP_TO_CODEC_ASP3_DOUT
SPI_AP_TO_RACER_SCLK
I2S_AP_TO_SPKRAMP_TOP_MCLK
I2S_AP_TO_CODEC_ASP3_BCLK
I2S_AP_TO_CODEC_ASP3_LRCLK
PP1V8_IO
I2C4_AP_SCL
I2S_AP_TO_CODEC_MCLK1_R
I2S_AP_TO_SPKRAMP_TOP_MCLK_R
SPI_AP_TO_CODEC_SCLK
SPI_RACER_TO_AP_MISO
SPI_AP_TO_RACER_MOSI
SPI_AP_TO_RACER_SCLK_R
SPI_AP_TO_RACER_CS_L
SPI_AP_TO_CODEC_CS_L
AP_TO_RACER_REF_CLK_R
PP1V8_IO
I2C0_AP_SCL
I2C1_AP_SDA
I2C1_AP_SCL
I2C1_AP_SCL
I2C2_AP_SCL
I2C3_AP_SCL
PP1V8_S2
I2C3_AP_SDA
SPMI_PMU_BI_PMGR_SDATA
SPMI_PMGR_TO_PMU_SCLK_R SPMI_PMGR_TO_PMU_SCLK
CODEC_TO_AP_INT_L CCG2_TO_SMC_INT_L
I2C1_SMC_SDA
PMU_TO_SEP_DOUBLE_CLICK_DET
I2C4_AP_SCL
I2C4_AP_SDA
I2C4_AP_SDA
I2C0_SMC_SDA
PP1V8_IO
I2C2_AP_SDA
I2C2_AP_SCL
I2C0_SMC_SCL
PP1V8_S2
AP_TO_NAND_SYS_CLK
AP_TO_NAND_SYS_CLK_R
AP_TO_CCG2_SWCLK
AP_BI_CCG2_SWDIO
IKTARA_TO_SMC_INT
BOARD_ID3
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R
I2S_AP_TO_BB_DOUT
I2S_BB_TO_AP_DIN
I2C3_AP_SCL
I2C3_AP_SDA
I2C0_SMC_SCL
I2C1_SMC_SCL
I2C0_SMC_SDA
AP_TO_RACER_REF_CLK
I2C1_SMC_SDA
I2C1_SMC_SCL
PP1V8_IO
I2C4_AP_SDA
I2C4_AP_SCL
SOC: Serial
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
U1490 U1490335S00233
1 CRITICAL COMMON
MF
5%
4.7K
1/32W
01005
ROOM=SOC
20 
1/32W
MF
01005
ROOM=SOC
5%
4.7K
CRITICAL
ROOM=SOC
WLCSP
OMIT_TABLE
ROOM=SOC
20%
0.47UF
X5R
6.3V
01005
16 5 
0.00
0%
MF
01005
1/32W
ROOM=SOC
20 
ROOM=SOC
MF
01005
0.00
0%
1/32W
50 
MF
ROOM=SOC
01005
1%
1/32W
33.2
ROOM=SOC
MF
01005
4.7K
5%
1/32W
01005
ROOM=SOC
MF
4.7K
5%
1/32W
38 
47 4 
47 4 
50 
0.00
1/32W
0%
ROOM=SOC
01005
MF
50 
47 4 
48 10 
48 10 
2.2K
5%
1/32W
MF
ROOM=SOC
01005
ROOM=SOC
2.2K
01005
1/32W
MF
5%
50 42 10 
50 42 10 
16 5 4 
16 5 
16 
20 4 
50 47 23 22 21 10 
50 10 
49 33 10 
49 46 20 10 
50 47 23 22 21 10 
50 10 
49 33 10 
49 46 20 10 
38 
50 
50 5 
50 
38 
38 
38 
50 
50 
38 
50 
50 
50 
50 
38 
38 
38 
38 
2.2K
5%
1/32W
MF
01005
ROOM=SOC
1/32W
MF
01005
ROOM=SOC
5%
2.2K
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
2.2K
1/32W
5%
MF
01005
ROOM=SOC
2.2K
1/32W
5%
MF
01005
01005
1/32W
5%
2.2K
MF
ROOM=SOC
01005
5%
1/32W
2.2K
MF
ROOM=SOC
01005
ROOM=SOC
1/32W
2.2K
5%
MF
01005
MF
1/32W
5%
ROOM=SOC
2.2K
0.00
0%
ROOM=SOC
01005
MF
1/32W
1/32W
0.00
0%
01005
ROOM=SOC
MF
01005
1/32W
0.00
MF
0%
ROOM=SOC
MF
1%
33.2
1/32W
01005
ROOM=SOC
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
49 46 20 10 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
10 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
49 46 20 10 
49 33 10 
49 33 10 
50 42 10 
50 49 
48 47 46 38 22 20 17 14 12 10 
50 42 10 
10 
10 
10 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
50 10 
50 10 
50 47 23 22 21 10 
50 49 
48 47 46 38 22 20 17 14 12 10 
50 47 23 22 21 10 
48 10 
48 10 
43 35 34 32 30 
29 28 27 17 16 14 10 8 7 6 5 
10 
10 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_ITEM
IN
VSS
VCC
SCL SDA
NC
NC
NC
NC
NC
NC
OUT
NC
OUT
OUT
NC
NC
IN
OUT
BI
OUT
IN
IN
OUT
IN
BI
OUT
IN
OUT
NC
NC
NC
NC
OUT
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
NC
NC
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 6 OF 16
SPMI_SDATA
SPMI_SCLK
I2C0_SDA
I2C0_SCL
I2C1_SCL
I2C1_SDA
I2C2_SDA
I2C3_SCL
I2C3_SDA
SMC_I2CM0_SCL
SEP_SPI0_MISO
SMC_I2CM1_SDA
SMC_UART0_TXD
SEP_SPI0_SCLK
SEP_SPI0_MOSI
SEP_I2C_SCL
SEP_I2C_SDA
I2C2_SCL
SMC_UART0_RXD
SMC_I2CM0_SDA
SMC_I2CM1_SCL
DWI_CLK
NAND_SYS_CLK
DWI_DO
CLK24M_OUT
I2S0_BCLK
I2S0_LRCK
I2S0_DOUT
I2S1_LRCK
I2S1_BCLKI2S1_MCK
I2S0_DIN
I2S0_MCK
I2S2_MCK
I2S2_BCLK
I2S2_DIN
I2S1_DIN
I2S1_DOUT
I2S2_LRCK
I2S2_DOUT
SPI0_MISO
I2S3_MCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S3_LRCK
SPI0_SSIN
SPI1_SCLK
SPI1_SSIN
SPI1_MOSI
SPI1_MISO
SPI0_MOSI
SPI0_SCLK
SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI2_SSIN
SPI2_SCLK
SPI2_MOSI
SPI2_MISO
SPI3_SSIN
SOC - GPIO INTERFACES
11 OF 51
PP1V8_IO
PP1V8_IO
9.0.0
evt-1
15 OF 80
051-02221
21
R1500
P2
R5
AF4
AF5
N35
N36
M35
K36
D31
C32
B32
D30
B30
C28
B29
B28
M37
P36
L36
P34
AF2
AF3
A28
C30
D28
AC4
AB2
AK5
AK4
AK3
AJ6
AJ5
AJ4
AJ3
V3
V4
V5
U2
U4
U6
T2
T3
T4
T5
R2
R3
R4
P4
P6
A32
B33
D29
D32
C34
D33
L35
K34
K38
L37
N37
R35
P38
R36
T35
AL4
U1000
UART_BT_TO_AP_CTS_L 50 
UART_GNSS_TO_AP_CTS_L
ROOM=SOC
200K
NOSTUFF
PMU_TO_AP_PRE_UVLO_L
JULIET_PMU_TO_RIGEL_STROBE_R
WLAN_TO_AP_TIME_SYNC
UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD
UART_AP_TO_BT_RTS_L
1%
1/32W
MF
01005
UART_AP_TO_GNSS_RTS_L
UART_GNSS_TO_AP_RXD
PMU_TO_AP_BUTTON_POWER_KEY_L
PMU_TO_AP_BUTTON_VOL_DOWN_L
BOARD_REV1
BOARD_REV2
BOARD_REV3
BB_TO_AP_RESET_DETECT_L
AP_TO_BB_TIME_MARK
AP_TO_NFC_FW_DWLD_REQ
AP_TO_SPKRAMP_TOP_RESET_L
AP_TO_BT_WAKE
AP_TO_GNSS_WAKE
CAMPMU_TO_AP_IRQ_L
AP_TO_BB_IPC_GPIO1
AP_TO_BB_RESET_L
AP_TO_BB_COREDUMP
AP_TO_NFC_DEV_WAKE
AP_TO_DISPLAY_RESET_L
UART_AP_TO_ACCESSORY_TXD
UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_NFC_RTS_L
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_RTS_L
UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD
UART_AP_TO_GNSS_TXD
UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD
UART_NFC_TO_AP_CTS_L
UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_TXD
AP_TO_CAMPMU_RESET_L JULIET_PMU_TO_RIGEL_STROBE
BOARD_REV0
AP_TO_WLAN_DEVICE_WAKE
AP_TO_BBPMU_RADIO_ON_L
PMU_TO_AP_BUTTON_VOL_UP_L
SPKRAMP_TOP_TO_AP_INT_L
BOARD_ID0
AP_TO_RACER_RESET_L
PMU_HYDRA_TO_AP_FORCE_DFU
AP_TO_PMU_AMUX_SYNC
BOARD_ID4
DFU_STATUS
SOC: GPIO & UART
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
35 34 
20 6 4 
50 
28 
50 
50 
50 
50 
5 
4 
5 
50 
50 
28 
5 4 
48 
50 
50 
50 
50 
50 
50 
48 
48 
50 
50 
50 
50 
50 
48 
20 
20 
5 
5 
5 
5 
20 
5 
50 48 20 
50 
50 
50 
20 
50 
50 
50 
43 
50 
50 
50 
50 
50 
50 
ROOM=SOC
WLCSP
TMIT78B0-C4
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
OUT
NC
NC
IN
NC
NC
NC
NC
NC
IN
NC
IN
NC
NC
IN
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 5 OF 16
UART7_RXD
UART7_TXD
UART4_TXD
UART4_CTS*
UART3_CTS*
UART2_RTS*
UART1_RTS*
UART1_CTS*
UART0_TXD
UART0_RXD
UART1_TXD
UART2_CTS*
UART1_RXD
TMR32_PWM0
TMR32_PWM1
TMR32_PWM2
UART2_RXD
UART2_TXD
UART3_RXD
UART3_TXD
UART4_RTS*
UART4_RXD
UART3_RTS*
UART6_RXD
UART6_TXD
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_14
GPIO_12
GPIO_13
GPIO_11
GPIO_15
GPIO_20
GPIO_19
GPIO_16
GPIO_17
GPIO_18
GPIO_23
GPIO_24
GPIO_25
GPIO_22
GPIO_21
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_37
GPIO_36
REQUEST_DFU2
REQUEST_DFU1
SPI SCM
SOC - AOP
1.8V @ 15mA MAX
AOP I2C Pull-Ups
AOP_PDM_CLK4
I2C1 SCM
I2C0 SCM
12 OF 51
9.0.0
evt-1
16 OF 80
051-02221
21
R1603
21
R1604
2
1 C1691
2
1 C1690
2
1R1622
2
1R1623
2
1R1621
2
1R1620
AP
19
AP
17
AP
15
AP
13
AC2
AC5
BA18
AY19
BA17
AT15
AU11
AW8
BA8
AY8
AT14
AT21
AY17
AV20
AV8
AU10
AW7
AW17
AW18
BA16
AU19
BA15
BA13
AT19
BA14
AW9
AV10
AV9
BA9
AY14
BA12
AV18
AW14
AT18
BA10
AV17
BA11
AY13
AV15
AU17
AW13
AV14
AW12
AV13
AT17
AV16
AU16
AY11
AV12
AY10
AV11
AT16
AW11
AW10
AU13
AU14
AT11
U1000
21
R1601
21
R1602
AOP_TO_CODEC_RESET_L
AP_TO_MANY_BSYNC
PMU_TO_AOP_IRQ_L
SPKRAMP_BOT_ARC_TO_AOP_INT_L
AOP_TO_CODEC_CLP_EN
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
I2C1_AOP_SDA
I2C1_AOP_SCL
I2C0_AOP_SDA
I2C0_AOP_SCL
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
I2S_AOP_TO_CODEC_MCLK2_R
I2S_AOP_TO_CODEC_ASP2_DOUT
I2S_AOP_TO_CODEC_ASP2_LRCLK
I2S_CODEC_ASP2_TO_AOP_DIN
I2S_AOP_TO_CODEC_ASP2_BCLK
UART_AOP_TO_RACER_TXD
UART_RACER_TO_AOP_RXD
AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A
UART_AOP_TO_BB_TXD
UART_BB_TO_AOP_RXD
COMPASS_TO_AOP_INT
ALS_TO_AOP_INT_L
HALL3_TO_AOP_IRQ_L
PROX_BI_AP_AOP_INT_L
AOP_TO_SPKRAMP_BOT_ARC_RESET_L
RACER_TO_AOP_INT_L
ROMEO_TO_AOP_B2B_DETECT
PHOSPHORUS_TO_AOP_INT
SPI_AOP_TO_PHOSPHORUS_CS_L
ACCEL_GYRO_TO_AOP_INT
ACCEL_GYRO_TO_AOP_DATARDY
SPI_AOP_TO_ACCEL_GYRO_CS_L
AOP_TO_DDR_SLEEP1_READY
I2S_AOP_TO_CODEC_MCLK2
PP1V8_S2
HYDRA_TO_NUB_DOCK_CONNECT
CODEC_TO_AOP_GPIO2
HYDRA_TO_NUB_INT
SWD_AP_BI_NAND_SWDIO
SWD_AOP_BI_BB_SWDIO
SWD_AOP_BI_RACER_SWDIO
SWD_AOP_TO_MANY_SWCLK
PMU_TO_AOP_CLK32K
CODEC_TO_AOP_GPIO1
PP1V8_S2
HALL2_TO_AOP_IRQ_L
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
SPI_IMU_TO_AOP_MISO
SPI_AOP_TO_IMU_SCLK_R
SPI_AOP_TO_IMU_MOSI
I2C1_AOP_SDA
I2C1_AOP_SCL
I2C0_AOP_SDA
I2C0_AOP_SCL
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
SPI_AOP_TO_IMU_SCLK
SOC: AOP
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
01005
49.9
1%
MF
ROOM=SOC
1/32W
MF
1/32W
ROOM=SOC
1%
49.9
01005
50 
38 
20%
01005
X5R-CERM
6.3V
0.1UF
ROOM=SOCROOM=SOC
0201
CER-X5R
6.3V
20%
4UF
50 
36 
35 
50 41 
48 
48 
50 
50 
36 12 
36 12 
38 
38 
50 49 41 25 12 4 
50 49 41 25 12 4 
1.00K
5%
ROOM=SOC
1/32W
MF
01005
ROOM=SOC
01005
5%
MF
1.00K
1/32W
50 
50 
50 41 38 
50 49 41 38 
50 49 41 38 
49 41 38 
16 4 
50 
20 
50 16 4 
38 
38 
38 
50 
50 
26 4 
38 
38 
50 
50 
26 4 
26 4 
20 
50 28 21 20 8 
26 4 
26 4 
38 
50 41 
36 
26 
26 
26 4 
49 25 4 
14 4 
1/32W
01005
ROOM=SOC
5%
1.00K
MF
01005
1.00K
MF
5%
1/32W
ROOM=SOC
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
MF
1%
01005
1/32W
49.9
33.2
1/32W
MF
01005
ROOM=SOC
1%
50 49 
48 47 46 38 22 20 17 14 12 10 
50 49 
48 47 46 38 22 20 17 14 12 10 
50 49 41 25 12 4 
50 49 41 25 12 4 
36 12 
36 12 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
IN
NC
OUT
NC
BI
NC
NC
IN
NC
IN
OUT
IN
IN
IN
IN
BI
OUT
NC
IN
IN
BI
OUT
OUT
OUT
IN
IN
IN
OUT
BI
BI
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
BI
IN
OUT
SYM 7 OF 16
AOP_PDM_CLK0
RT_CLK32768
AOP_SWD_TCK_OUT
AOP_SWD_TMS0
AOP_SWD_TMS1
AOP_PDM_DATA1
SWD_TMS2
DOCK_ATTENTION
AOP_PDM_DATA0
SWD_TMS3
AOP_I2CM0_SCL
AOP_I2CM1_SDA
AOP_I2CM1_SCL
AOP_I2CM0_SDA
DOCK_CONNECT
AOP_FUNC_0
AOP_FUNC_1
AON_DDR_RESET*
AOP_FUNC_2
AOP_FUNC_7
AOP_FUNC_6
AOP_FUNC_12
AOP_FUNC_11
AOP_FUNC_10
AOP_FUNC_3
AOP_FUNC_9
AOP_FUNC_8
AOP_FUNC_5
AOP_FUNC_4
AOP_FUNC_19
AOP_FUNC_13
AOP_FUNC_18
AOP_FUNC_17
AOP_FUNC_16
AOP_FUNC_15
AOP_FUNC_14
AOP_FUNC_20
AOP_FUNC_21
AOP_FUNC_22
AOP_FUNC_23
AOP_FUNC_24
AOP_FUNC_26
AOP_SPI_MOSI
AOP_SPI_MISO
AOP_FUNC_25
AOP_SPI_SCLK
AOP_UART2_RXD
AOP_UART2_TXD
AOP_I2S0_BCLK
AOP_UART1_TXD
AOP_UART0_TXD
AOP_UART1_RXD
AOP_UART0_RXD
AOP_I2S0_DIN
AOP_I2S0_MCK
AOP_I2S0_DOUT
AOP_I2S0_LRCK
VD
DI
O
18
_A
O
P
VD
DI
O
18
_A
O
P
VD
DI
O
18
_A
O
P
VD
DI
O
18
_A
O
P
0.635V @ 2.6A MAX
0.765V @ 4.9A MAX
(Analog)
0.735V @ 0.6A MAX
1.01V @ 2.1A MAX
1.06V @ 1.1A MAX
0.675V @ 0.19A MAX
0.80V @ 0.63A MAX
0.8V @2.8A MAX
1.06V @ 18.3A MAX
0.8V @ 10.6A MAX
0.575V @ 3.4A MAX
1.06V @ 4.3A MAX
0.575V @ 1.4A MAX
1.2V @ 20mA MAX (SOC)
1.2V @ 7mA MAX (GPU)
1.2V @ 7mA MAX (CPU)
0.7V @ 75mA MAX
0.8V @ 10mA MAX
0.8V @ 6A MAX
1.06V @ 11.0A MAX
SOC - CPU, GPU & SOC RAILS
0.575V @ 2.7A MAX
(Analog)
0.8V @ 6mA MAX
0.8V @ 6mA MAX
13 OF 51
9.0.0
evt-1
17 OF 80
051-02221
2
1 C1761
2
1 C1760
4
3
2
1
C1764
4
3
2
1
C1763
4
3
2
1
C1762
2
1 C1794
4
3
2
1
C1793
4
3
2
1
C1792
4
3
2
1
C1791
2
1 C1723
2
1 C1722
2
1 C1721
2
1 C1720
4
3
2
1
C1773
2
1 C1750
4
3
2
1
C1772
4
3
2
1
C1707
4
3
2
1
C1713
2
1 C1703
2
1
C1702
4
3
2
1
C1706
4
3
2
1
C1705
4
3
2
1
C1712
4
3
2
1
C1711
4
3
2
1
C1704
4
3
2
1
C1710
4
3
2
1
C1709
4
3
2
1
C1708
2 1
XW1790
4
3
2
1
C1732
4
3
2
1
C1733
P23
Y27
Y21
Y25
Y19
W30
W28
W24
W22
W18
V27
V25
V21
V19
U30
U28
U24
U22
U18
U16
T27
T25
T21
T19
T15
T13
R28
R24
R22
R18
R16
R12
R10
P27
P25
P21
P19
P15
P13
N29
N18
N16
N12
N10
M21
M15
M13
L19
J20
G13
F22
AN24
AN22
AN12
AM25
AM13
AL30
AL28
AL24
AL22
AL18
AL16
AL12
AK27
AK25
AK21
AK19
AK15
AK13
AJ28
AJ24
AJ22
AJ18
AJ16
AH27
AH25
AG28
AG24
AG22
AF27
AF25
AE28
AE24
AE22
AD29
AD27
AD25
AD21
AD9
AC30
AC28
AC24
AC22
AB27
AB25
AB21
AA30
AA28
AA24
AA22
AA18
AA9
U1000
AN20
AN18
AN16
AM21
AM19
AM17
AM15
M29
G30
K23
K19
K11
H25
H21
H17
H13
N26
N23
N28
N24
N22
L24
M23
L28
L22
L18
L12
K29
K17
L16
J30
J26
J24
J22
J18
J12
H31
H23
H19
H15
H11
J28
G26
G24
G22
G20
F31
J16
F25
L20
K21
W14
Y15
Y13
V15
V13
U12
U10
AA10
U14
AF14
AE20
AC14
AC9
AB18
AA12
AH21
AH20
AH18
AH16
AH14
AH12
AH10
AG15
AG9
AF20
AE14
AD15
AC20
AB19
AB17
AB15
AB13
AB11
AA16
AA14
M20
L21
W16
U1000
4
3
2
1
C1738
4
3
2
1
C1739
4
3
2
1
C1737
4
3
2
1
C1736
4
3
2
1
C1781
21
XW1731
4
3
2
1
C1734
4
3
2
1
C1735
2
1 C1730
2
1 C1731
4
3
2
1
C1782
21
XW1760
2 1
XW1701
PP_SOC_S1
PP_GPU_SRAM
PP1V2_SOC
BUCK11_FB
BUCK2_FB
AP_CPU_PCORE_SENSE
AP_VDD_GPU_SENSE
TP_SOC_SENSE
BUCK1_FB
PP_GPUBUCK0_FB
PP_CPU_PCORE
PP0V8_SOC_FIXED_S1
PP_CPU_ECORE
PP0V7_VDD_LOW_S2
PP_CPU_SRAM
SOC: Power (1/3)
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
ROOM=SOC
4V
X5R
0201
4UF
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
6.3V
ROOM=SOC
CER-X5R
4UF
0201
20%
01005
0.1UF
ROOM=SOC
6.3V
X5R-CERM
20%
01005
6.3V
ROOM=SOC
0.1UF
X5R-CERM
20%
X5R-CERM
0.1UF
6.3V
ROOM=SOC
01005
20%
0402-D2X-1
ROOM=SOC
4V
X5R
20%
14UF
4UF
CER-X5R
6.3V
ROOM=SOC0201
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
4V
X5R
4UF
20%
0201
ROOM=SOCROOM=SOC
0201
X5R
4V
20%
4UF
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-10402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
4V
X5R
ROOM=SOC
14UF
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
X5R
0402-D2X-1
4V
20%
14UF
ROOM=SOC
0402-D2X-1
4V
X5R
20%
14UF
ROOM=SOC
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
20 18 
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
4 
20 4 
20 4 
0402-D2X-1
14UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
17 17 
17 
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
WLCSP
TMIT78B0-C4
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
SHORT-20L-0.05MM-SM
ROOM=SOC
NO_XNET_CONNECTION
OMIT
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
4UF
ROOM=SOC
4V
X5R
0201
20%
ROOM=SOC
4UF
X5R
0201
20%
4V
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
NO_XNET_CONNECTION
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
ROOM=SOC
OMIT
SHORT-20L-0.05MM-SM
17 
17 
19 14 9 7 
17 4 
17 4 
17 14 9 8 7 6 
18 
19 
17 
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
D
SIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
A
PAGE TITLE
2
 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUTOUT
OUT
SYM 9 OF 16
VDD_SOC_SENSE
VDD_SOC
SYM 8 OF 16
VDD_GPU
VDD_ECPU
VDD_FIXED_PLL_GPU
VDD_FIXED_PLL_SOC
VDD12_PLL_CPU
VDD12_PLL_GPU
VDD12_PLL_SOC
VDD_FIXED_CPU
VDD_CPU
VDD_LOW
VDD_CPU_SRAM
VDD_CPU_SENSE
VDD_GPU_SRAM
VDD_GPU_SENSE
1.8V @ 60mA MAX
DCS Voltage Sense ->
1.8V @ 1mA MAX
VDDQL Voltage Sense ->
(Analog)
1.06V - 1.17V @2.2A MAX
DDR IMPEDANCE CONTROL
0.6V @ 262mA MAX
0.8V @ 8mA MAX
0.8V @ 0.9A MAX
1.8V @ 1mA MAX
1.8V @ 200mA MAX
Place caps on SoC Corners
SOC - POWER SUPPLIES
1.06V - 1.17V @ (Inc in VDD2)
(Analog)
1.2V @ 16mA MAX
0.875V @ 0.8A MAX
0.730V @ 0.51A MAX
0.600V @ 0.35A MAX
1.8V @ 5.3mA MAX (CPU)
1.8V @ 1.1mA MAX (GPU)
1.8V @ 3.3mA MAX (SOC)
Place caps on SoC Corners
14 OF 51
9.0.0
evt-1
18 OF 80
051-02221
2
1 C1862
2
1 C1861
2
1 C1880
21
R1880
2
1 C1881
2
1 C1813
2
1 C1812
2
1 C1811
2
1 C1810
4
3
2
1
C1801
2
1 C1805
2
1 C1803
2
1 C1802
21
XW18702
1 C1870
2
1 C1860
2
1 C1863
2
1 C1804
2
1 C1833
2
1 C1832
2
1 C1831
V9
AF9
D23
F21
Y31
V31
AB31
AP25
AP23
J31
AD30
AJ12
G21
Y16
AJ9
AF21
T12
AN19
AN13
AT6
H12
U1000
2
1R1871
2
1R1870
C4
A4
V39
T39
P39
P31
K31
F39
D39
V1
T1
K9
H1
F9
F1
D1
AV39
AT39
AP39
AK31
AF39
AF31
AD39
AV1
AT1
AP9
AK9
AH1
AF1
AD1
T29
D9
AK29
AJ11
G34
E6
AN34
AR6
R30
K30
L10
F10
AK30
AE30
AP10
AJ10
W1
P1
N39
M1
K39
J1
H39
D38
C38
C3
C2
AW38
AW2
AV37
AV2
AP1
AN39
AM1
AK39
AJ1
AH39
AC39
AA38
AA2
Y37
Y3
B37
B3
AW37
AW3
AB37
AB3
N38
H34
H35
G35
E4
E5
E3
AM34
AN35
AM35
AJ2
AP6
AP5
AR5
U1000
R29
D8
AJ29
AK11
Y29
Y23
Y17
Y9
W26
W20
V29
V23
V17
U26
U20
T31
T23
T17
T11
R26
R20
R14
P29
P17
P11
N20
N14
M17
M11
F23
F19
AP24
AP21
AP11
AM23
AM11
AL26
AL20
AL14
AK23
AK17
AJ26
AJ20
AJ14
AH29
AH23
AG26
AF29
AF23
AE26
AD31
AD23
AC26
AB29
AB23
AB9
AA26
AA20
BA19
AY20
U1000
2
1 C1840
2
1 C1841
2
1 C1842
2
1 C1843
2
1 C1850
2
1 C1851
2
1 C1852
2
1 C1853
2
1 C1830
2
1R1863
2
1R1862
2
1R1861
2
1R1860
PP1V2_LPADC
PP0V6_VDDQL_S1
DDR3_RREF
DDR2_RREF
DDR1_RREF
DDR0_RREF
DDR0_ZQ
AOP_TO_DDR_SLEEP1_READY
LPADC_GND
PP1V8_S2
SYSTEM_ALIVE
DDR3_ZQ
PP1V8_S2
PP1V1_S2
PP1V8_LPOSC_S2
PP1V8_IO
PP0V8_SOC_FIXED_S1
PP1V8_IO
PP0V8_SOC_FIXED_S1
PP1V1_S2
PP1V2_SOC
PP_DCS_S1
PP1V8_IO
PP0V6_VDDQL_S1
SOC: Power (2/3)
SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb
ROOM=SOC
4V
X5R
0201
4UF
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
5%
ROOM=SOC
56PF
NP0-C0G-CERM
01005
25V
300
5%
1/32W
MF
ROOM=SOC
01005
ROOM=SOC
01005
6.3V
0.47UF
X5R
20%
4UF
CER-X5R
ROOM=SOC
6.3V
0201
20%
ROOM=SOC
CER-X5R
6.3V
4UF
0201
20%
4UF
CER-X5R
ROOM=SOC
6.3V
0201
20%
0402-0.1MM
26UF
ROOM=SOC
4V
X5R
20%
0402-D2X-1
ROOM=SOC
14UF
4V
X5R
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
ROOM=SOC
4V
X5R
0201
4UF
20%
ROOM=SOC
SHORT-20L-0.05MM-SM
OMIT
ROOM=SOC
X5R-CERM
6.3V
2.2UF
0201
20%
4UF
ROOM=SOC
4V
X5R
0201
20%
4UF
ROOM=SOC
4V
X5R
0201
20%
23 20 16 
4UF
ROOM=SOC
4V
X5R
0201
20%
12 4 
4UF
ROOM=SOC
4V
X5R
0201
20%
4UF
X5R
20%
ROOM=SOC
0201
4V
4UF
ROOM=SOC
4V
X5R
0201
20%
ROOM=SOC
WLCSP
TMIT78B0-C4
01005
MF
1/32W
1%
240
ROOM=SOC
01005
MF
1/32W
1%
240
ROOM=SOC
WLCSP
TMIT78B0-C4
ROOM=SOC
ROOM=SOC
WLCSP
TMIT78B0-C4
6.3V
2.2UF
X5R-CERM
ROOM=SOC
0201
20%
ROOM=SOC
6.3V
X5R-CERM
2.2UF
0201
20%
ROOM=SOC
2.2UF
X5R-CERM
6.3V
0201
20%
ROOM=SOC
2.2UF
6.3V
X5R-CERM