Simulador de Micro-Arquitetura

Prévia do material em texto

UNIVERSIDADE DO ESTADO DO RIO DE JANEIRO
 Centro de Tecnologias e Ciências
 Faculdade de Engenharia
 Departamento de Engenharia de Sistemas e Computação
 
Arquitetura de Computadores 
Profa. Luiza de Macedo Mourelle
Trabalho 
Simulador de Micro-Arquitetura
Nome: Rachel Reuters da Silva
E-mail: belchel@hotmail.com
Rio de Janeiro
2013
1. INTRODUÇÃO
Este trabalho visa consolidar os conhecimentos adquiridos em sala de aula sobre a micro-arquitetura [1]. A proposta é modelar uma das micro-arquiteturas discutidas (horizontal ou vertical), utilizando a linguagem de descrição de hardware VHDL [2]. A validação do modelo será feita através de simulação, utilizando o simulador MODELSIM [3]. Na Seção 2, será descrito o modelo de cada componente, juntamente com a respectiva validação funcional. Na Seção 3, serão apresentadas as informações necessárias à utilização do simulador.
2. DESCRIÇÃO DO MODELO
A especificação do modelo de cada componente da arquitetura mais horizontal escolhida, em VHDL, será descrita, devidamente comentada, em sub-seções. Para cada modelo, será apresentada a descrição do teste feito e a janela de simulação correspondente.
2.1 Multiplexador 
Um multiplexador é um circuito combinacional cuja finalidade é selecionar uma das entradas a partir de um controlador. 
2.1.1 Código VHDL do Multiplexador 2x1
Utilizando o modelo estrutural, o código do multiplexador 2x1 é: 
library ieee;
use ieee.std_logic_1164.all;
entity MUX2X1_ESTRU is
port (A,B,C:in bit; S:out bit);
end MUX2X1_ESTRU ;
architecture estrutural of MUX2X1_ESTRU is
component AND2
port (E1,E2:in bit; S: out bit);
end component;
component INV
port (E: in bit; S: out bit);
end component;
component OR2
port (E1,E2:in bit; S: out bit);
end component;
signal S1,S2,S3: bit;
begin
 P1:AND2 port map (B,C,S1);
 P2: INV port map (C,S2);
 P3: AND2 port map (S2,A,S3);
 P4: OR2 port map (S1,S3,S);
END estrutural;
entity AND2 is
port (E1,E2: in bit; S: out bit);
end AND2;
architecture fluxo of AND2 is
begin
 S <= E1 AND E2;
end fluxo;
entity INV is
port (E:in bit; S: out bit);
end INV;
architecture fluxo of INV is
begin
 S<= not (E);
end fluxo;
entity OR2 is
port (E1,E2: in bit; S: out bit);
end OR2;
architecture fluxo of OR2 is
begin
 S <= E1 OR E2;
end fluxo;
entity teste_estru is
end teste_estru;
architecture teste of teste_estru is
component MUX2X1_ESTRU
port (A,B,C:in bit;S:out bit);
end component;
signal sigA,sigB,sigC,digS:bit;
begin
comp: MUX2X1_ESTRU
port map (sigA,sigB,sigC,digS);
process
begin
 sigA <= '0','1' after 2 ns, '0' after 4 ns;
 sigB <= '1','0' after 3 ns, '1' after 5 ns;
 sigC <= '0','1' after 3 ns, '0' after 6 ns;
 wait;
end process;
end teste;
2.1.2 Simulação do Multiplexador 2x1
A Imagem da página seguinte mostra a simulação do multiplexador 2x1 no ModelSim.
2.1.3 Código VHDL do Multiplexador 16x1
Utilizando o modelo estrutural, o código do multiplexador 16x1 é: 
library ieee;
use ieee.std_logic_1164.all;
entity mux2x1_16 is
port (A,B:in bit_vector (15 downto 0);
 C: in bit;
 S:out bit_vector (15 downto 0));
end mux2x1_16;
architecture estrutural of mux2x1_16 is
component MUX2X1_ESTRU
port (A,B,C: in bit; S:out bit);
end component;
begin
 M15:MUX2X1_ESTRU port map (A(15),B(15),C,S(15));
 M14:MUX2X1_ESTRU port map (A(14),B(14),C,S(14));
 M13:MUX2X1_ESTRU port map (A(13),B(13),C,S(13));
 M12:MUX2X1_ESTRU port map (A(12),B(12),C,S(12));
 M11:MUX2X1_ESTRU port map (A(11),B(11),C,S(11));
 M10:MUX2X1_ESTRU port map (A(10),B(10),C,S(10));
 M09:MUX2X1_ESTRU port map (A(09),B(09),C,S(09));
 M08:MUX2X1_ESTRU port map (A(08),B(08),C,S(08));
 M07:MUX2X1_ESTRU port map (A(07),B(07),C,S(07));
 M06:MUX2X1_ESTRU port map (A(06),B(06),C,S(06));
 M05:MUX2X1_ESTRU port map (A(05),B(05),C,S(05));
 M04:MUX2X1_ESTRU port map (A(04),B(04),C,S(04));
 M03:MUX2X1_ESTRU port map (A(03),B(03),C,S(03));
 M02:MUX2X1_ESTRU port map (A(02),B(02),C,S(02));
 M01:MUX2X1_ESTRU port map (A(01),B(01),C,S(01));
 M00:MUX2X1_ESTRU port map (A(00),B(00),C,S(00));
end estrutural;
entity testbenchMUX2X1_16 is
end testbenchMUX2X1_16;
architecture teste of testbenchMUX2X1_16 is
component MUX2X1_16
port (A,B:in bit_vector (15 downto 0);C: in bit;
 S:out bit_vector (15 downto 0));
end component;
signal sigA,sigB,sigS:bit_vector (15 downto 0);
signal sigC:bit;
begin
comp:MUX2X1_16 port map (sigA,sigB,sigC,sigS);
process
begin
 sigA<="0000000000000000","1111111111111111" after 2 ns,"0000000000000000" after 4 ns;
 sigB<="1111111111111111","0000000000000000" after 3 ns,"1111111111111111" after 5 ns;
 sigC<='0','1' after 3 ns,'0' after 6 ns;
 wait;
end process;
end teste;
2.1.4 Simulação do Multiplexador 16x1
A Imagem da página seguinte mostra a simulação do multiplexador 16x1 realizada no ModelSim.
2.2 Decodificador
Dispositivo que desfaz a codificação, podendo, assim, a informação original que foi codificada, ser recuperada.
2.2.1 Código VHDL do Decodificador 4x16
Utilizando o modelo estrutural, o código do decodificador 4x16 é: 
library ieee;
use ieee.std_logic_1164.all;
entity DEC4x16_estru is 
 port (A: in bit_vector (3 downto 0); S:out bit_vector (15 downto 0));
end DEC4x16_estru;
architecture estrutural of DEC4x16_estru is
 component AND4
 port (E1,E2,E3,E4: in bit; S: out bit);
 end component;
 component INV
 port (E: in bit; S: out bit);
 end component;
 signal Sig: bit_vector(0 to 3);
 begin
 N0: INV port map (A(0),Sig(0)); --D
 N1: INV port map (A(1),Sig(1)); --C
 N2: INV port map (A(2),Sig(2)); --B
 N3: INV port map (A(3),Sig(3)); --A
 A0: AND4 port map (Sig(0),Sig(1),Sig(2),Sig(3),S(0));
 A1: AND4 port map (A(0),Sig(1),Sig(2),Sig(3),S(1));
 A2: AND4 port map (A(1),Sig(0),Sig(2),Sig(3),S(2));
 A3: AND4 port map (A(1),A(0),Sig(2),Sig(3),S(3));
 A4: AND4 port map (A(2),Sig(3),Sig(1),Sig(0),S(4));
 A5: AND4 port map (A(2),A(1),Sig(3),Sig(1),S(5));
 A6: AND4 port map (A(2),A(1),Sig(3),Sig(0),S(6));
 A7: AND4 port map (A(2),A(1),A(0),Sig(3),S(7));
 A8: AND4 port map (A(3),Sig(2),Sig(1),Sig(0),S(8));
 A9: AND4 port map (A(3),A(0),Sig(2),Sig(1),S(9));
 A10: AND4 port map (A(3),A(1),Sig(2),Sig(0),S(10));
 A11: AND4 port map (A(3),A(1),A(0),Sig(2),S(11));
 A12: AND4 port map (A(3),A(2),Sig(1),Sig(0),S(12));
 A13: AND4 port map (A(3),A(2),A(0),Sig(1),S(13));
 A14: AND4 port map (A(3),A(2),A(1),Sig(0),S(14));
 A15: AND4 port map (A(3),A(2),A(1),A(0),S(15)); 
 end estrutural;
 
entity AND4 is
port (E1,E2,E3,E4: in bit; S: out bit);
end AND4;
architecture fluxo of AND4 is
begin
 S <= E1 AND E2 AND E3 AND E4;
end fluxo;
entity INV is
port (E:in bit; S: out bit);
end INV;
architecture fluxo of INV is
begin
 S <= not (E);
end fluxo;
entity teste_dec_estru is
end teste_dec_estru;
architecture teste of teste_dec_estru is
 component DEC4x16_estru
 port (A: in bit_vector (3 downto 0); S:out bit_vector (15 downto 0));
 end component;
signal sigA: bit_vector (3 downto 0); 
signal sigS: bit_vector (15 downto 0);
begin
 comp:DEC4x16_estru port map (sigA,sigS);
 process
 begin
 sigA<="0000","0001" after 2 ns,"0010" after 4 ns,"0011" after 6 ns,"0100" after 8 ns,"0101" after 10 ns,"0110" after 12 ns,"0111" after 14 ns,"1000" after 16 ns,"1001" after 18 ns,"1010" after 20 ns,"1011" after 22 ns,"1100" after 24 ns,"1101" after 26 ns,"1110" after 28 ns,"1111" after 30 ns,"0000" after 32ns; 
 wait;
 end process;
end teste;
2.2.2 Simulação do Decodificador 4x16:
A Imagem da página seguinte mostra a simulação do decodificador 4x16 realizada no ModelSim.
2.3 Unidade Lógica e Aritmética
Circuito digital que realiza operações lógicas e aritméticas (somas, subtrações e funções lógicas).
2.3.1 Código VHDL da ALU 1 bit
Utilizando o modelo estrutural, o código da ALU de 1 bit é:
library ieee;
use ieee.std_logic_1164.all;
entity ALU_estru_1bit is
 port (A,B,F0,F1,Cin: in bit; S,Z,Cout: out bit);
end ALU_estru_1bit;
-- ALU(0):A , ALU(1): B, ALU(2): F0, ALU(3): F1
-- F0 F1
-- 0 0 = +
-- 0 1 = AND
-- 1 0 = A
-- 1 1 = NOT A
architecture estrutural of ALU_estru_1bit is
 component AND2
 port (E1,E2:in bit; S: out bit);
 end component;
 component AND3
 port (E1,E2,E3:in bit; S: out bit);
 end component;
 component AND4
 port (E1,E2,E3,E4:in bit; S: out bit);
 end component;
 component OR2
 port (E1,E2:in bit; S: out bit);
 end component;
 component OR4
 port (E1,E2,E3,E4:in bit; S: out bit);
 end component;
 component INV
 port (E: in bit; S: out bit);
 end component;
 component XOR2
 port (E1,E2: in bit;s:out bit);
 end component;
 
signal Sig : bit_vector (0 to 13);
begin
 P1: and2 port map(A,B,sig(0));
 P2: or2 port map (A,B,sig(1));
 P3: and2 port map (sig(1),Cin,sig(2));
 P4: or2 port map ( sig(2),sig(0), sig(5));
 P5: xor2 port map (sig(3),Cin, sig(4));
 p6: xor2 port map (A,B,sig(3));
 p7: inv port map (A, sig(6));
 p8: inv port map (F0,sig(7));
 p9: inv port map (F1,sig(8));
 p10: and3 port map ( sig(5),sig(7),sig(8),Cout); --saida do carry ouy
 p11: and3 port map (sig(4), sig(7),sig(8),sig(9)); -- saida da SOMA
 p12: and4 PORT MAP (sig(8),F0,B, A,sig(10)); -- saida AND
 p13: and3 port map (A,F1,sig(7),sig(11)); --saida A
 p14: and3 port map (sig(6),F0,F1,sig(12)); --saida NOT A
 p15: or4 port map (sig(9), sig(10),sig(11),sig(12),S); --Saida final
 p16: inv port map (B,sig(13));
 p17: and2 port map (sig(6),sig(13),Z);
end estrutural; 
entity AND2 is
 port (E1,E2: in bit; S: out bit);
end AND2;
architecture fluxo of AND2 is
 begin
 S <= E1 AND E2 ;
end fluxo;
entity AND3 is
 port (E1,E2,E3: in bit; S: out bit);
end AND3;
architecture fluxo of AND3 is
 begin
 S <= E1 AND E2 AND E3 ;
end fluxo;
entity AND4 is
 port (E1,E2,E3,E4: in bit; S: out bit);
end AND4;
architecture fluxo of AND4 is
 begin
 S <= E1 AND E2 and E3 AND E4 ;
end fluxo;
entity INV is
 port (E:in bit; S: out bit);
end INV;
architecture fluxo of INV is
 begin
 S<= not (E);
end fluxo;
entity OR2 is
 port (E1,E2: in bit; S: out bit);
end OR2;
architecture fluxo of OR2 is
 begin
 S <= E1 OR E2 ;
end fluxo;
entity OR4 is
 port (E1,E2,E3,E4: in bit; S: out bit);
end OR4;
architecture fluxo of OR4 is
 begin
 S <= E1 OR E2 or E3 or E4 ;
end fluxo;
entity XOR2 is
 port (E1,E2: in bit; S: out bit);
end xor2;
architecture fluxo of xor2 is
 begin
 S <= E1 XOR E2 ;
end fluxo;
entity teste_ALU_estru1bit is
end teste_ALU_estru1bit;
architecture teste of teste_ALU_estru1bit is
 component ALU_estru_1bit
 port (A,B,F0,F1,Cin: in bit; S,Z,Cout : out bit);
 end component;
 signal sigA,sigB,sigF0,sigF1,sigCin:bit;
 signal sigS,sigZ,sigCout:bit;
begin
 comp: ALU_estru_1bit
 port map (sigA,sigB,sigF0,sigF1,sigCin,sigS, sigZ,sigCout); 
 process 
 begin
 sigA<= '1','0' after 6 ns ;
 sigB<= '1','0' after 9 ns ;
 sigF0<='0','1' after 3 ns, '0' after 6 ns, '1' after 9 ns;
 sigF1<='0','1' after 3 ns ;
 sigCin<='0';
 
 wait;
 end process;
end teste;
 
2.3.2 Simulação da ALU de 1 bit:
A Imagem abaixo mostra a simulação da ALU de 1 bit realizada no ModelSim.
2.3.3 Código VHDL da ALU 16 bits:
Utilizando o modelo estrutural e a ALU de 1 bit, o código da ALU de 16 bits é:
library ieee;
use ieee.std_logic_1164.all;
-- port (A,B,F0,F1,Cin: in bit; S,Z,Cout: out bit);
entity alu_16bits is 
 port (AF,BF:in bit_vector (15 downto 0);
 F0F: in bit;
 F1F: in bit;
 NF: OUT bit; 
 ZTOTAL: out bit;
 SFIM:out bit_vector (15 downto 0));
end alu_16bits;
architecture estrutural of alu_16bits is
 component alu_estru_1bit
 port (A,B,F0,F1,Cin: in bit; S,Z,Cout: out bit);
 end component;
 component and16
 port (E1:in bit_vector(0 to 15); S: out bit);
 end component;
 component INV
 port (E: in bit; S: out bit);
 end component;
signal SigCout : bit_vector (15 downto 0);
signal SigZF : bit_vector (15 downto 0);
signal sigULTIMO: bit;
begin
 ALU15:alu_estru_1bit port map (AF(15),BF(15),F0F,F1F,sigCout(14),sigULTIMO,sigZF(15),sigCout(15));
 ALU14:alu_estru_1bit port map (AF(14),BF(14),F0F,F1F,sigCout(13),SFIM(14),sigZF(14),sigCout(14));
 ALU13:alu_estru_1bit port map (AF(13),BF(13),F0F,F1F,sigCout(12),SFIM(13),sigZF(13),sigCout(13));
 ALU12:alu_estru_1bit port map (AF(12),BF(12),F0F,F1F,sigCout(11),SFIM(12),sigZF(12),sigCout(12));
 ALU11:alu_estru_1bit port map (AF(11),BF(11),F0F,F1F,sigCout(10),SFIM(11),sigZF(11),sigCout(11));
 ALU10:alu_estru_1bit port map (AF(10),BF(10),F0F,F1F,sigCout(9),SFIM(10),sigZF(10),sigCout(10));
 ALU09:alu_estru_1bit port map (AF(9),BF(9),F0F,F1F,sigCout(8),SFIM(9),sigZF(9),sigCout(9));
 ALU08:alu_estru_1bit port map (AF(8),BF(8),F0F,F1F,sigCout(7),SFIM(8),sigZF(8),sigCout(8));
 ALU07:alu_estru_1bit port map (AF(7),BF(7),F0F,F1F,sigCout(6),SFIM(7),sigZF(7),sigCout(7));
 ALU06:alu_estru_1bit port map (AF(6),BF(6),F0F,F1F,sigCout(5),SFIM(6),sigZF(6),sigCout(6));
 ALU05:alu_estru_1bit port map (AF(5),BF(5),F0F,F1F,sigCout(4),SFIM(5),sigZF(5),sigCout(5));
 ALU04:alu_estru_1bit port map (AF(4),BF(4),F0F,F1F,sigCout(3),SFIM(4),sigZF(4),sigCout(4));
 ALU03:alu_estru_1bit port map (AF(3),BF(3),F0F,F1F,sigCout(2),SFIM(3),sigZF(3),sigCout(3));
 ALU02:alu_estru_1bit port map (AF(2),BF(2),F0F,F1F,sigCout(1),SFIM(2),sigZF(2),sigCout(2));
 ALU01:alu_estru_1bit port map (AF(1),BF(1),F0F,F1F,sigCout(0),SFIM(1),sigZF(1),sigCout(1));
 ALU00:alu_estru_1bit port map (AF(0),BF(0),F0F,F1F,'0',SFIM(0),sigZF(0),sigCout(0));
 P1: and16 port map (sigZF,ZTOTAL);
 P2: inv port map ( sigULTIMO, NF); 
 SFIM(15)<=sigULTIMO; 
 
end estrutural;
entity and16 is
 port (E1:in bit_vector(0 to 15); S: out bit);
end and16;
architecture fluxo of and16 is
 begin
 S<= E1(0) AND E1(1) AND E1(2) AND E1(3) AND E1(4) AND E1(5) AND E1(6) AND E1(7) AND E1(8) 
 AND E1(9) AND E1(10) AND E1(11) AND E1(12) AND E1(13) AND E1(14) AND E1(15) ;
END fluxo; 
entity INV is
 port (E:in bit; S: out bit);
end INV;
architecture fluxo of INV is
 begin
 S<= not (E);
end fluxo;
entity teste_alu_16 is
end teste_alu_16;
architecture teste of teste_alu_16 is
 component alu_16bits
 port (AF,BF:in bit_vector (15 downto 0);
 F0F: in bit;
 F1F: in bit;
 NF: OUT bit; 
 ZTOTAL: out bit;
 SFIM:out bit_vector (15 downto 0));
 end component;
signal sigA,sigB,sigSfim:bit_vector (15 downto 0);
signal sigF0,sigF1,sigNF,sigZTOTAL:bit;
begin
 comp:alu_16bits port map (sigA,sigB,sigF0,sigF1,sigNF,sigZTOTAL,sigSfim);
 process
 begin
 sigA<="0000000000000000","1111111111111111" after 2 ns,"0000000000000000" after 4 ns;
 sigB<="1111111111111111","0000000000000000" after 3 ns,"1111111111111111" after 5 ns;
 sigF0<='0','1' after 3 ns,'0' after 6 ns;
 sigF1<='0','0' after 3 ns,'1' after 8 ns;
 wait;
 end process;
end teste;
2.3.4 Simulação da ALU de 16 bits:
A Imagem na página seguinte mostra a simulação da ALU de 16 bits realizada no ModelSim.
2.4 Deslocador
O deslocador pode deslocar bits para direita ou para a esquerda.
2.4.1 Código VHDL do deslocador:
Utilizando o modelo algorítimico, o código do deslocador é:
library ieee;
use ieee.std_logic_1164.all;
entity Desloc_algo is
 port(ALU: in bit_vector(15 downto 0);
 SH: in bit_VECTOR(1 downto 0);
 S: out bit_vector(15 downto 0));
 end Desloc_algo ;
 
 architecture algoritmica of Desloc_algo is
 begin 
 process (ALU,SH)
 begin
 if (SH = "00") 
 then S <= ALU; 
 elsif (SH="01")
 then S<= ((ALU) srl 1);
 elsif (SH="10")
 then S<= ((ALU) sll 1);
 else 
 null;
 end if;
 end process;
end algoritmica;
entity test_desloc_algo is
end test_desloc_algo;
architecture teste of test_desloc_algo is
 component Desloc_algo
 port(ALU: in bit_vector(15 downto 0);
 SH: in bit_vector(1 downto 0);
 S: out bit_vector(15 downto 0));
 end component;
 
signal sigA,sigS:bit_vector(15 downto 0);
signal sigSH: bit_vector(1 downto 0);
begin
 comp: Desloc_algo port map (sigA,sigSH,sigS);
 process
 begin
 sigA<="0000000000000000","1111111111111111" after 2 ns;
 sigSH<="00","01" after 4 ns,"11" after 6 ns, "10" after 8 ns;
 wait;
 end process;
end teste;
2.4.2 Simulação do deslocador:
A Imagem seguinte mostra a simulação do deslocador realizada no ModelSim.
2.5 Lógica de Microsequenciamento
Circuito em que se verifica se deve ou não haver um desvio.
2.5.1 Código VHDL da Lógica de Microsequenciamento:
Utilizando o modelo de fluxo de dados, o código do circuito de Lógica e Microsequenciamento é:
library ieee;
use ieee.std_logic_1164.all;
entity microSeq_fluxo is
 port (Neg,Zero: in bit; Cond: in bit_vector(0 to 1); S: out bit);
end microSeq_fluxo;
architecture fluxo of microSeq_fluxo is
 begin
 S <= ((Cond(0) AND Neg) OR (Cond(1) AND Zero) OR (Cond(0) AND Cond(1))); 
end fluxo;
 
entity teste_microSeq_fluxo is
end teste_microSeq_fluxo;
architecture teste of teste_microSeq_fluxo is
 component microSeq_fluxo
 port (Neg,Zero: in bit; Cond: in bit_vector(0 to 1); S: out bit);
 end component;
 signal sigNeg,sigZero,sigS: bit;
 signal sigCond: bit_vector (0 to 1);
begin
 comp: microSeq_fluxo port map (sigNeg,sigZero, sigCond, sigS);
 process
 begin
 sigNeg<= '0','1' after 2 ns, '0' after 6 ns;
 sigZero<= '1','0' after 2 ns, '1' after 4 ns , '0' after 6 ns;
 sigCond<="01" after 2 ns, "00" after 4 ns, "11" after 6 ns;
 wait;
 end process;
end teste;
2.5.2 Simulação da Lógica de Microsequenciamento:
A Imagem da página seguinte mostra a simulação da Lógica de Microsequenciamento realizada no ModelSim.
2.6 Flip Flop D
O flip-flop D possui uma entrada, que é ligada diretamente à saída quando o clock é mudado. Independentemente do valor atual da saída, ele irá assumir o valor 1 se D = 1 quando o clock for mudado ou o valor 0 se D = 0 quando o clock for mudado.
2.6.1 Código VHDL do Flip Flop D:
Utilizando o modelo algorítmico, o código do Flip Flop D é:
library ieee;
use ieee.std_logic_1164.all;
entity ffD is
 port(RST,CLK:in bit;
 D: in std_logic;
 Q,NQ: out std_logic);
end ffD;
architecture algoritmica of ffD is
begin
 process (RST,D,CLK) begin
 if ( RST = '1' ) then
 Q<= '0';
 NQ <= '1';
 elsif ( CLK = '1' and CLK'event ) then 
 Q <= D;
 NQ <= not D;
 end if;
 end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity teste_ffD1 is
end teste_ffD1;
architecture teste of teste_ffD1 is
 component ffD
 port(RST,CLK:in bit;
 D: in std_logic;
 Q,NQ: out std_logic);
 end component;
 signal sigRST, sigCLK: bit;
 signal sigD,sigQ,sigNQ :std_logic ;
begin
 comp:ffD port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
process 
 begin
 sigCLK <= not (sigCLK) after 3 ns;
 sigD<='0','1' after 2 ns;
 sigRST<='0', '1' after 4 ns;
 wait for 5 ns;
 end process;
end teste;
2.6.2 Simulação do Flip Flop D:
A Imagem seguinte mostra a simulação do Flip Flop D realizada no ModelSim.
2.7 Registrador de 16 bits
A fim de armazenar alguma informação, torna-se necessária a utilização de registradores. 
2.7.1 Código VHDL do Registrador de 16 bits:
Utilizando o modelo estrutural e vários flip flops D, o código do Registrador de 16 bits é:
library ieee;
use ieee.std_logic_1164.all;
entity ffD16 is
 port(RST,CLK:in bit;
 D: in std_logic_vector(15 downto 0);
 Q,NQ: out std_logic_vector(15 downto 0));
end ffD16;
architecture estru_ffD16 of ffD16 is
 component ffD
 port(RST,CLK:in bit;
 D: in std_logic;
 Q,NQ: out std_logic);
 end component;
begin
 GEN:for I in 15 downto 0 generate
 ff : ffD port map (RST, CLK, D(I), Q(I),NQ(I));
 end generate ;
end estru_ffD16;
library ieee;
use ieee.std_logic_1164.all;
entity teste_ffD16 is
end teste_ffD16;
architecture teste of teste_ffD16 is
 component ffD16
 port(RST,CLK:in bit;
 D: in std_logic_vector(15 downto 0);
 Q,NQ: out std_logic_vector(15 downto 0));
 end component;
 signal sigRST, sigCLK: bit;
 signal sigD,sigQ,sigNQ :std_logic_vector(15 downto 0) ;
begin
 comp:ffD16 port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
 
process 
 begin
 sigCLK <='0', not (sigCLK) after 3 ns;
 wait for 5 ns;
end process;
 
process 
 begin
 sigD<="1011100010111001","0100001000001000" after 2 ns,"0000001000010001" after 10 ns;
 sigRST<='0', '1' after 4 ns;
 wait ;
end process;
end teste;
2.7.2 Simulação do Registrador de 16 bits:
A Imagem seguinte mostra a simulação do Registrador de 16 bits realizada no ModelSim.
2.8 Registrador de Microinstrução (MIR)
A fim de armazenar as microinstruções, um registrador é utilizado apenas com essa função.
2.8.1 Código VHDL do MIR:
Utilizando o modelo estrutural e flip flops D, o código do Registrador de 16 bits é:
library ieee;
use ieee.std_logic_1164.all;
entity MIR is
 port(RST,CLK:in bit;
 D: in std_logic_vector(31 downto 0);
 Q,NQ: out std_logic_vector(31 downto 0));
end MIR;
architecture estru_MIR of MIR is
 component ffD
 port(RST,CLK:in bit;
 D: in std_logic;
 Q,NQ: out std_logic);
 end component;
begin
 GEN:for I in 31 downto 0 generate
 ff : ffD port map (RST, CLK, D(I), Q(I),NQ(I));
 end generate ;
end estru_MIR;
library ieee;
use ieee.std_logic_1164.all;
entity teste_MIR is
end teste_MIR;
architecture teste of teste_MIR is
 component MIR
 port(RST,CLK:in bit;
 D: in std_logic_vector(31 downto 0);
 Q,NQ: out std_logic_vector(31 downto 0));
 end component;
signal sigRST, sigCLK: bit;
signal sigD,sigQ,sigNQ :std_logic_vector(31 downto 0) ;
begin
 comp:MIR port map (sigRST, sigCLK, sigD,sigQ,sigNQ);
process
begin
 sigCLK <='0', not (sigCLK) after 1 ns;
wait for 2 ns;
end process;
process
begin
 sigD<="10111000101110011011100010111001","01000010000010000100001000001000" after 2 ns,"00000010000100010000001000010001" after 10 ns;
 sigRST<='0', '1' after 4 ns;
 wait ;
end process;
end teste;
2.8.2 Simulação do MIR:
A Imagem da página seguinte mostra a simulação do MIR realizada no ModelSim
2.9 MAR 
Registrador cuja finalidade é armazenar os endereços.
2.9.1 Código VHDL do MAR:
Utilizando o modelo algorítmico, o código do MAR de 16 bits é:
library ieee;
use ieee.std_logic_1164.all ;
entity MAR is
 port (Entrada : in std_logic_vector(15 downto 0);
 CLK,Flag:in bit;
 Saida: out std_logic_vector(15 downto 0) 
 );
end MAR;
architecture algo_MAR of MAR is
 begin
 process (CLK,Flag)
 begin
 if (Flag = '1' and CLK = '1' and CLK'event) then
 Saida <= Entrada;
 end if;
 end process;
 end algo_MAR;
 
library ieee ;
use ieee.std_logic_1164.all ;
entity teste_mar is 
end teste_mar;
architecture teste of teste_mar is
 component MAR
 port(Entrada : in std_logic_vector(15 downto 0);
 CLK,Flag:in bit;
 Saida: out std_logic_vector(15 downto 0) 
 );
 end component;
 signal sigIN, sigOUT: std_logic_vector(15 downto 0);
 signal sigCLK, sigF: bit;
 begin
 comp: MAR port map (sigIN,sigCLK,sigF,sigOUT); 
 process 
 begin
 sigCLK <= not(sigClk) after 1 ns;
 wait for 2 ns;
 end process;
 
 process
 begin
 sigF <= '1', '0' after 3 ns, '1' after 5 ns ;
 sigIN <= "1010001010001011","0001000100001101" after 3 ns ,"0000001111010111" after 6 ns ;
 wait;
 end process;
end teste;
2.9.2 Simulação do MAR:
A Imagem seguinte mostra a simulação do MAR realizada no ModelSim.
2.10 MBR 
Registrador cuja finalidade é armazenar os dados.
2.10.1 Código VHDL do MBR:
Utilizando o modelo algorítmico, o código do MBR de 16 bits é:
library ieee ;
use ieee.std_logic_1164.all;
entity MBR is
 port(barramento: inout std_logic_vector(15 downto 0);
 toCPU: out std_logic_vector(15 downto 0);
 fromCPU: in std_logic_vector(15 downto 0);
 clock,rd,wr,controle : in bit);
end MBR;
architecture algoritmicaof MBR is
begin
 process(controle, clock, rd,wr)
 begin
 if (clock='1' and clock'event) then
 if (controle = '1' ) then
 if ( wr ='1') then
 barramento <= fromCPU;
 else
 barramento<="ZZZZZZZZZZZZZZZZ";
 end if;
 elsif (rd = '1') then
 toCPU <= barramento;
 end if;
 end if;
end process;
end algoritmica;
library ieee;
use ieee.std_logic_1164.all;
entity teste_MBR is
end teste_MBR;
architecture testbench of teste_MBR is
 component MBR is
 port(barramento: inout std_logic_vector(15 downto 0);
 toCPU: out std_logic_vector(15 downto 0);
 fromCPU: in std_logic_vector(15 downto 0);
 clock ,rd,wr,controle: in bit);
 end component;
signal sigClk,sigRD,sigCTRL,sigWR: bit;
signal sigBarramento,sigtoCPU,sigfromCPU: std_logic_vector (15 downto 0);
begin
 comp: MBR port map (sigBarramento,sigtoCPU,sigfromCPU,sigCLK,sigRD,sigWR,sigCTRL);
process
begin
 sigClk <= not (sigClk) after 1 ns;
wait for 2 ns;
end process;
process
begin
 sigCTRL <= '1','0' after 6 ns;
 sigRD <= '0','1' after 5 ns,'0' after 10 ns;
 sigWR <= '1','0' after 6 ns;
 sigfromCPU <= "1010101010101010","1111111111111111" after 5 ns;
wait;
end process;
end testbench;
2.10.2 Simulação do MBR:
A Imagem da página seguinte mostra a simulação do MBR realizada no ModelSim.
2.11 Memória de Controle
Registrador cuja finalidade é armazenar as microinstruções.
2.11.1 Código VHDL da Memória de Controle:
Utilizando o modelo algorítmico, o código da Memória de Controle é:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MC is
	port(	
	 endereço:	in std_logic_vector(7 downto 0);
		micro_instru:	out std_logic_vector(31 downto 0)
	);
end MC;
architecture algo_MC of MC is
 type vetor_microinstrucoes is array(0 to 255) of std_logic_vector(31 downto 0);
 constant microinstrucoes : vetor_microinstrucoes := 
 (
 "00010000110000000000000000000000",
 "00000000010100000110000000000000",
 "10110000000100110000000000011100",
 "00100100000101000011001100010011",
 "00110100000101000000010000001011",
 "00110000000000000000010000001001",
 "00010000110000000011000000000000",
 "00010000010000000000000000000000",
 "11110000000100010000000000000000",
 "00010001101000000011000100000000",
 "01110000001000000000000000000000",
 "00110000000000000000010000001111",
 "00010000110000000011000000000000",
 "00010000010000000000000000000000",
 "11100000000100010001000000000000",
 "00010000110000000011000000000000",
 "00000000010100010110000100000000",
 "10011000000110100000000000000000",
 "01100000000100011010000100000000", 
 "00001000000110101000001100010011", 
 "00000000110010101010001100010011", 
 "00000000010010101010001100010011", 
 "10011000000110101010001100010011", 
 "01100000000100011010000100000000", 
 "01100000000000000000000000000000",
 "00110000000000000000010000011011",
 "10011000000110101010001100010011",
 "01110000000100010011100000000000",
 "00100100000101000011001101011000",
 "00110010000101000000010000100011",
 "00110000000000000000010000100001",
 "00000000000001010010001100000000",
 "01100000110000001011000000000111",
 "00000000000001010010001100000000",
 "11110001100000001010000100001010",
 "00110000000000000000010000001101",
 "00000000000001010010001100000000",
 "01100000110000001011000000001101",
 "00000000000001010010001100000000",
 "01100000110000001011000000010000",
 "00110100000101000000100000101110",
 "00110000000000000000010000101100",
 "00110000000000000000000100010110",
 "01100000000000000000000000000000",
 "01010000000000000000000100010110",
 "01101000000100000011100000000000",
 "00110100000101000000010000110010",
 "00000000000100100010011100000000",
 "00010001101000000011000000000000",
 "01101000001100000011010000000000",
 "00110100000101000000010001000001",
 "00110100000101000000010001000001",
 "00110000000000000000001000111000",
 "00010000110000000001000000000100",
 "00000000010100100010011100000000",
 "01100000101000000100000000001010",
 "00000000110101000100011100000000",
 "00000000010000000000000000000000",
 "01100000101000000001000000001010",
 "00110000000000000000010000111110",
 "00000000000100100010011100000000",
 "01110001101000000010000100001010",
 "00000000110100100010011000000000",
 "00000000010000000000000000000000",
 "11110000000100010000000000000000",
 "00110100000101000000010001001001",
 "00110000000101000000010001000110",
 "00000000110100100010011000000000",
 "00000000010000000000000000000000",
 "11110000000100000000000000000000",
 "00010000000110100000000100000000",
 "00010000000100010000001000000000",
 "01100000000100100010101000000000",
 "00110000000000000000010000000000",
 "00110000000000000000010000000000",
 "00001000000110100011100100000000",
 "00001000000110100011100100000000",
 "01100000000100101010001000000000",
 "00001000000110100011100000000000",
 "00011000000110100000101000000000",
 "01100000000110101010011001001011", 
others=>(others=>'0')		
 );
signal instru: std_logic_vector(31 downto 0);
begin					 
 process(endereço)
 begin
 instru <= microinstrucoes(conv_integer(endereço)); 
 end process;
 micro_instru <= instru;
end algo_MC;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity teste_MC is
end teste_MC;
architecture teste of teste_MC is
 component MC
 	port(	
	 endereço:	in std_logic_vector(7 downto 0);
		micro_instru:	out std_logic_vector(31 downto 0)
	);
 end component;
 signal sigEND: std_logic_vector(7 downto 0);
 signal sigMIC: std_logic_vector(31 downto 0) ;
begin
 comp: MC
 port map (sigEND,sigMIC); 
 process 
 begin
 sigEND<= "00000010", "00000001" after 3 ns ;
 wait;
 end process;
end teste;
2.11.2 Simulação da Memória de Controle:
A Imagem da página seguinte mostra a simulação da Memória de Controle realizada no ModelSim.
2.12 Latch 
Armazenamento assíncrono de informação.
2.12.1 Código do Latch de 16 bits
Utilizando o modelo algorítmico, o código da Latch de 16 bits é:
library ieee ;
use ieee.std_logic_1164.all;
entity latch_16bits is
generic(n: natural :=16);
port(	entrada:	in std_logic_vector(n-1 downto 0);
	clock:		in std_logic;
	saida:	out std_logic_vector(n-1 downto 0)
	);
end latch_16bits;
architecture algoritmica of latch_16bits is
begin
process(entrada, clock)
begin
 if (clock='1' and clock'event) then
	saida <= entrada;
 end if;
end process;	
end comportamental;
library ieee ;
use ieee.std_logic_1164.all;
entity tb_latch_32bits is
end tb_latch_32bits;
architecture teste of tb_latch_32bits is
component latch_32bits
 generic(nbits: natural:=32);
 port(
 entrada: in std_logic_vector(nbits-1 downto 0);
 clock: in std_logic;
 saida:out std_logic_vector(nbits-1 downto 0)
 );
end component;
signal ent,s:std_logic_vector(31 downto 0);
signal clock:std_logic;
begin
 reg:latch_32bits port map(ent,clock,s);
 process
 begin
 clock <= '1', '0' after 10 ns, '1' after 20 ns, '0' after 30 ns, '1' after 40 ns, '0' after 50 ns;
 ent <= x"00000000", x"00010001" after 5 ns, x"01010101" after 20 ns, x"00A100A1" after 25 ns; 
 wait;
 end process;
end teste;
2.13 Divisor de Ciclos
O objetivo desse circuito é a divisão de subciclos. 
2.13.1 Código do Divisor de Ciclos
Utilizando o modelo algorítmico, o código do Divisor de Ciclos é:
library ieee ;
use ieee.std_logic_1164.all;
entity divisor_ciclos is
generic(qt_ciclos: natural := 4);
port(	
 ciclo:	out std_logic_vector(qt_ciclos DOWNTO 1);
 clock: in std_logic
	);
end divisor_ciclos;
architecture comportamental of divisor_ciclos is
 signal ciclo_tmp : std_logic_vector(qt_ciclos+1 DOWNTO 1) := "00001" ;
begin 
 process(clock)
 begin
 if (clock'event) then
	for i in qt_ciclos downto 1 loop
	 ciclo_tmp(i)<=ciclo_tmp(i-1);
	end loop;
 	 if (ciclo_tmp(qt_ciclos+1)= '1') then
	 ciclo_tmp <= "00001";
 	 end if;
 end if;
end process;
end architecture;
library ieee ;
use ieee.std_logic_1164.all ;
entity tb_gsc is
end tb_gsc;
architecture teste of tb_gsc is
component divisor_ciclos
 generic(qt_ciclos: natural := 4);
	port(	
	ciclo:	out std_logic_vector(qt_ciclos DOWNTO 1);
	clock: in std_logic
	);
end component;
component relogio
 generic(meio_periodo: std.STANDARD.TIME :=5 ns);
 port(	
	saida:	out std_logic
	);
end component;
signal clk:std_logic;
signal ciclos:std_logic_vector(4 downto 1);
begin
 rel:relogio port map (clk);
 divisor:divisor_ciclos port map(ciclos, clk);
 process(clk)
 begin
 end process;
end teste;
2.14 Incrementador
O objetivo desse circuito é incrementar um sinal.
2.14.1 Código do Incrementador
Utilizando o modelo algorítmico, o código do Divisor de Ciclos é:
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tb_incrementador is
end tb_incrementador ;
architecture teste OF tb_incrementador IS
component incrementador
 generic(nbits: natural :=8);
 port(
	entrada : in std_logic_vector(nbits-1 DOWNTO 0);
	vaium : out std_logic;
	saida : out std_logic_vector(nbits-1 DOWNTO 0)
	);
end component;
signal ent,s:std_logic_vector(7 downto 0);
signal vai:std_logic;
begin
 inc:incrementador port map(ent,vai,s);
 process
 begin
 ent <= x"00", x"10" after 20 ns;
 wait;
 end process;
end teste;
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity incrementador is
 	generic(nbits: natural :=8);
	port(
		entrada : in std_logic_vector(nbits-1 DOWNTO 0);
		vaium : out std_logic;
		saida : out std_logic_vector(nbits-1 DOWNTO 0)
	);
end incrementador;
architecture comportamental OF incrementador IS
 signal saida_tmp : std_logic_vector(nbits DOWNTO 0);
begin
	process(entrada)
	begin
 saida_tmp <= entrada+"000000001";
	end process;
 saida <= saida_tmp(nbits-1 downto 0);
 vaium <= saida_tmp(nbits);
end comportamental;
2.15 Processador
Utilizando a microarquitetura horizontal :
2.15.1 Código doProcessador
Utilizando o modelo estrutural e todos os componentes indicados acima e mostrados anteriormente, o código do Processador é:
library ieee;
use ieee.std_logic_1164.all;
entity arq_horizontal is
 generic(nbits: natural :=16);
 port(
	barramentoEndereco : OUT std_logic_vector (nbits-1 DOWNTO 0);
	barramentoDeDados : INOUT std_logic_vector (nbits-1 DOWNTO 0);
	RD : OUT std_logic ;
	WR : OUT std_logic
	);
end arq_horizontal;
architecture estrutural of arq_horizontal is 
 component registrador_16bits
	port(	
	entrada:	in std_logic_vector(15 downto 0);
	clock:	in std_logic;
 carregar:	in std_logic;
	limpar:	in std_logic;
	ativa_saida_a: in std_logic;
	ativa_saida_b: in std_logic;
	saida_barramento_a:	out std_logic_vector(15 downto 0);
	saida_barramento_b:	out std_logic_vector(15 downto 0)
	 );
 end component;
	
 component latch_16bits 
	port(	entrada:	in std_logic_vector(15 downto 0);
	clock:		in std_logic;
	saida:	out std_logic_vector(15 downto 0)
		);
 end component;
	
 component alu_16bits
	port (AF,BF:in std_logic_vector (15 downto 0);
 F0F: in std_logic;
 F1F: in std_logic;
 NF: OUT std_logic; 
 ZTOTAL: out std_logic;
 SFIM:out std_logic_vector (15 downto 0));
 end component;
	
 component Desloc_algo
	port(ALU: in std_logic_vector(15 downto 0);
 SH: in std_logic_vector(1 downto 0);
 S: out std_logic_vector(15 downto 0));
	end component;
	
 component DEC4X16_fluxo
 port (A,B,C,D:in std_logic; S: out std_logic_vector (0 to 15));
 end component;
	
 component gsc
 port (sclock1, sclock2, sclock3, sclock4: out std_logic); 
 end component;
 
 component lms
 port(	
	N : in std_logic ;
 Z : in std_logic ;
 COND : in std_logic_vector(1 DOWNTO 0);
 DESVIAR : out std_logic
	 );
 end component;
 
 component mux2x1_16
	 port (A,B:in std_logic_vector (15 downto 0);
 C: in std_logic;
 S:out std_logic_vector (15 downto 0));
 end component;
 
 component mux2x1_8bits
	PORT(
 entrada1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
 entrada2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
 controle : IN STD_LOGIC;
 saida : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);	
 END component;
 
 component incrementador
	port(
	entrada : in std_logic_vector(7 DOWNTO 0);
	vaium : out std_logic;
	saida : out std_logic_vector(7 DOWNTO 0)
	 );
 end component;
 
 component mpc
	port(	entrada:	in std_logic_vector(7 downto 0);
	clock:		in std_logic;
	saida:	out std_logic_vector(7 downto 0)
	 );
 end component;
 
 component latch_32bits
 port(
 entrada: in std_logic_vector(31 downto 0);
 clock: in std_logic;
 saida:out std_logic_vector(31 downto 0)
 );
 end component;
 
 component mbr
	port(barramento: inout std_logic_vector(15 downto 0);
 toCPU: out std_logic_vector(15 downto 0);
 fromCPU: in std_logic_vector(15 downto 0);
 clock,rd,wr,controle : in std_logic);
 end component;
 
 component mar
 port(Entrada : in std_logic_vector(15 downto 0);
 CLK,Flag:in std_logic;
 Saida: out std_logic_vector(15 downto 0) 
 );
 end component;
 
 
component MIR 
 port(RST,CLK:in std_logic;
 D: in std_logic_vector(31 downto 0);
 Q: out std_logic_vector(31 downto 0));
end component;
 
 component MC 
	port(	
	 endereço:	in std_logic_vector(7 downto 0);
		micro_instru:	out std_logic_vector(31 downto 0)
	);
end component;
 signal subClock1,subClock2,subClock3,subClock4 : std_logic;
 signal saida_MMUX,saida_MPC, saida_INC : std_logic_vector(7 downto 0);
 signal sig_n_alu, sig_z_alu, inc_cy, sig_lms : std_logic ;
 signal saida_MBR: std_logic_vector(15 downto 0);
 signal saida_MC : std_logic_vector(31 downto 0);
 signal saida_MIR : std_logic_vector(31 downto 0);
 signal saida_dec_a,saida_dec_b,saida_dec_c : std_logic_vector(15 downto 0);
 signal barramentoC, barramentoB, barramentoA : std_logic_vector(15 downto 0);
 signal saida_ALU : std_logic_vector(15 downto 0);
 signal saida_Desloc : std_logic_vector(15 downto 0);
 signal saida_LatchA,saida_LatchB: std_logic_vector(15 downto 0);
 	signal MBRbarramento: std_logic_vector(15 downto 0);
 	signal saida_AMUX: std_logic_vector (15 downto 0);
 	signal saida_MAR: std_logic_vector(15 downto 0) ;
 
begin
 
 subciclos : gsc port map (subClock1, subClock2, subClock3, subClock4); 
 mmux : mux2x1_8bits port map (saida_INC, saida_MIR(7 downto 0), sig_lms, saida_MMUX);
 mpcx : mpc port map (saida_MMUX, subClock4, saida_MPC); 
 inc : incrementador port map (saida_MPC, inc_cy, saida_INC); 
 mcx : MC port map (saida_MPC, saida_MC); 
 MIRx : MIR port map ('0',subClock1,saida_MC, saida_MIR); 
 lmsx : lms port map (sig_n_alu, sig_z_alu, saida_MIR(30 downto 29), sig_lms); 
 MBRx : mbr port map (MBRbarramento,saida_MBR,saida_Desloc,subClock4,saida_MIR(22),saida_MIR(21),saida_MIR(24)); -- duvida no barramento 
 
 decC : DEC4X16_fluxo port map (saida_MIR(19),saida_MIR(18),saida_MIR(17),saida_MIR(16), saida_dec_c); 
 decB : DEC4X16_fluxo port map (saida_MIR(15),saida_MIR(14),saida_MIR(13),saida_MIR(12), saida_dec_b); 
 decA : DEC4X16_fluxo port map (saida_MIR(11),saida_MIR(10),saida_MIR(09),saida_MIR(08), saida_dec_a); 
 
 AMUX : mux2x1_16 port map (saida_MBR, saida_LatchA , saida_MIR(31), saida_AMUX); 
 
 ALU : alu_16bits port map (saida_AMUX ,saida_LatchB , saida_MIR(27), saida_MIR(28) , sig_n_alu ,
 sig_z_alu , saida_ALU);
 
 desloc : Desloc_algo port map ( saida_ALU,saida_MIR(26 downto 25),saida_Desloc); 
 
 LA : latch_16bits port map (barramentoA, subClock3 , saida_LatchA);
 LB : latch_16bits port map (barramentoB, subClock3 , saida_LatchB);
 
 MARx : mar PORT MAP (saida_LatchB, subClock3 ,saida_MIR(23),saida_MAR);
 regPC : registrador_16bits port map(barramentoC,subClock4, saida_dec_a(0), '0', saida_dec_a(1), saida_dec_b(0), barramentoA, barramentoB);
 regAC : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(1), '0', saida_dec_a(2), saida_dec_b(1), barramentoA, barramentoB);
 regSP : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(2), '0', saida_dec_a(3), saida_dec_b(2), barramentoA, barramentoB);
 regIR : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(3), '0', saida_dec_a(4), saida_dec_b(3), barramentoA, barramentoB);
 regTIR : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(4), '0', saida_dec_a(5), saida_dec_b(4), barramentoA, barramentoB);
 reg0 : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(5), '0', saida_dec_a(5), saida_dec_b(5), barramentoA, barramentoB);
 reg1 : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(6), '0', saida_dec_a(6), saida_dec_b(6), barramentoA, barramentoB);
 reg_1 : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(7), '0', saida_dec_a(7), saida_dec_b(7), barramentoA, barramentoB);
 regAMASK : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(8), '0', saida_dec_a(8), saida_dec_b(8), barramentoA, barramentoB);
 regSMASK : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(9), '0', saida_dec_a(9), saida_dec_b(9), barramentoA, barramentoB);
 regA : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(10), '0', saida_dec_a(10), saida_dec_b(10), barramentoA, barramentoB);
 regB : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(11), '0', saida_dec_a(11), saida_dec_b(11), barramentoA, barramentoB);
 regC : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(12), '0', saida_dec_a(12), saida_dec_b(12), barramentoA, barramentoB);
 regD : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(13), '0', saida_dec_a(13), saida_dec_b(13), barramentoA, barramentoB);
 regE : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(14), '0', saida_dec_a(14), saida_dec_b(14), barramentoA, barramentoB);
 regF : registrador_16bits port map(barramentoC, subClock4, saida_dec_a(15), '0', saida_dec_a(15), saida_dec_b(15), barramentoA, barramentoB); 
end estrutural;
library ieee;
use ieee.std_logic_1164.all;
entity testeprocessador is
end testeprocessador;
architecture teste of testeprocessador is
 component arq_horizontal
 port (barramentoEndereco : OUT std_logic_vector (15 DOWNTO 0);
		barramentoDeDados : INOUT std_logic_vector (15 DOWNTO 0);
		RD : OUT std_logic ;
		WR : OUT std_logic);
 end component;
 signal sigBarEnd: std_logic_vector (15 DOWNTO 0);
 signal sigBarDados: std_logic_vector (15 DOWNTO 0); 
 signal sigRD,sigWR:std_logic ;
begin
 comp: arq_horizontal
 port map (sigBarEnd,sigBarDados,sigRD,sigWR); 
 process 
 begin
 sigBarDados <= "0100001000101111","1010001011010110" after 1 ns, "1001000001000011" after 2 ns,"1000010111110111" after 3 ns;
 wait;
 end process;
end teste;
3. CONCLUSÃO
Foi utilizado o programa ModelSim como ferramenta gratuita para a simulação de um processador cuja microarquitetura é a mais horizontal. Cada componente foi compilado e simulado separadamente, para que, em seguida, fossem utilizados como sub componentes do processador, a partir do modelo estrutural.
Para isso foram consultados os manuais de VHDL e o livro do Tanenbaum, Organização Estruturada de Computadores. Além das transparências da Profª Luiza Mourelle. 
4. REFERÊNCIAS
[1] Tanenbaum, A. S., “Organização Estruturada de Computadores”, 3a. Edição, Pearson/Prentice Hall.
[2] Ashenden, Peter J., “The VHDL Cookbook”, 1st Edition, Department of Computer Science, University of Adelaide, South Australia, http://tams-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf.
[3] Mentor Graphics, http://www.model.com.