verilog

Prévia do material em texto

// Somador Binário de 2 Bits
module SomadorBinario2 (SW, LEDR);
input [3:0] SW;
output [2:0] LEDR;
wire A1, A0, B1, B0, S1, S0, C, Ci;
assign B0 = SW[0];
assign B1 = SW[1];
assign A0 = SW[2];
assign A1 = SW[3];
assign LEDR[0] = S0;
assign LEDR[1] = S1;
assign LEDR[2] = C;
SomadorCompleto U1(S0, Ci, A0, B0, 0);
SomadorCompleto U2(S1, C, A1, B1, Ci);
Endmodule
// Subtrator Binário de 2 Bits
module SubtratorBinario2 (SW, LEDR);
input [3:0] SW;
output [2:0] LEDR;
wire A1, A0, B1, B0, S1, S0, C, Ci;
assign B0 = SW[0];
assign B1 = SW[1];
assign A0 = SW[2];
assign A1 = SW[3];
assign LEDR[0] = S0;
assign LEDR[1] = S1;
assign LEDR[2] = C;
SubtratorCompleto U1(S0, Ci, A0, B0, 0);
SubtratorCompleto U2(S1, C, A1, B1, Ci);
endmodule
// Módulo SomadorCompleto
module SomadorCompleto (S, Co, A, B, Ci);
input A, B, Ci;
output S, Co;
wire x, y, z;
Porta_XOR U1(S, A, B, Ci);
Porta_AND U2(x, A, B, 1);
Porta_AND U3(y, A, Ci, 1);
Porta_AND U4(z, B, Ci, 1);
Porta_OR U5(Co, x, y, z);
endmodule
// Módulo SubtratorCompleto
module SubtratorCompleto (S, Co, A, B, Ci);
input A, B, Ci;
output S, Co;
wire x, y, z;
Porta_XOR U1(S, A, B, Ci);
Porta_AND U2(x, ~A, B, 1);
Porta_AND U3(y, ~A, Ci, 1);
Porta_AND U4(z, B, Ci, 1);
Porta_OR U5(Co, x, y, z);
endmodule
// Módulo Porta_AND
module Porta_AND(S, A, B, C);
input A, B, C;
output S;
assign S = A&B&C;
endmodule
// Módulo Porta_OR
module Porta_OR(S, A, B, C);
input A, B, C;
output S;
assign S = A | B | C;
endmodule
// Módulo Porta_XOR
module Porta_XOR(S, A, B, C);
input A, B, C;
output S;
assign S = A^B^C;
endmodule
// Módulo Somador/Subtrator de 2 bits
module Soma_Sub (SW, LEDR);
input [4:0] SW;
output [2:0] LEDR;
wire A1, A0, B1, B0, S1, S0, C, m, x, y, z, t, u, v;
assign B0 = SW[0];
assign B1 = SW[1];
assign A0 = SW[2];
assign A1 = SW[3];
assign m = SW[4]
assign LEDR[0] = S0;
assign LEDR[1] = S1;
assign LEDR[2] = C;
// Determinação de S0
Porta_XOR U1(S0, A0, B0, 0);
// Determinação de S1
Porta_XOR U2(x, A0, m, 0);
Porta_XOR U3(y, A1, m, 0);
Porta_AND U4(z, x, B0, 1);
Porta_XOR U5(S1, A1, B1, z);
// Determinação de C
Porta_AND U6(t, y, B1, 1);
Porta_AND U7(u, x, y, B0);
Porta_AND U8(v, x, B1, B0);
 Porta_OR U9(C, t, u, v);
endmodule
//Módulo do Flip-Flop D
module FlipFlopD(Q, D, CK, CLR);
	input D, CK, CLR;
	output Q;
	reg Q;
	always @(negedge CK or negedge CLR)
		begin
			if(!CLR) Q = 0;
			else Q = D;
		end
endmodule
//Módulo do Flip-Flop JK
module FlipFlopJK(Q, J, K, CK, CLR);
	input J, K, CK, CLR;
	output Q;
	reg Q;
	always @(negedge CK or negedge CLR)
		begin
			if(!CLR) Q = 0;
			else
begin
case ({J, K})
		0: Q = Q;
		1: Q = 0;
		2: Q = 1;
		3: Q = ~Q;
endcase
end
		end
endmodule
//Módulo da porta NAND
module porta_NAND(S, A, B);
	input A, B;
	output S;
	assign S = ~(A&B);
endmodule
// Registrador entrada paralela / saída serial de 4 bits
wire Q, E, CK, CLR;
wire[3:0] I, x;
	wire [2:0] y;
	assignI [3:0] = SW [3:0]
assignE = SW[4];
	assign CLR = SW[5];
assign CK = CLOCK_27;
	porta_NAND U0( x[3], I[3], E);
	porta_NAND U1( x[2], I[2], E);
	porta_NAND U2( x[1], I[1], E);
	porta_NAND U3( x[0], I[0], E);
FlipFlopD_PR U4( y[2], 0, CK, CLR, x[3] );
FlipFlopD_PR U5( y[1], y[2], CK, CLR, x[2] );
FlipFlopD_PR U6( y[0], y[1], CK, CLR, x[1] );
FlipFlopD_PRU7(Q, y[0], CK, CLR, x[0] );
	assign LEDR[0] = Q;
	endmodule
//Módulo do Flip-Flop D com entrada PR
module FlipFlopD_PR(Q, D, CK, CLR, PR);
	input D, CK, CLR, PR;
	output Q;
	reg Q;
	always @(negedge CK or negedge CLR or negedge PR)
		begin
			if(!CLR) Q = 0;
			else if(!PR) Q = 1;
			else Q = D;
end
endmodule
// Registrador de deslocamento direita/esquerda de 4 bits
wire [3:0] q, x;
	wire [1:0] y;
wire D, CK, CLR;
	assign D = SW [0];
assign CLR = SW[1];
	assign y[1:0] = SW[3:2];
	assign CK = KEY[0];
	MUX2x1 U3( x[3], D, q[2], y[1]);
	FlipFlopD W3( q[3], x[3], CK, CLR);
MUX2x1 U2( x[2], D, q[1], q[3]);
	FlipFlopD W2( q[2], x[2], CK, CLR);
MUX2x1 U1( x[1], D, q[0], q[2]);
	FlipFlopD W1( q[1], x[1], CK, CLR);
MUX2x1 U0( x[0], D, y[0], q[1]);
FlipFlopD W0( q[0], x[0], CK, CLR);
assign LEDR [3:0] = q[3:0];
	endmodule
//Módulo do MUX 2x1
module MUX2x1(S, D, I0, I1);
	input I0, I1, D;
	output S;
	reg S;
	always @( I0 or I1 or D)
		begin
			case(D)
				0: S = I0;
				1: S = I1;
			endcase
		end
endmodule
// Contador gray síncrono modulo 6 decrescente
wire CK, CLR;
wire [2:0] A, J, K;
assign CLR = SW[0];
assign CK = KEY[0];
assign K[2] = ~A[0];
assign J[1] = ~A[0];
assign J[0] = ~A[2];
porta_AND U1(J[2], ~A[1], ~A[0]);
porta_AND U2(K[1], ~A[2], A[0]);
porta_OR U3(K[0], ~A[1], A[2]);
FlipFlop_JK W2(A[2], CK, CLR, J[2], K[2]);
FlipFlop_JK W1(A[1], CK, CLR, J[1], K[1]);
FlipFlop_JK W0(A[0], CK, CLR, J[0], K[0]);
assign LEDR[2:0] = A[2:0];
endmodule
// Contador Johnson modificado de 4 bits
wire CK, CLR, x, y;
wire [3:0] A, J, K;
assign CLR = SW[0];
assign CK = KEY[0];
assign J[2] = A[3];
assign K[2] = ~A[3];
assign J[1] = A[2];
assign K[1] = ~A[2];
assign J[0] = A[1];
assign K[0] = ~A[1]; 
porta_OR U1(x, ~A[2], ~A[1]);
porta_AND U2(J[3], x, ~A[0]);
porta_OR U3(y, A[2], A[1]);
porta_AND U4(K[3], y, A[0]);
FlipFlop_JK W3(A[3], CK, CLR, J[3], K[3]);
FlipFlop_JK W2(A[2], CK, CLR, J[2], K[2]);
FlipFlop_JK W1(A[1], CK, CLR, J[1], K[1]);
FlipFlop_JK W0(A[0], CK, CLR, J[0], K[0]); 
assign LEDR[3:0] = A[3:0];
endmodule
//Contador síncrono em anel 4 de bits
wire CK, CLR, S;
wire [3:0]Y, D;
wire [0:3]Q;
assign Y[3:0] = SW[3:0];
assign S = SW[4];
assign CLR = SW[5];
assign CK = KEY[0];
mux21 U0(Y[0], Q[3], S, D[0]);
mux21 U1(Y[1], Q[0], S, D[1]);
mux21 U2(Y[2], Q[1], S, D[2]);
mux21 U3(Y[3], Q[2], S, D[3]);
FlipFlop_D W0(Q[0], CK, CLR, D[0]);
FlipFlop_D W1(Q[1], CK, CLR, D[1]);
FlipFlop_D W2(Q[2], CK, CLR, D[2]);
FlipFlop_D W3(Q[3], CK, CLR, D[3]);
assign LEDR[3:0] = Q[0:3];
endmodule
// Contador assíncrono módulo 8 crescente/decrescente
wire CK, CLR, C;
wire [2:0]Q;
assign C = SW[0];
assign CLR = SW[1];
assign CK = KEY[0];
mux21 U0(x, Q[0], ~Q[0], C);
mux21 U1(y, Q[1], ~Q[1], C);
FlipFlop_T W0(Q[0], CK, CLR, 1);
FlipFlop_T W1(Q[1], x, CLR, 1);
FlipFlop_T W2(Q[2], y, CLR, 1);
assign LEDR[2:0] = Q[2:0];
endmodule