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Lecture 3: 
CMOS 
Transistor 
Theory
3: CMOS Transistor Theory 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Outline
‰ Introduction
‰ MOS Capacitor
‰ nMOS I-V Characteristics
‰ pMOS I-V Characteristics
‰ Gate and Diffusion Capacitance
3: CMOS Transistor Theory 3CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Introduction
‰ So far, we have treated transistors as ideal switches
‰ An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
‰ Transistor gate, source, drain all have capacitance
– I = C (ΔV/Δt) -> Δt = (C/I) ΔV
– Capacitance and current determine speed
3: CMOS Transistor Theory 4CMOS VLSI DesignCMOS VLSI Design 4th Ed.
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
Vg < 0
MOS Capacitor
‰ Gate and body form MOS 
capacitor
‰ Operating modes
– Accumulation
– Depletion
– Inversion
3: CMOS Transistor Theory 5CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Terminal Voltages
‰ Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
‰ Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds ≥ 0
‰ nMOS body is grounded. First assume source is 0 too.
‰ Three regions of operation
– Cutoff
– Linear
– Saturation
Vg
Vs Vd
VgdVgs
Vds
+-
+
-
+
-
3: CMOS Transistor Theory 6CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS Cutoff
‰ No channel
‰ Ids ≈ 0
+
-
Vgs = 0
n+ n+
+
-
Vgd
p-type body
b
g
s d
3: CMOS Transistor Theory 7CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS Linear
‰ Channel forms
‰ Current flows from d to s 
– e- from s to d
‰ Ids increases with Vds
‰ Similar to linear resistor
+
-
Vgs > Vt
n+ n+
+
-
Vgd = Vgs
+
-
Vgs > Vt
n+ n+
+
-
Vgs > Vgd > Vt
Vds = 0
0 < Vds < Vgs-Vt
p-type body
p-type body
b
g
s d
b
g
s d Ids
3: CMOS Transistor Theory 8CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS Saturation
‰ Channel pinches off
‰ Ids independent of Vds
‰ We say current saturates
‰ Similar to current source
+
-
Vgs > Vt
n+ n+
+
-
Vgd < Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
3: CMOS Transistor Theory 9CMOS VLSI DesignCMOS VLSI Design 4th Ed.
I-V Characteristics
‰ In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
3: CMOS Transistor Theory 10CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Channel Charge
‰ MOS structure looks like parallel plate capacitor 
while operating in inversions
– Gate – oxide – channel
‰ Qchannel = CV
‰ C = Cg = εoxWL/tox = CoxWL
‰ V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-
drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, εox = 3.9)
polysilicon
gate
Cox = εox / tox
3: CMOS Transistor Theory 11CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Carrier velocity
‰ Charge is carried by e-
‰ Electrons are propelled by the lateral electric field 
between source and drain
– E = Vds/L
‰ Carrier velocity v proportional to lateral E-field 
– v = μE μ called mobility
‰ Time for carrier to cross channel:
– t = L / v
3: CMOS Transistor Theory 12CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS Linear I-V
‰ Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
ds
gs t ds
ds
gs t ds
QI
t
W VC V V V
L
VV V V
μ
β
=
⎛ ⎞= − −⎜ ⎟⎝ ⎠
⎛ ⎞= − −⎜ ⎟⎝ ⎠ ox = 
WC
L
β μ
3: CMOS Transistor Theory 13CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS Saturation I-V
‰ If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
‰ Now drain voltage no longer increases current
( )2
2
2
dsat
ds gs t dsat
gs t
VI V V V
V V
β
β
⎛ ⎞= − −⎜ ⎟⎝ ⎠
= −
3: CMOS Transistor Theory 14CMOS VLSI DesignCMOS VLSI Design 4th Ed.
nMOS I-V Summary
( )2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
β
β
⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪⎪ − >⎪⎩
‰ Shockley 1st order transistor models
3: CMOS Transistor Theory 15CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Example
‰ We will be using a 0.6 μm process for your project
– From AMI Semiconductor
– tox = 100 Å
– μ = 350 cm2/V*s
– Vt = 0.7 V
‰ Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2 λ
( ) 14 283.9 8.85 10350 120 μA/V100 10ox
W W WC
L L L
β μ
−
−
⎛ ⎞× ⋅ ⎛ ⎞= = =⎜ ⎟⎜ ⎟⋅ ⎝ ⎠⎝ ⎠
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
Vds
I
d
s
 
(
m
A
)
Vgs = 5
Vgs = 4
Vgs = 3
Vgs = 2
Vgs = 1
3: CMOS Transistor Theory 16CMOS VLSI DesignCMOS VLSI Design 4th Ed.
pMOS I-V
‰ All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
‰ Mobility μp is determined by holes
– Typically 2-3x lower than that of electrons μn
– 120 cm2/V•s in AMI 0.6 μm process
‰ Thus pMOS must be wider to 
provide same current
– In this class, assume 
μn / μp = 2
-5 -4 -3 -2 -1 0-0.8
-0.6
-0.4
-0.2
0
I
d
s
(
m
A
)
Vgs = -5
Vgs = -4
Vgs = -3
Vgs = -2
Vgs = -1
Vds
3: CMOS Transistor Theory 17CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Capacitance
‰ Any two conductors separated by an insulator have 
capacitance
‰ Gate to channel capacitor is very important
– Creates channel charge necessary for operation
‰ Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is 
associated with source/drain diffusion
3: CMOS Transistor Theory 18CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Gate Capacitance
‰ Approximate channel as connected to source
‰ Cgs = εoxWL/tox = CoxWL = CpermicronW
‰ Cpermicron is typically about 2 fF/μm 
n+ n+
p-type body
W
L
tox
SiO2 gate oxide
(good insulator, εox = 3.9ε0)
polysilicon
gate
3: CMOS Transistor Theory 19CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Capacitance
‰ Csb, Cdb
‰ Undesirable, called parasitic capacitance
‰ Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process