1 (224)

Prévia do material em texto

Step 1 of 4 6.22DP Refer 32-to-1 multiplexer as shown in figure 6-62 in the text book consists three stages. The first stage contains 74 X 138(3-to-8 decoder), the second stages are made of four 74 X 151((8-to-1 multiplexer), and last stage consists of one 4 input NAND gate, 74 X 20. Consider the worst time delay nothing but selecting the highest time delay among to-high and to-low for the 74LS components from the Table 6-2 and Table 6-3 in the textbook. Write the scrutinized propagation delay list is as shown in table 1. Table 1 Part number From To (ns) '138 Any select Dutput(2) 41 41 Any select Output(3) 39 39 G2A,G2B Output 32 32 G1 Output 38 38 '151 Any select Y 32 32 Any data Y 21 21 Enable Y 30 30 '20 15 15 Step 2 of 4 Now calculate the delay in transmission signal from any input to output by considering each device separately. Assume each of this signals are transmitted one after another not simultaneously as in parallel process because we are trying to find out the worst case delays. Find the propagation delay for the stage 74 X 138. Enable delays of the device we will calculate as (32+32+38)ns=102ns From the figure 6-35 in the text book, it is clear that the data transmission delay of 74x138 is by considering the signal transmitted through 3 NAND gates internally as we are trying to find out worst case scenario. As there are three input lines, the total delays will be (39x3)ns=87ns Thus total delay of 74 138 is (102+87)ns=189ns Step 3 of 4 In second stages the total delay of four 74 X 151 is the summation of enable delay, select line delay and data delay. This total delay we will calculate using the above table as follows, As only one data line D6 is selected here in each 74 X 151. Step 4 of 4 In last stage we will calculate the delay of one 4 input NAND gate 74 X 20 as follows, Thus the total delay of 32-to1 MUX is The worst case delay of 32-to-1 MUX of figure 6-62 is 837 ns