Aula 07 Somadores e Multiplicadores2

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Somadores e Multiplicadores
Descrição Arquitetural
Prof. Edward David Moreno
edwdavid@gmail.com
Meio-Somador
Efetua operações de 1 bit;
Em palavras maiores falha por não considerar 
o estouro da adição anterior;
Exemplos:
0 0 0 1
0 0 1 1
+0 +1 +0 +1
0 1 1 0
Vai-um
Meio-Somador
library IEEE;
use IEEE.std_logic_1164.all;
entity meiosomador is
port (
a,b: in STD_LOGIC;
s, vaium: out STD_LOGIC
);
end meiosomador;
architecture meiosomador_arch of meiosomador is
begin
s <= a xor b;
vaium <= a and b;
end meiosomador_arch;
Somador Completo (1 bit)
Implementa sinais de controle 
chamados “vem-um” e “vai-um”.
Somador Completo (1 bit)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador1bit is
port (
cin,a,b: in STD_LOGIC;
s,cout: out STD_LOGIC
);
end somador1bit;
architecture somador1bit_arch of somador1bit is
begin
s <= a xor b xor cin;
cout <= (a and b) or ((a xor b) and cin);
end somador1bit_arch;
Somador Completo (4 bits)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador4bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end somador4bits;
architecture somador4bits_arch of somador4bits is
begin
process(a,b,cin)
variable soma:std_logic_vector(3 downto 0);
variable c:std_logic;
begin
c := cin;
for i in 0 to 3 loop
soma(i) := a(i) xor b(i) xor c;
c := (a(i) and b(i)) or ((a(i) xor b(i)) and c);
end loop;
cout <= c;
s <= soma;
end process;
end somador4bits_arch;
Respostas – Somador 8 bits (v1)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador8bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(7 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end somador8bits;
architecture somador8bits_arch of somador8bits is
begin
process(a,b,cin)
variable soma:std_logic_vector(7 downto 0);
variable c:std_logic;
begin
c := cin;
for i in 0 to 7 loop
soma(i) := a(i) xor b(i) xor c;
c := (a(i) and b(i)) or ((a(i) xor b(i)) and c);
end loop;
cout <= c;
s <= soma;
end process;
end somador8bits_arch;
Respostas – Somador 16 bits (v1)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador16bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(15 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end somador16bits;
architecture somador16bits_arch of somador16bits is
begin
process(a,b,cin)
variable soma:std_logic_vector(15 downto 0);
variable c:std_logic;
begin
c := cin;
for i in 0 to 15 loop
soma(i) := a(i) xor b(i) xor c;
c := (a(i) and b(i)) or ((a(i) xor b(i)) and c);
end loop;
cout <= c;
s <= soma;
end process;
end somador16bits_arch;
Respostas – Somador 8 bits (v2)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador8bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(7 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end somador8bits;
architecture somador8bits_arch of somador8bits is
component somador4bits
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
Respostas – Somador 8 bits (v2)
(continuação)
signal aux:std_logic;
begin
s1: somador4bits port map (cin, a(3 downto 0), b(3 downto 
0), aux, s(3 downto 0));
s2: somador4bits port map (aux, a(7 downto 4), b(7 downto 
4), cout, s(7 downto 4));
end somador8bits_arch;
Respostas – Somador 16 bits (v2)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador16bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(15 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end somador16bits;
architecture somador16bits_arch of somador16bits is
component somador8bits
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(7 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
Respostas – Somador 16 bits (v2)
(continuação)
signal aux:std_logic;
begin
s1: somador8bits port map (cin, a(7 downto 0), b(7 downto 
0), aux, s(7 downto 0));
s2: somador8bits port map (aux, a(15 downto 8), b(15 downto 
8), cout, s(15 downto 8));
end somador16bits_arch;
Resumo das Estatísticas
Ocupação
Temporização
FF LUTs4 LUTs3 CLBs
Somador 8 bits (v1) 0 20 2 12
Somador 8 bits (v2) 0 20 2 12
Somador 16 bits (v1) 0 40 6 24
Somador 16 bits (v2) 0 40 6 24
TL TR AT
Somador 8 bits (v1) 13,197ns 16,745ns 29,942ns
Somador 8 bits (v2) 13,197ns 17,891ns 31,088ns
Somador 16 bits (v1) 21,033ns 36,211ns 57,244ns
Somador 16 bits (v2) 21,033ns 29,843ns 50,876ns
Algoritmo Multiplicador
INICIO:
� Contador de bits recebe o numero de bits a 
ser multiplicado;
� Inicializa produto com zero;
� Para i de 0 até número de bits da 
multiplicação faça
� Deslocar (resultado);
� Vaium recebe bit mais significativo do 
multiplicador;
� Se vaium igual a 1 (um) então
� Soma (produto,multiplicando);
� Deslocar (multiplicador);
� Resultado recebe produto;
FIM.
Algoritmo Multiplicador
Implementação: Multiplicador de 4 bits
library ieee;
use ieee.std_logic_1164.all;
entity mult4bits is
port (a, b: in std_logic_vector (3 downto 0);
s: out std_logic_vector (3 downto 0));
end mult4bits;
architecture arch_mult4bits of mult4bits is
-- deslocamento de 1 bit para esquerda, zerando o bit menos 
significativo
function deslocador (x : std_logic_vector (3 downto 0))
return std_logic_vector is
variable y : std_logic_vector (3 downto 0);
begin
for i in 3 downto 1 loop
y(i) := x(i-1);
end loop ;
y(0) := '0';
return y;
end;
Implementação: Multiplicador de 4 bits
-- somador de 4 bits
function somador4bits (a : std_logic_vector (3 downto 0);
b : std_logic_vector (3 downto 0))
return std_logic_vector is
variable vaium : std_logic;
variable soma : std_logic_vector (3 downto 0);
begin
vaium := '0';
for i in 0 to 3 loop
soma(i) := a(i) xor b(i) xor vaium;
vaium := ( a(i) and b(i) ) or ( b(i) and vaium) or 
(vaium and a(i) );
end loop;
return soma;
end;
Implementação: Multiplicador de 4 bits
begin
process(a,b)
variable aux1 : std_logic_vector (3 downto 0);
variable aux2 : std_logic_vector (3 downto 0);
variable vaium : std_logic;
begin
-- inicializações
aux1 := "0000";
aux2 := a;
vaium := '0';
-- implementação do algoritmo
for i in 0 to 3 loop
aux1 := deslocador( aux1 );
vaium := aux2(3);
if vaium = '1' then
aux1 := somador4bits( aux1, b );
end if;
aux2 := deslocador( aux2 );
end loop;
s <= aux1;
end process;
end arch_mult4bits;
Descrição comportamental
Descreve o comportamento do circuito;
Os circuitos somador e multiplicador 
também podem ser implementados 
utilizando descrição comportamental;
Somador 4 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity somador is
port (
a, b: in INTEGER range 0 to 15;
s: out INTEGER range 0 to 15
);
end somador;
architecture somador_arch of somador is
begin
process (a,b)
begin
s <= a + b;
end process;
end somador_arch;
Multiplicador 4 bits
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult is
port (
a, b: in INTEGER range 0 to 15;
s: out INTEGER range 0 to 15
);
end mult;
architecture mult_arch of mult is
begin
process (a,b)
begin
s <= a * b;
end process;
end mult_arch;