CPU8 VHDL

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CPU8 is
 port (
 rw: out STD_LOGIC;
 dout: out STD_LOGIC_VECTOR (7 downto 0);
 din: in STD_LOGIC_VECTOR (7 downto 0);
 addr: out STD_LOGIC_VECTOR (3 downto 0);
 clk: in STD_LOGIC
 );
end CPU8;
architecture CPU8_arch of CPU8 is
-- declaracao de registradores
signal PC: STD_LOGIC_VECTOR (3 downto 0); -- contador de prog.
signal RI: STD_LOGIC_VECTOR (7 downto 0); -- inst. que esta sendo 
executada
signal A: STD_LOGIC_VECTOR (7 downto 0); -- armazena result. operacoes
signal B: STD_LOGIC_VECTOR (7 downto 0); -- reg. auxiliar
-- maquina de estados
signal ESTADO: STD_LOGIC_VECTOR (1 downto 0); -- estados do 
processador (busca, dec, exec)
-- instrucoes (constantes) (opcodes)
constant ADD: STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- 0h
constant SUB: STD_LOGIC_VECTOR (3 downto 0) := "0001"; -- 1h
constant ANDX: STD_LOGIC_VECTOR (3 downto 0) := "0010"; -- 2h
constant ORX: STD_LOGIC_VECTOR (3 downto 0) := "0011"; -- 3h
constant XORX: STD_LOGIC_VECTOR (3 downto 0) := "0100"; -- 4h
constant INC: STD_LOGIC_VECTOR (3 downto 0) := "0101"; -- 5h
constant DEC: STD_LOGIC_VECTOR (3 downto 0) := "0110"; -- 6h
constant LOAD: STD_LOGIC_VECTOR (3 downto 0) := "1000"; -- 8h
begin
process (clk)
begin
if clk'event and clk='1' then -- aqui vai meu processador
case ESTADO is
when "00" => -- busca
RI <= din;
rw <= '0'; -- memoria em leitura
PC <= PC + 1;
ESTADO <= "01";
when "01" => -- decodificacao e execucao
case RI(7 downto 4) is
when ADD => A <= A + B;
when SUB => A <= A - B;
when ANDX => A <= A AND B;
when ORX => A <= A OR B;
when XORX => A <= A XOR B;
when INC => A <= A + 1;
when DEC => A <= A - 1;
-- when LOAD =>
when others => null;
end case;
ESTADO <= "00";
when others => null;
end case;
end if;
end process;
end CPU8_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity CPU8 is
 port (
 rw: out STD_LOGIC;
 dout: out STD_LOGIC_VECTOR (7 downto 0);
 din: in STD_LOGIC_VECTOR (7 downto 0);
 addr: out STD_LOGIC_VECTOR (3 downto 0);
 clk: in STD_LOGIC
 );
end CPU8;
architecture CPU8_arch of CPU8 is
-- declaracao de registradores
signal PC: STD_LOGIC_VECTOR (3 downto 0); -- contador de prog.
signal RI: STD_LOGIC_VECTOR (7 downto 0); -- inst. que esta sendo 
executada
signal A: STD_LOGIC_VECTOR (7 downto 0); -- armazena result. operacoes
signal B: STD_LOGIC_VECTOR (7 downto 0); -- reg. auxiliar
-- maquina de estados
signal ESTADO: STD_LOGIC_VECTOR (1 downto 0); -- estados do 
processador (busca, dec, exec)
-- instrucoes (constantes) (opcodes)
constant ADD: STD_LOGIC_VECTOR (3 downto 0) := "0000"; -- 0h
constant SUB: STD_LOGIC_VECTOR (3 downto 0) := "0001"; -- 1h
constant ANDX: STD_LOGIC_VECTOR (3 downto 0) := "0010"; -- 2h
constant ORX: STD_LOGIC_VECTOR (3 downto 0) := "0011"; -- 3h
constant XORX: STD_LOGIC_VECTOR (3 downto 0) := "0100"; -- 4h
constant INC: STD_LOGIC_VECTOR (3 downto 0) := "0101"; -- 5h
constant DEC: STD_LOGIC_VECTOR (3 downto 0) := "0110"; -- 6h
constant LOAD: STD_LOGIC_VECTOR (3 downto 0) := "1000"; -- 8h
begin
process (clk)
begin
if clk'event and clk='1' then -- aqui vai meu processador
case ESTADO is
when "00" => -- busca
RI <= din;
rw <= '0'; -- memoria em leitura
PC <= PC + 1;
ESTADO <= "01";
when "01" => -- decodificacao e execucao
case RI(7 downto 4) is
when ADD => A <= A + B;
when SUB => A <= A - B;
when ANDX => A <= A AND B;
when ORX => A <= A OR B;
when XORX => A <= A XOR B;
when INC => A <= A + 1;
when DEC => A <= A - 1;
-- when LOAD =>
when others => null;
end case;
ESTADO <= "00";
when others => null;
end case;
end if;
end process;
end CPU8_arch;