278500-Apresentações
287 pág.

278500-Apresentações


DisciplinaArquitetura e Organização de Computadores 1269 materiais4.365 seguidores
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comes from outside of the 
processor
\u2022 New Registers: EPC and Cause
\u2022 Two Methods: Simple and Vectored
189\uf6d92004 Morgan Kaufmann Publishers
Datapath
Read
register 1
Read
register 2
Write
register
Write
data
Registers ALU
Zero
Read
data 1
Read
data 2
Sign
extend
16 32
Instruction
[31\u201326]
Instruction
[25\u201321]
Instruction
[20\u201316]
Instruction
[15\u20130]
ALU
result
M
u
x
M
u
x
Shift
left 2
Shift
left 2
Instruction
register
PC 0
1
M
u
x
0
1
M
u
x
0
1
M
u
x
0
1
M
u
x
0
1
A
B 0
1
2
3
M
u
x
0
1
2
3
ALUOut
Instruction
[15\u20130]
Memory
data
register
Address
Write
data
Memory
MemData
4
Instruction
[15\u201311]
PCWriteCond
PCWrite
IorD
MemRead
MemWrite
MemtoReg
IRWrite
CauseWrite
IntCause
EPCWrite
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite
RegDst
26 28
Outputs
Control
Op
[5\u20130]
ALU
control
PC [31\u201328]
Instruction [25\u20130]
Instruction [5\u20130]
Jump
address
[31\u20130]
EPC
Cause
8000 0180
0
1
190\uf6d92004 Morgan Kaufmann Publishers
Control
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
MemRead
IorD = 1
MemWrite
IorD = 1
RegDst = 1
RegWrite
MemtoReg = 0
RegDst = 0
RegWrite
MemtoReg = 1
PCWrite
PCSource = 10
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
Instruction decode/
register fetch
Instruction fetch
0 1
Start
( O p 
= ' L W
' ) o r 
( O p 
= ' S W
' )
( O p
 = 
R -
t y p
e )
( O
p =
 '
B E
Q '
)
(
O
p
 
=
 
'
J
'
)
Jump
completion
9862
3
4
5 7
Write-back step
R-type completion
Memory
access
Memory
access
Execution
Branch
completion
Memory address
computation
(Op = 'SW')
(
O
p
 
=
 
'
L
W
'
)
IntCause = 1
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PCSource = 11
IntCause = 0
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PCSource = 11
Overflow
Overflow
11 10
(Op = other)
191\uf6d92004 Morgan Kaufmann Publishers
Chapter Six
192\uf6d92004 Morgan Kaufmann Publishers
Motivação
Time
6 PM 7 8 9 10 11 12 1 2 AM
Task
order
A
B
C
D
193\uf6d92004 Morgan Kaufmann Publishers
Motivação
Time
6 PM 7 8 9 10 11 12 1 2 AM
Task
order
A
B
C
D
194\uf6d92004 Morgan Kaufmann Publishers
Pipelining
\u2022 Improve performance by increasing instruction throughput
Ideal speedup is number of stages in the pipeline. Do we achieve this?
Program
execution
order
(in instructions)
lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
Time
200 400 600 800 1000 1200 1400 1600 1800
Instruction
fetch Reg ALU
Data
access Reg
Instruction
fetch Reg ALU
Data
access Reg
Instruction
fetch
800 ps
800 ps
800 ps
Program
execution
order
(in instructions)
lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
Time
200 400 600 800 1000 1200 1400
Instruction
fetch Reg ALU
Data
access Reg
Instruction
fetch
Instruction
fetch
Reg ALU Dataaccess Reg
Reg ALU Dataaccess Reg
200 ps
200 ps
200 ps 200 ps 200 ps 200 ps 200 ps
Note: 
timing assumptions changed
for this example
195\uf6d92004 Morgan Kaufmann Publishers
Pipelining
\u2022 What makes it easy
\u2013 all instructions are the same length
\u2013 just a few instruction formats
\u2013 memory operands appear only in loads and stores
\u2022 What makes it hard?
\u2013 structural hazards: suppose we had only one memory
\u2013 control hazards: need to worry about branch instructions
\u2013 data hazards: an instruction depends on a previous instruction
\u2022 We\u2019ll build a simple pipeline and look at these issues
\u2022 We\u2019ll talk about modern processors and what really makes it hard:
\u2013 exception handling
\u2013 trying to improve performance with out-of-order execution, etc.
196\uf6d92004 Morgan Kaufmann Publishers
Basic Idea
\u2022 What do we need to add to actually split the datapath into stages?
WB: Write backMEM: Memory accessIF: Instruction fetch ID: Instruction decode/
register file read
EX: Execute/
address calculation
Address
Write
data
Read
dataData
Memory
Read
register 1
Read
register 2
Write
register
Write
data
Registers
Read
data 1
Read
data 2
ALU
Zero
ALU
result
ADDAddresultShift
left 2
Address
Instruction
Instruction
memory
Add
4
PC
Sign
extend
16 32
197\uf6d92004 Morgan Kaufmann Publishers
Pipelined Datapath
Can you find a problem even if there are no dependencies? 
What instructions can we execute to manifest the problem?
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EXIF/ID EX/MEM MEM/WB
16 32
198\uf6d92004 Morgan Kaufmann Publishers
Corrected Datapath
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EXIF/ID EX/MEM MEM/WB
16 32
199\uf6d92004 Morgan Kaufmann Publishers
Graphically Representing Pipelines
\u2022 Can help with answering questions like:
\u2013 how many cycles does it take to execute this code?
\u2013 what is the ALU doing during cycle 4?
\u2013 use this representation to help understand datapaths
Program
execution
order
(in instructions)
lw $1, 100($0)
lw $2, 200($0)
lw $3, 300($0)
Time (in clock cycles)
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC7
IM DMReg RegALU
IM DMReg RegALU
IM DMReg RegALU
200\uf6d92004 Morgan Kaufmann Publishers
Pipeline Control
MemWrite
PCSrc
MemtoReg
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Write
register
Write
data
Instruction(15Ð0)
Instruction(20Ð16)
Instruction(15Ð11)
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
Add ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EXIF/ID EX/MEM MEM/WB
16 32 6 ALU
control
RegDst
ALUOp
ALUSrc
RegWrite
Branch
201\uf6d92004 Morgan Kaufmann Publishers
\u2022 We have 5 stages. What needs to be controlled in each stage?
\u2013 Instruction Fetch and PC Increment
\u2013 Instruction Decode / Register Fetch
\u2013 Execution
\u2013 Memory Stage
\u2013 Write Back
\u2022 How would control be handled in an automobile plant?
\u2013 a fancy control center telling everyone what to do?
\u2013 should we use a finite state machine?
Pipeline control
202\uf6d92004 Morgan Kaufmann Publishers
\u2022 Pass control signals along just like the data
Pipeline Control
Execution/Address Calculation 
stage control lines
Memory access stage 
control lines
Write-back 
stage control 
lines
Instruction
Reg 
Dst
ALU 
Op1
ALU 
Op0
ALU 
Src Branch
Mem 
Read
Mem 
Write
Reg 
write
Mem to 
Reg
R-format 1 1 0 0 0 0 0 1 0
lw 0 0 0 1 0 1 0 1 1
sw X 0 0 1 0 0 1 0 X
beq X 0 1 0 1 0 0 0 X
Control
EX
M
WB
M
WB
WB
IF/ID ID/EX EX/MEM MEM/WB
Instruction
203\uf6d92004 Morgan Kaufmann Publishers