278500-Apresentações
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278500-Apresentações


DisciplinaArquitetura e Organização de Computadores 1277 materiais4.376 seguidores
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Datapath with Control (1)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
204\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (2)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
205\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (2)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
206\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (4)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
207\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (5)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
208\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (6)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
209\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (7)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
210\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (8)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
211\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (9)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
212\uf6d92004 Morgan Kaufmann Publishers
Datapath with Control (10)
WB
M
EX
WB
M WB
PCSrc
MemRead
Add
Address
Instruction
memory
Read
register 1
Read
register 2
Instruction
[15\u20130]
Instruction
[20\u201316]
Instruction
[15\u201311]
Write
register
Write
data
Read
data 1
Read
data 2
Registers Address
Write
data
Read
data
Data
memory
Add Add
result
ALU ALU
result
Zero
Shift
left 2
Sign
extend
PC
4
ID/EX
IF/ID
EX/MEM
MEM/WB
16 632 ALU
control
RegDst
ALUOp
ALUSrc
Branch
Control
213\uf6d92004 Morgan Kaufmann Publishers
\u2022 Problem with starting next instruction before first is finished
\u2013 dependencies that \u201cgo backward in time\u201d are data hazards
Dependencies
Program
execution
order
(in instructions)
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
Time (in clock cycles)
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
10 10 10 10 10/\u201320 \u201320 \u201320 \u201320 \u201320
Value of
register $2:
214\uf6d92004 Morgan Kaufmann Publishers
\u2022 Have compiler guarantee no hazards
\u2022 Where do we insert the \u201cnops\u201d ?
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14, $2, $2
sw $15, 100($2)
\u2022 Problem: this really slows us down!
Software Solution
215\uf6d92004 Morgan Kaufmann Publishers
\u2022 Use temporary results, don\u2019t wait for them to be written
\u2013 register file forwarding to handle read/write to same register
\u2013 ALU forwarding
Forwarding
what if this $2 was $13?
Program
execution
order
(in instructions)
sub $2, $1, $3
and $12, $2, $5
or $13, $6, $2
add $14,$2 , $2
sw $15, 100($2)
Time (in clock cycles)
CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8 CC 9
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
IM DMReg Reg
10 10 10 10 10/\u201320 \u201320 \u201320 \u201320 \u201320Value of register $2:
Value of EX/MEM: X X X \u201320 X X X X X
Value of MEM/WB: X X X X \u201320 X X X X
216\uf6d92004 Morgan Kaufmann Publishers
Forwarding
\u2022 The main idea (some details not shown)
ALU
Data
memory
Registers
M
u
x
M
u
x
M
u
x
M
u
x
ID/EX EX/MEM MEM/WB
Forwarding
unit
EX/MEM.RegisterRd
MEM/WB.RegisterRd
Rs
Rt
Rt
Rd
ForwardB
ForwardA
217\uf6d92004 Morgan Kaufmann Publishers
\u2022 Load