278500-Apresentações
287 pág.

278500-Apresentações


DisciplinaArquitetura e Organização de Computadores 1277 materiais4.375 seguidores
Pré-visualização17 páginas
The Processor: Datapath & Control
127\uf6d92004 Morgan Kaufmann Publishers
\u2022 Abstract / Simplified View:
Two types of functional units:
\u2013 elements that operate on data values (combinational)
\u2013 elements that contain state (sequential)
More Implementation Details
Data
Register #
Register #
Register #
PC Address Instruction
Instruction
memory
Registers ALU Address
Data
Data
memory
AddAdd
4
128\uf6d92004 Morgan Kaufmann Publishers
\u2022 Unclocked vs. Clocked
\u2022 Clocks used in synchronous logic 
\u2013 when should an element that contains state be updated?
State Elements
Clock period Rising edge
Falling edge
cycle time
129\uf6d92004 Morgan Kaufmann Publishers
\u2022 The set-reset latch
\u2013 output depends on present inputs and also on past inputs
An unclocked state element
R
S
Q
Q
130\uf6d92004 Morgan Kaufmann Publishers
\u2022 Output is equal to the stored value inside the element
(don't need to ask for permission to look at the value)
\u2022 Change of state (value) is based on the clock
\u2022 Latches: whenever the inputs change, and the clock is asserted
\u2022 Flip-flop: state changes only on a clock edge
(edge-triggered methodology)
"logically true", 
\u2014 could mean electrically low
A clocking methodology defines when signals can be read and written
\u2014 wouldn't want to read a signal at the same time it was being written
Latches and Flip-flops
131\uf6d92004 Morgan Kaufmann Publishers
\u2022 Two inputs:
\u2013 the data value to be stored (D)
\u2013 the clock signal (C) indicating when to read & store D
\u2022 Two outputs:
\u2013 the value of the internal state (Q) and it's complement
D-latch
Q
C
D
_
Q
D
C
Q
132\uf6d92004 Morgan Kaufmann Publishers
D flip-flop
\u2022 Output changes only on the clock edge
D
C
Q
D
C
D
latch
D
C
Q
D
latch
D
C
Q Q
Q Q
133\uf6d92004 Morgan Kaufmann Publishers
Our Implementation
\u2022 An edge triggered methodology
\u2022 Typical execution:
\u2013 read contents of some state elements, 
\u2013 send values through some combinational logic
\u2013 write results to one or more state elements
State
element
1
State
element
2
Combinational logic
Clock cycle
134\uf6d92004 Morgan Kaufmann Publishers
\u2022 Built using D flip-flops
Register File
Read register
number 1 Read
data 1Read register
number 2
Read
data 2
Write
register
Write
Write
data
Register file
Read register
number 1
Register 0
Register 1
. . .
Register n \u2013 2
Register n \u2013 1
M
u
x
Read register
number 2
M
u
x
Read data 1
Read data 2
Do you understand? What is the \u201cMux\u201d above?
135\uf6d92004 Morgan Kaufmann Publishers
Abstraction
\u2022 Make sure you understand the abstractions!
\u2022 Sometimes it is easy to think you do, when you don\u2019t
M
u
x
C
Select
32
32
32
B
A
M
u
x
Select
B31
A31
C31
M
u
x
B30
A30
C30
M
u
x
B0
A0
C0
.
.
.
.
.
.
136\uf6d92004 Morgan Kaufmann Publishers
Register File
\u2022 Note: we still use the real clock to determine when to write
Write
0
1
n-to-2n
decoder
n \u2013 1
n
Register 0
C
D
Register 1
C
D
Register n \u2013 2
C
D
Register n \u2013 1
C
D
.
.
.
Register number
.
.
.
Register data
137\uf6d92004 Morgan Kaufmann Publishers
Simple Implementation
\u2022 Include the functional units we need for each instruction
PC
Instruction
address
Instruction
Instruction
memory
Add Sum
a. Instruction memory b. Program counter c. Adder
138\uf6d92004 Morgan Kaufmann Publishers
Simple Implementation
\u2022 Include the functional units we need for each instruction
Address Readdata
Data
memory
a. Data memory unit
Write
data
MemRead
MemWrite
b. Sign-extension unit
Sign
extend
16 32
139\uf6d92004 Morgan Kaufmann Publishers
Simple Implementation
\u2022 Include the functional units we need for each instruction
Read
register 1
Read
register 2
Write
register
Write
Data
Registers ALUData
Data
Zero
ALU
result
RegWrite
a. Registers b. ALU
5
5
5
Register
numbers
Read
data 1
Read
data 2
ALU operation4
140\uf6d92004 Morgan Kaufmann Publishers
Building the Datapath
\u2022 Use multiplexors to stitch them together
Read
register 1
Read
register 2
Write
register
Write
data
Write
data
Registers ALU
Add
Zero
RegWrite
MemRead
MemWrite
PCSrc
MemtoReg
Read
data 1
Read
data 2
ALU operation4
Sign
extend
16 32
Instruction ALU
result
Add
ALU
result
M
u
x
M
u
x
M
u
x
ALUSrc
Address
Data
memory
Read
data
Shift
left 2
4
Read
address
Instruction
memory
PC
141\uf6d92004 Morgan Kaufmann Publishers
Control
\u2022 Selecting the operations to perform (ALU, read/write, etc.)
\u2022 Controlling the flow of data (multiplexor inputs)
\u2022 Information comes from the 32 bits of the instruction
\u2022 Example:
add $8, $17, $18 Instruction Format:
000000 10001 10010 01000 00000 100000
op rs rt rd shamt funct
\u2022 ALU's operation based on instruction type and function code
142\uf6d92004 Morgan Kaufmann Publishers
\u2022 e.g., what should the ALU do with this instruction
\u2022 Example: lw $1, 100($2)
35 2 1 100
op rs rt 16 bit offset
\u2022 ALU control input
0000 AND
0001 OR
0010 add
0110 subtract
0111 set-on-less-than
1100 NOR
\u2022 Why is the code for subtract 0110 and not 0011?
Control
143\uf6d92004 Morgan Kaufmann Publishers
\u2022 Must describe hardware to compute 4-bit ALU control input
\u2013 given instruction type 
00 = lw, sw
01 = beq, 
10 = arithmetic
\u2013 function code for arithmetic
\u2022 Describe it using a truth table (can turn into gates):
ALUOp 
computed from instruction type
Control
Instruction RegDst ALUSrc
Memto-
Reg
Reg 
Write
Mem 
Read
Mem 
Write Branch ALUOp1 ALUp0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
Read
reg ister 1
Read
reg ister 2
W rite
reg ister
W rite
data
Write
data
Registers
ALU
Add
Zero
Read
data 1
Read
data 2
S ign
extend
16 32
Instruction
[31\u20130] ALU
result
Add
ALU
result
M
u
x
M
u
x
M
u
x
Address
Data
memory
Read
data
Shift
le ft 2
4
Read
address
Instruction
memory
PC
1
0
0
1
0
1
M
u
x
0
1
ALU
contro l
Instruction [5\u20130]
Instruction [25\u201321]
Instruction [31\u201326]
Instruction [15\u201311]
Instruction [20\u201316]
Instruction [15\u20130]
RegDst
Branch
MemRead
Mem toReg
ALUOp
MemWrite
ALUSrc
RegW rite
Control
145\uf6d92004 Morgan Kaufmann Publishers
Control
\u2022 Simple combinational logic (truth tables)
Operation2
Operation1
Operation0
Operation
ALUOp1
F3
F2
F1
F0
F (5\u20130)
ALUOp0
ALUOp
ALU control block
R-format Iw sw beq
Op0
Op1
Op2
Op3
Op4
Op5
Inputs
Outputs
RegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOpO
146\uf6d92004 Morgan Kaufmann Publishers
\u2022 All of the logic is combinational
\u2022 We wait for everything to settle down, and the right thing to be done
\u2013 ALU might not produce \u201cright answer\u201d right away
\u2013 we use write signals along with clock to determine when to write
\u2022 Cycle time determined by length of the longest path
Our Simple Control Structure
We are ignoring some details like setup and hold times
State
element
1
State
element
2
Combinational logic
Clock cycle
147\uf6d92004 Morgan Kaufmann Publishers
Single Cycle Implementation
\u2022 Calculate cycle time assuming negligible delays except:
\u2013 memory (200ps), ALU and adders (100ps), register file access (50ps)
Read
register 1
Read
register 2
Write
register
Write