LogixProCCZF

destination.
S:0/2 Zero (Z) indicates a 0 value after a math, move, or logic instruction.
S:0/3 Sign (S) indicates a negative (less than 0) value after a math, move, or
logic instruction.
Overflow Trap Bit, S:5/0
Minor error bit (S:5/0) is set upon detection of a mathematical overflow or division
by zero. If this bit is set upon execution of an END statement or a Temporary End
(TND) instruction, or an I/O Refresh (REF), the recoverable major error code 0020
is declared.
In applications where a math overflow or divide by zero occurs, you can avoid a
CPU fault by using an unlatch (OTU) instruction with address S:5/0 in your
program. The rung must be between the overflow point and the END, TND, or REF
statement.
Math Instructions
3–5
Changes to the Math Register, S:13 and S:14
Status word S:13 contains the least significant word of the 32-bit values of the MUL
and DDV instructions. It contains the remainder for DIV and DDV instructions. It
also contains the first four BCD digits for the Convert from BCD (FRD) and
Convert to BCD (TOD) instructions.
Status word S:14 contains the most significant word of the 32-bit values of the MUL
and DDV instructions. It contains the unrounded quotient for DIV and DDV
instructions. It also contains the most significant digit (digit 5) for TOD and FRD
instructions.
Using Floating Point Data File (F8:)
This file type is valid for SLC 5/03 (OS301 and higher), SLC 5/04, and SLC 5/05
processors. These are 2-word elements and addressable only at the element level.
Assign floating point addresses as follows:
Format Explanation
F Floating Point file
Ff:e f File number. Number 8 is the default file. A file number between 9- 255 can
be used if additional storage is required.
: Element delimiter
e Element
number
Ranges from 0- 255. These are 2-word elements.
Non-extended 32-bit numbers
Examples:
F8:2 Element 2, floating point file 8
F10:36 Element 36, floating point file 10 (file 10 designated as a floating
point file by the user)
PrefaceInstruction Set Reference Manual
3–6
Add (ADD)
Use the ADD instruction to add one value (source A) to another value (source B)
and place the result in the destination.
Updates to Arithmetic Status Bits
With this Bit: The Processor:
Carry (C) sets if carry is generated; otherwise resets (integer). For floating point, it is cleared.
Overflow (V)
sets if overflow is detected at destination; otherwise resets. On overflow, the minor error flag is also set. For
floating point, the overflow value is placed in the destination. For an integer, the value –32,768 or 32,767 is
placed in the destination. Exception: If you are using an SLC 5/02 or higher processor or a MicroLogix 1000
controller and have S:2/14 (math overflow selection bit) set, then the unsigned, truncated overflow remains in
the destination.
Zero (Z) sets if result is zero; otherwise resets.
Sign (S) sets if result is negative; otherwise resets.
Subtract (SUB)
Use the SUB instruction to subtract one value (source B) 
from another (source A) and place the result in the destination.
Updates to Arithmetic Status Bits
With this Bit: The Processor:
Carry (C) sets if borrow is generated; otherwise resets (integer). For floating point it is cleared.
Overflow (V)
sets if underflow; otherwise reset. On underflow, the minor error flag is also set. For floating point, the overflow
value is placed in the destination. For an integer, the value –32,768 or 32,767 is placed in the destination.
Exception: If you are using an SLC 5/02 or higher processor or a MicroLogix 1000 controller and have S:2/14
(math overflow selection bit) set, then the unsigned, truncated overflow remains in the destination.
Zero (Z) sets if result is zero; otherwise resets.
Sign (S) sets if result is negative; otherwise resets.
3333 333
ADD
ADD
Source A
Source B
Dest
Output Instruction
3333 333
SUB
SUBTRACT
Source A
Source B
Dest
Output Instruction
Math Instructions
3–7
32-Bit Addition and Subtraction
You have the option of performing 16-bit or 32-bit signed integer addition and
subtraction. This is facilitated by status file bit S:2/14 (math overflow selection bit).
Math Overflow Selection Bit S:2/14
Set this bit when you intend to use 32-bit addition and subtraction. When S:2/14 is
set, and the result of an ADD, SUB, MUL, DIV, or NEG instruction cannot be
represented in the destination address (due to math underflow or overflow):
• The overflow bit S:0/1 is set.
• The overflow trap bit S:5/0 is set.
• The destination address contains the unsigned, truncated, least significant 16
bits of the result.
Note For MUL, DIV, integer, and all floating point instructions with an integer
destination, when S:2/14 is set, the state change takes effect immediately.
When S:2/14 is reset (default condition), and the result of an ADD, SUB, MUL,
DIV, or NEG instruction cannot be represented in the destination address (due to
math underflow or overflow):
• The overflow bit S:0/1 is set.
• The overflow trap bit S:5/0 is set.
• The destination address contains 32767 if the result is positive or –32768 if the
result is negative.
Note Additionally, the SLC 5/03 and higher processors only assert the state of bit S:2/14
at the end of scan for the ADD, SUB, and NEG instructions.
Note that the status of bit S:2/14 has no effect on the DDV instruction. Also, it has
no effect on the math register content when using MUL and DIV instructions.
Note The SLC 5/03 and higher processors only interrogate this bit upon going to the Run
mode and end-of-scan. Use the Data Monitor function to make this selection prior
to entering the Run mode.
33 333
PrefaceInstruction Set Reference Manual
3–8
Example of 32-bit Addition
The following example shows how a 16-bit signed integer is added to a 32-bit
signed integer. Remember that S:2/14 must be set for 32-bit addition.
Note that the value of the most significant 16 bits (B3:3) of the 32-bit number is
increased by 1 if the carry bit S:0/0 is set and it is decreased by 1 if the number
being added (B3:1) is negative.
To avoid a major error from occurring at the end of the scan, you must unlatch
overflow trap bit S:5/0 as shown.
Math Instructions
3–9
(U)
 S:5
0
END
] [
B3
 0
[OSR]
B3
 1
When rung goes true for a
single scan, B3:1 is added
to B3:2. The result is
placed in B3:2.
SUB
SUBTRACT
Source A B3:3
0000000000000011
Source B 1
Dest B3:3
0000000000000011
ADD
ADD
Source A B3:1
0101010110101000
Source B B3:2
0001100101000000
Dest B3:2
0001100101000000
ADD
ADD
Source A 1
Source B B3:3
0000000000000011
Dest B3:3
0000000000000011
] [
S:0
 0
] [
B3
31
Add 16–bit value B3:1 to 32–bit value B3:3 B3:2
Add Operation Binary Hex Decimal
B3:3 B3:2
B3:1
B3:3 B3:2
0000 0000 0000 0011 0001 1001 0100 0000
0101 0101 1010 1000
0000 0000 0000 0011 0110 1110 1110 1000
0003 1940
55A8
0003 6EE8
203,072
21,928
225,000
Addend
Addend
Sum
À
If a carry is generated (S:0/0
set), 1 is added to B3:3.
If B3:1 is negative (B3/31
set), 1 is subtracted from
B3:3.
Overflow trap bit S:5/0 is
unlatched to prevent a major
error from occurring at the
end of the scan.
À
The programming device displays 16-bit decimal values only. The decimal value of a 32-bit integer is derived from the
displayed binary or hex value. For example, 0003 1940 Hex is 164x3 + 163x1 + 162x9 + 161x4 + 160x0 = 203,072.
Application Note: You can use the rung above with a DDV instruction and a