Manual de Soluções - Eletrônica de Potência - Daniel W. Hart

Prévia do material em texto

CHAPTER 1 SOLUTIONS 
 
(1-1) 
 
 
 
(1-2) 
 
 
 
 
 
 
 
 
In part (b), the voltage across the current source is reduced from 24 V by the switch resistance and diode 
voltage drop. 
 
(1-3) 
 
 
 
 
 
 
 
 
 
(1-4) 
 
 
 
 
 
 
CHAPTER 2 SOLUTIONS 
2/21/10 
2-1) Square waves and triangular waves for voltage and current are two examples. 
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2-2) a) 
 b) peak power = 2890 W. 
 c) P = 2890/2 = 1445 W. 
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2-3) 
 v(t) = 5sin2πt V. 
 a) 4sin2πt A.; p(t) = v(t)i(t) = 20 sin22πt W.; P = 10 W. 
 b) 3sin4πt A.; p(t) = 15sin(2πt)sin(4πt) W.; P = 0 
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2-4) a) 
 
 b) 
 
 c) 
 
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2-5) a) 
 
 
 b) 
 
 
 c) 
 
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2-6) 
 
 
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2-7) 
 a) 
 
 
 b) 
 
 
 c) 
 
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2-8) Resistor: 
 
 Inductor: 
 dc source: 
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2-9) a) With the heater on, 
 
 b) P = 1500(5/12) = 625 W. 
 c) W = PT = (625 W)(12 s) = 7500 J. (or 1500(5) = 7500 W.) 
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2-10) 
 
 a) 
 
 
 b) All stored energy is absorbed by R: WR = 0.648 J. 
 
 c) 
 
 
 d) No change in power supplied by the source: 16.2 W. 
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2-11) 
 a) 
 
 b) Energy stored in L must be transferred to the resistor in (20 - 11.1) = 8.9 ms. Allowing five time 
constants, 
 
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2-12) 
 a) i(t) = 1800t for 0 < t < 4 ms 
 i(4 ms) = 7.2 A.; WLpeak = 1.296 J. 
 
 b) 
 
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2-13) 
 a) The zener diode breaks down when the transistor turns off to maintain inductor current. 
 b) Switch closed: 0 < t < 20 ms. 
 
 
 Switch open, zener on: 
 
 Therefore, inductor current returns to zero at 20 + 30 = 50 ms. 
 iL = 0 for 50 ms < t < 70 ms. 
 
 c) 
 
 
 d) 
 
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2-14) a) The zener diode breaks down when the transistor turns off to maintain inductor current. 
 b) Switch closed: 0 < t < 15 ms. 
 
 
 
 
 Switch open, zener on: 
 
 Therefore, inductor current returns to zero at 15 + 30 = 45 ms. 
 iL = 0 for 45 ms < t < 75 ms. 
 
 c) 
 
 
 
 d) 
 
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2-15) Examples are square wave (Vrms = Vm) and a triangular wave (Vrms = Vm/√3). 
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2-16) Phase conductors: 
 Neutral conductor: 
 
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2-17) Re: Prob. 2-4 
 
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2-18) Re: Prob. 2-5 
 
 
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2-19) 
 
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2-20) 
 
 
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2-21) dc Source: 
 
 
 
 Resistor: 
 
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2-22) 
 
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2-23) 
 
n Vn In Pn ∑Pn 
0 20 5 100 100 
1 20 5 50 150 
2 10 1.25 6.25 156.25 
3 6.67 0.556 1.85 158.1 
4 5 0.3125 0.781 158.9 
Power including terms through n = 4 is 158.9 watts. 
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2-24) 
 
n Vn In θn - ϕn° Pn 
0 50.0000 10.0 0 500.0 
1 50.0000 10.0 26.6 223.6 
2 25.0000 2.5 45.0 22.1 
3 16.6667 1.11 56.3 5.1 
4 12.5000 0.625 63.4 1.7 
Through n = 4, ∑Pn = 753 W. 
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2-25) 
 
 
Resistor Average Power 
n Vn Zn In angle Pn 
0 50.00 20.00 0.7 0.00 9.8 
1 127.32 25.43 5.01 0.67 250.66 
2 63.66 37.24 1.71 1.00 29.22 
3 42.44 51.16 0.83 1.17 6.87 
4 31.83 65.94 0.48 1.26 2.33 
5 25.46 81.05 0.31 1.32 0.99 
PR = ∑ Pn ≈ 300 W. 
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2-26) a) THD = 5% → I9 = (0.05)(10) = 0.5 A. 
 b) THD = 10% → I9 = (0.10)(10) = 1 A. 
 c) THD = 20% → I9 = (0.20)(10) = 2 A. 
 d) THD = 40% → I9 = (0.40)(10) = 4 A. 
 
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2-27) a) 
 
 
 
 
 
 
 b) 
 
 c) 
 
 
 
d) 
 
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2-28) a) 
 
 b) 
 
 c) 
 
 d) 
 
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2-29) 
 
 
 a) 
 
 b) 
 
 c) 
 
 d) 
 
 e) 
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2-30) 
 
 
 a) 
 
 b) 
 
 c) 
 
 d) 
 
 e) 
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2-31) 
 
 
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2-32) PSpice shows that average power is 60 W and energy is 1.2 J. Use VPULSE and IPULSE for the 
sources. 
 
 
 
 
 
 
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2-33) Average power for the resistor is approximately 1000 W. For the inductor and dc source, the 
average power is zero (slightly different because of numerical solution). 
 
 
 
 
 
 
 
 
 
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2-34) 
 
 
 
 
 
 
 
 
 
 
Rms voltage is 8.3666 V. Rms current is 5.2631 A. 
 
 
 
 
 
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2-35) See Problem 2-10. 
 
 
 
 
 
 
 
 
The inductor peak energy is 649 mJ, matching the resistor absorbed energy. The source power is -16.2 
W absorbed, meaning 16.2 W supplied. 
 
b) If the diode and switch parameters are changed, the inductor peak energy is 635 mJ,and the resistor 
absorbed energy is 620 mJ. The difference is absorbed by the switch and diode. 
 
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2-36) 
 
The inductor current reaches a maximum value of 3.4 A with the resistances in the circuit: I = 
75/(20+1+1) = 3.4 A. 
 
Quantity Probe Expression Result 
Inductor resistor average power AVG(W(R1)) 77.1 W 
Switch average power AVG(W(S1)) 3.86 W each 
Diode average power AVG(W(D1)) 81 mW each 
Source average power AVG(W(Vcc)) -85.0 W 
 
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2-37) 
a) Power absorbed by the inductor is zero. Power absorbed by the Zener diode is 13.8 W. 
 
 
 
 
 
b) Power in the inductor is zero, but power in the 1.5Ω resistor is 1.76 W. Power absorbed by the Zener 
diode is 6.35 W. Power absorbed by the switch is 333 mW. 
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3-38) 
See Problem 3-37 for the circuit diagram. 
a) Power absorbed by the Zener diode is 36.1 W. Power absorbed by the inductor is zero. 
 
 
b) Power in the inductor is zero, but power in the 1.5Ω resistor is 4.4 W. Power absorbed by the Zener 
diode is 14.2 W. Power absorbed by the switch is 784 mW. 
 
 
2-39) 
 
 
 
 
 
 
 
 
 
 
 
 
Quantity Probe Expression Result 
Power AVG(W(V1)) 650 W 
rms current RMS(I(V1)) 14 A 
Apparent power S RMS(V(I1:+))* RMS(I(V1)) 990 VA 
Power factor AVG(W(V1)) / (RMS(V(I1:+))* RMS(I(V1))) 0.66 
 
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2-40) 
 
 
DESIRED QUANTITY ORIGINAL RESULT NEW VALUES 
Inductor Current max = 4.5 A. 4.39 A 
Energy Stored in Inductor max = 2.025 J 1.93 L 
Average Switch Power 0.010 W. 0.66 W 
Average Source Power (absorbed) -20.3 W. -19.9 W 
Average Diode Power AVG(W(D1)) 0.464 W. 0.464 W. .449 W 
Average Inductor Power 0 0 
Average Inductor Voltage 0 0 
Average Resistor Power 19.9 W. 18.8 W 
Energy Absorbed by Resistor 1.99 J. 1.88 J 
Energy Absorbed by Diode .046 J. .045 J 
Energy Absorbed by Inductor 0 0 
rms Resistor Current 0.998 A. 0.970 A 
 
 
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2-41) Use the part VPULSE or IPULSE (shown). Here, the period is 100 ms, and the rise times chosen are 
20 ms, 50 ms, and 80 ms. The fall times are the period minus the rise times. Each rms value is 0.57735, 
which is identical to 1/√3. 
 
 
 
 
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CHAPTER 3 SOLUTIONS 
2/20/10 
3-1) 
 
3-2) 
 
 
 
 
 
 
 
 
3-3) 
 
3-4) Using Eq. 3-15, 
 
 
 
 
 
 
 
3-5) Using Eq. 3-15, 
 
3-6) Using Eq. 3-15, 
 
 
 
 
 
3-7) Using an ideal diode model, R = 48 Ω for an average current of 2 A. 
 
 
 
 
 
 
 
 
 
 
 
3-8) Using Eqs. 3-22 and 3-23, 
 
3-9) Using Eqs. 3-22 and 3-23, 
 
 
 
3-10) Using Eq. 3-33, 
 
 
3-11) 
 
 
 
 
 
 
3-12) L ≈ 0.14 H for 50 W (51 W). 
 
 
 
 
 
 
3-13) Using Eq. 3-34, 
 a) 
 
b) 
n Vn Zn In 
0 54.02 12.00 4.50 
1 84.85 25.6 3.31 
2 36.01 46.8 0.77 
4 7.20 91.3 0.08 
The terms beyond n = 1 are insignificant. 
 
3-14) 
 
Run a transient response long enough to achieve steady-state results (e.g., 1000ms). The peak-to-
peak load current is approximately 1.48 A, somewhat larger than the 1.35 A obtained using only 
the first harmonic. (The inductance should be slightly larger, about 0.7 H, to compensate for the 
approximation of the calculation.) 
 
 
 
 
 
 
 
3-15) 
a) 
 
b) A PSpice simulation using an ideal diode model gives 0.443 A p-p in the steady state. This 
compares with 2(I1)=2(0.199)=0.398 A p-p. 
 
3-16) 
 
3-17) a) τ = RC = 10310-3=1 s; τ/T = 60. With τ >> T, the exponential decay is very small 
and the output voltage has little variation. 
 b) Exact equations: 
 
 c) Approximation of Eq. 3-51: 
 
3-18) a) R = 100 Ω: τ = RC (100)10-3 = 0.1 s; τ/T = 6. 
 
 b) R = 10 Ω: τ = RC (10)10-3 = 0.01 s; τ/T = .6. 
 
 In (a) with τ/T=6, the approximation is much more reasonable than (b) where τ/T=0.6. 
 
 
 
3-19) a) With C = 4000 µF, RC = 4 s., and the approximation of Eq. 3-51 should be reasonable. 
 
 b) With C = 20 µF, RC = 0.02, which is on the order of one source period. Therefore, the 
approximation will not be reasonable and exact equations must be used. 
 
3-20) a) With C = 4000 µF, RC = 2 s., and the approximation of Eq. 3-51 should be reasonable. 
 
 b) With C = 20 µF, RC = 0.01, which is on the order of one source period. Therefore, the 
approximation will not be reasonable and exact equations must be used. 
 
3-21) From Eq. 3-51 
 
 
3-22) Assuming Vo is constant and equal to Vm, 
 
 From Eq. 3-51 
 
3-23) Using the definition of power factor and Vrms from Eq. 3-53, 
 
3-24) 
 
 
 
3-25) 
 
3-26) 
 
3-27) 
 
 
3-28) α ≈ 46°. Do a parametric sweep for alpha. Use the default (Dbreak) diode, and use Ron = 
0.01 for the switch. Alpha of 46 degrees results in approximately 2 A in the load. 
 
 
 
 
 
 
 
 
3-29) α ≈ 60.5°. Do a parametric sweep for alpha. Use the default (Dbreak) diode, and use Ron 
= 0.01 for the switch. Alpha of 60.5 degrees results in approximately 1.8 A in the load. 
 
 
 
 
 
 
 
 
3-30) From Eq. 3-61, 
 
3-31) From Eq. 3-61, 
 
 
 
 
3-32) α ≈ 75°. Alpha = 75 degrees gives 35 W in the dc voltage source. An Ron = 0.01 for the 
switch and n = 0.001 for the diode (ideal model). 
 
 
 
 
 
 
 
 
 
 
 
 
3-33) From Eq. 3-61, 
 
3-34) α ≈ 81° 
3-35) 
 
3-36) 
 v0 = vs when S1 on, v0=0 when D2 on 
 
 
 
 
3-37) 
 
PSpice: 
Use a current source for the constant load current: 
 
 
 
 
 
 
 
 
 
D1 to D2 
 
 
 
 
 
 
D2 to D1 
 
 
 
 
 
 
3-38) u = 20°. Run the simulation long enough for steady-state results. From the Probe output, 
the commutation angle from D1 to D2 is about 20 degrees, and from D2 to D1 is about 18 
degrees. Note that the time axis is changed to angle in degrees here. 
 
 
 
 
 
 
 
 
 
 
 
3-39) Run the simulation long enough for steady-state results. From the Probe output, the 
commutation angle from D1 to D2 is about 16.5 degrees, and from D2 to D1 is about 14.7 
degrees. Note that the time axis is changed to angle in degrees here. 
 
 
 
 
 
 
 
 
 
3-40) At ωt = π, D2 turns on, D1 is on because of the current in LS (see Fig. 3-17). 
 
 
 
 
 
3-41) At ωt = α, 
 
3-42) A good solution is to use a controlled half-wave rectifier with an inductor in series with the 
48-V source and resistance (Fig. 3-15). The switch will change the delay angle of the SCR to 
produce the two required power levels. The values of the delay angle depend on the value 
selected for the inductor. This solution avoids adding resistance, thereby avoiding introducing 
power losses.3-43) Several circuit can accomplish this objective, including the half-wave rectifier of Fig. 3-2a 
and half-wave rectifier with a freewheeling diode of Fig. 3-7, each with resistance added. 
Another solution is to use the controlled half-wave rectifier of Fig. 3-14a but with no resistance. 
The analysis of that circuit is like that of Fig. 3-6 but without Vdc. The resulting value of α is 75°, 
obtain from a PSpice simulation. That solution is good because no resistance is needed, and 
losses are not introduced. 
3-44 and 3-45) The controlled half-wave rectifier of Fig. 3-15 (without the resistance) can be 
used to satisfy the design specification. The value of the delay angle depends on the value 
selected for the inductor. 
 
CHAPTER 4 SOLUTIONS 
2/17/10 
4-1) Load: 
 
 Each diode: 
 
4-2) 
 
4-3) 
 
 
 
4-4) 
 
 
 
4-5) 
 
 b) Power is determined from the Fourier series. Using Eq. 4-4 and 4-5. 
n Vn, V. Zn. Ω In, A. 
2 72.0 27.1 2.65 
4 14.4 47.7 0.302 
 
 
4-6 
 
 
 b) Power is determined from the Fourier series. Using Eq. 4-4 and 4-5. 
n Vn, V. Zn. Ω In, A. 
2 72.0 19.3 3.74 
4 14.4 32.5 0.444 
 
 
 
4-7) 
 
4-8) Load: 
 
4-9) 
 
4-10) 
 
4-11) 
 
 b) Fourier Series 
n Vn, V. Zn. Ω In, A. 
2 72.2 11.7 6.16 
4 14.4 22.8 0.631 
 
 
 
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4-12 
 
 b) Fourier Series 
n Vn, V. Zn. Ω In, A. 
2 144.3 30.6 4.72 
4 28.9 60.5 0.477 
 
 
 
4-13) 
4-14) a) Continuous current; P=474 W. 
 b) Discontinuous current; P=805 W. 
4-15 
 
 b) Fourier Series 
n Vn, V. Zn. Ω In, A. 
2 72.0 30.4 2.37 
4 14.4 60.5 0.238 
 
 
 
4-16 
 
 
 b) Fourier Series 
n Vn, V. Zn. Ω In, A. 
2 72.0 45.5 1.58 
4 14.4 90.6 0.159 
 
 
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4-17) 
 
The current with the 100 μH inductor is discontinuous. 
 
 
4-18) 
 
4-19) 
 
4-20) C ≈ 3333/2 = 1667 µF. Peak diode currents are the same. Fullwave circuit has 
advantages of zero average source current, smaller capacitor, and average diode current ½ that 
for the halfwave. The halfwave circuit has fewer diodes, and has only one diode voltage drop 
rather than two. 
4-21) 
 > 1  continuous current 
 
 
 < 1  
Calculated Vo is slightly larger than initial estimate. Try Vo=120 V.: 
 
Therefore, 119 < Vo < 120 V. (Vo=119.6 with more iterations.) 
 
c) PSpice results: 
 
R = 7 results in continuous current with Vo = 108 V. R = 20 results in discontinuous current with Vo = 
120 V. The simulation was done with C = 10,000 μF. 
4-22) PSpice results with a 0.5 Ω resistance in series with the inductance: For Rload = 5 Ω, 
Vo=56.6 V. (compared to 63.7 volts with an ideal inductor); for Rload = 50 Ω, Vo=82.7 V. 
(compared to 84.1 volts with an ideal inductor). 
4-23) 
 
 
4-24) 
 
4-25) a) α = 15° : Check for continuous current. First period: 
 
 b) α = 75° Check for continuous current. First period: 
 
 
4-26)a) α = 20°: Check for continuous current. First period: 
 
 b) α = 80°: Check for continuous current. First period: 
 
4-27) The source current is a square wave of ±Io. 
 
 
 
4-28) 
 
 
Note that the turns ratio could be lower (higher secondary voltage) and α adjusted accordingly. 
4-29) 
 
4-30) 
 
 
4-31) 
 
Choose L somewhat larger, say 120 mH, to allow for approximations. 
 
4-32) In Fig. 4-14, Pac = Pbridge = -VoIo = 1000 W. Using Vdc = -96 V gives this solution: 
 
 
 
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4-33) 
 
4-34) 
 
 
4-35) 
 
 
 
4-36) 
 
4-37) 
There are no differences between the calculations in Problem 4.36 and the PSpice results. The 
power absorbed by each diode ia approximately 1.9 W. 
4-38)Equation (4-46) gives values of of I1 = 28.6 A, I5 = 5.71 A, I7 = 4.08 A, I11 = 2.60 A, and I13 
= 2.20 A. All compare well with the PSpice results. The total harmonic distortion (THD) is 
27.2% when including harmonics through n = 13. 
 
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4-39) 
 
 c) 
 
 
 
 
 
4-40) 
 
c) 
 
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4-41) 
 
4-42) 
 
 
4-43) 
 
4-44) 
 
 
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4-45) 
 
 
4-46) 
 
 
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4-47) 
 
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4-48) 
 
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4-49) 
 
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4-50) 
 
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4-51) 
 
 
 
Uncontrolled rectifiers with additional resistances added can also satisfy the specifications. 
However, adding resistance would increase power loss and decrease efficiency. 
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CHAPTER 5 SOLUTIONS 
 
3/9/10 
 
 
 
5-1) 
 
 
 
 
 
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5-2) 
 
 
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5-3) 
 
 
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5-4) 
 
 
 
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5-5) 
 
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5-6) 
 
 
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5-7) 
 
 
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5-8) 
 
 
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5-9) S1 is on from α to π, and D2 is on from π to 2π. 
 
 
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5-10) 
 
 
 
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5-11) a) Using Eq. 5-9, 
 
 
 
 
 
 
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5-12) Using Eq. 5-9, 
 
 
 
 
 
 
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5-13) Using Eq. 5-9, 
 
 
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5-14) Using Eq. 5-9, 
 
 
PSpice: P = AVG(W(R)) in Probe gives523 W (read at the end of the trace). The difference between 
PSpice and the theoretical output is because of the nonideal SCR model in PSpice. The PSpice result will 
be more realistic. The THD is 22.4% from the PSpice output file using Fourier terms through n = 9. 
 
 
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5-15) Use the PSpice circuit of Example 5-3. The .STEP PARAM command is quite useful for determining 
α. (a) α ≈ 81° for 400 W. (b) α ≈ 46° for 700 W. 
 
SINGLE-PHASE VOLTAGE CONTROLLER (voltcont.cir) 
*** OUTPUT VOLTAGE IS V(3), OUTPUT CURRENT IS I(R) *** 
**************** INPUT PARAMETERS ********************* 
.PARAM VS = 120 ; source rms voltage 
.PARAM ALPHA = 81 ; delay angle in degrees 
.STEP PARAM ALPHA 10 90 20 ; try several values of alpha. Modify the range for more precision 
.PARAM R = 15 ; load resistance 
.PARAM L = 15mH ; load inductance 
.PARAM F = 60 ; frequency 
 
.PARAM TALPHA = {ALPHA/(360*F)} ; converts angle to time delay 
.PARAM PW = {0.5/F} ; pulse width for switch control 
***************** CIRCUIT DESCRIPTION ********************* 
VS 1 0 SIN(0 {VS*SQRT(2)} {F}) 
S1 1 2 11 0 SMOD 
D1 2 3 DMOD ; forward SCR 
S2 3 5 0 11 SMOD 
D2 5 1 DMOD ; reverse SCR 
R 3 4 {R} 
L 4 0 {L} 
**************** MODELS AND COMMANDS ******************** 
.MODEL DMOD D(n=0.01) 
.MODEL SMOD VSWITCH (RON=.01) 
VCONTROL 11 0 PULSE(-10 10 {TALPHA} 0 0 {PW} {1/F}) ;control for both switches 
.TRAN .1MS 50MS 0MS 1u UIC ; one period of output 
.FOUR 60 I(R) ; Fourier Analysis to get THD 
.PROBE 
.END 
 
 
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5-16) Modify the PSpice circuit file of Example 5-3. Use the .STEP PARAM command (see Prob. 5-15) for 
determining α. (a) α ≈ 80° for 600 W. (b) α ≈ 57° for 1000 W. 
_____________________________________________________________________________________ 
 
5-17) The single-phase voltage controller of Fig. 5-4a is suitable for this application. Equation (5-9) 
applies for each half-period of the input sine wave. For 250 W delivered to the load, each half period 
must deliver 125 W. Therefore, the rms value of the current in Eq. (5-9) must be 2.28 A, found by using 
I2R = 125. A closed-form solution is not possible, but trial-and-error numerical techniques give α ≈ 74°. A 
similar but perhaps easier method is to use PSpice simulations using the PSpice A/D circuit file in 
Example 5-3. Modifying the diode model to .MODEL DMOD D(n=.01) to represent an ideal diode, and 
with trial-and-error values of α, gives α ≈ 74°. 
 
The average and rms currents are determined from a numerical integration of the current expression 
from Eq. (5-9) or from a PSpice simulation. ISCR,avg = 1.3 A, ISCR,rms = 2.3 A. The maximum voltage across the 
switches is 120√2sin(74°) = 163 V. 
 
 
5-18) The PSpice circuit file is shown below. The total average load power is three times the power in 
one of the phase resistors. Enter 3*AVG(W(RA)) in Probe. The results are (a) 6.45 kW for 20°, (b) 2.79 
kW for 80°, and (c) 433 W for 115°. Note that the .STEP PARAM command can be used to run the three 
simulations at once. 
 
THREE-PHASE VOLTAGE CONTROLLER -- R-L LOAD (3phvc.cir) 
*SOURCE AND LOAD ARE Y-CONNECTED (UNGROUNDED) 
********************** INPUT PARAMETERS **************************** 
.PARAM Vs=480 ; rms line-to-line voltage 
.PARAM ALPHA=20 ; delay angle in degrees 
.STEP PARAM ALPHA LIST 20 80 115 
.PARAM R=35 ; load resistance (y-connected) 
.PARAM L = 1p ; load inductance 
.PARAM F=60 ; source frequency 
********************** COMPUTED PARAMETERS ************************** 
.PARAM Vm={Vs*SQRT(2)/SQRT(3)} ; convert to peak line-neutral volts 
.PARAM DLAY={1/(6*F)} ; switching interval is 1/6 period 
.PARAM PW={.5/F} TALPHA={ALPHA/(F*360)} 
.PARAM TRF=10US ; rise and fall time for pulse switch control 
*********************** THREE-PHASE SOURCE ************************** 
VAN 1 0 SIN(0 {VM} 60) 
VBN 2 0 SIN(0 {VM} 60 0 0 -120) 
VCN 3 0 SIN(0 {VM} 60 0 0 -240) 
***************************** SWITCHES ******************************** 
S1 1 8 18 0 SMOD ; A-phase 
D1 8 4 DMOD 
S4 4 9 19 0 SMOD 
D4 9 1 DMOD 
 
S3 2 10 20 0 SMOD ; B-phase 
D3 10 5 DMOD 
S6 5 11 21 0 SMOD 
D6 11 2 DMOD 
 
S5 3 12 22 0 SMOD ; C-phase 
D5 12 6 DMOD 
S2 6 13 23 0 SMOD 
D2 13 3 DMOD 
***************************** LOAD ********************************** 
RA 4 4A {R} ; van = v(4,7) 
LA 4A 7 {L} 
 
RB 5 5A {R} ; vbn = v(5,7) 
LB 5A 7 {L} 
 
RC 6 6A {R} ; vcn = v(6,7) 
LC 6A 7 {L} 
************************* SWITCH CONTROL ***************************** 
V1 18 0 PULSE(-10 10 {TALPHA} {TRF} {TRF} {PW} {1/F}) 
V4 19 0 PULSE(-10 10 {TALPHA+3*DLAY} {TRF} {TRF} {PW} {1/F}) 
V3 20 0 PULSE(-10 10 {TALPHA+2*DLAY} {TRF} {TRF} {PW} {1/F}) 
V6 21 0 PULSE(-10 10 {TALPHA+5*DLAY} {TRF} {TRF} {PW} {1/F}) 
V5 22 0 PULSE(-10 10 {TALPHA+4*DLAY} {TRF} {TRF} {PW} {1/F}) 
V2 23 0 PULSE(-10 10 {TALPHA+DLAY} {TRF} {TRF} {PW} {1/F}) 
************************ MODELS AND COMMANDS ************************* 
.MODEL SMOD VSWITCH(RON=0.01) 
.MODEL DMOD D 
.TRAN .1MS 50MS 16.67ms 10US UIC 
.FOUR 60 I(RA) ; Fourier analysis of line current 
.PROBE 
.OPTIONS NOPAGE ITL5=0 
.END 
 
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5-19) The PSpice input file from Example 5-4 is used for this simulation. In Probe, enter the expression 
3*AVG(W(RA)) to get the total three-phase average power in the load, resulting in 368 W. Switch S1 
conducts when the current in phase A is positive, and S4 conducts when the current is negative. 
 
_____________________________________________________________________________________ 
 
 
5-20) The smallest value of α is 120°. The conduction angel must be less than for equal to 60°. The 
extinction angle is 180°, so α is 120° or greater. 
 
_____________________________________________________________________________________ 
 
 
5-21) 
 
THREE-PHASE VOLTAGE CONTROLLER -- R-L LOAD 
*MODIFIED FOR A DELTA-CONNECTED LOAD 
*SOURCE IS Y-CONNECTED (UNGROUNDED) 
********************** INPUT PARAMETERS **************************** 
.PARAM Vs=480 ; rms line-to-line voltage 
.PARAM ALPHA=45 ; delay angle in degrees 
.PARAM R=25 ; load resistance (y-connected) 
.PARAM L = 1p ; load inductance 
.PARAM F=60 ; source frequency 
********************** COMPUTED PARAMETERS ************************** 
.PARAM Vm={Vs*SQRT(2)/SQRT(3)} ; convert to peak line-neutral volts 
.PARAM DLAY={1/(6*F)} ; switching interval is 1/6 period 
.PARAM PW={.5/F} TALPHA={ALPHA/(F*360)} 
.PARAM TRF=10US ; rise and fall time for pulse switch control 
*********************** THREE-PHASE SOURCE ************************** 
VAN 1 0 SIN(0 {VM} 60) 
VBN 2 0 SIN(0 {VM} 60 0 0 -120) 
VCN 3 0 SIN(0 {VM} 60 0 0 -240) 
***************************** SWITCHES ******************************** 
S1 1 8 18 0 SMOD ; A-phase 
D1 8 4 DMOD 
S4 4 9 19 0 SMOD 
D49 1 DMOD 
 
S3 2 10 20 0 SMOD ; B-phase 
D3 10 5 DMOD 
S6 5 11 21 0 SMOD 
D6 11 2 DMOD 
 
S5 3 12 22 0 SMOD ; C-phase 
D5 12 6 DMOD 
S2 6 13 23 0 SMOD 
D2 13 3 DMOD 
***************************** LOAD ********************************** 
RA 4 4A {R} ; 
LA 4A 2 {L} 
 
RB 5 5A {R} ; 
LB 5A 3 {L} 
 
RC 6 6A {R} ; 
LC 6A 1 {L} 
************************* SWITCH CONTROL ***************************** 
V1 18 0 PULSE(-10 10 {TALPHA} {TRF} {TRF} {PW} {1/F}) 
V4 19 0 PULSE(-10 10 {TALPHA+3*DLAY} {TRF} {TRF} {PW} {1/F}) 
V3 20 0 PULSE(-10 10 {TALPHA+2*DLAY} {TRF} {TRF} {PW} {1/F}) 
V6 21 0 PULSE(-10 10 {TALPHA+5*DLAY} {TRF} {TRF} {PW} {1/F}) 
V5 22 0 PULSE(-10 10 {TALPHA+4*DLAY} {TRF} {TRF} {PW} {1/F}) 
V2 23 0 PULSE(-10 10 {TALPHA+DLAY} {TRF} {TRF} {PW} {1/F}) 
************************ MODELS AND COMMANDS ************************* 
.MODEL SMOD VSWITCH(RON=0.01) 
.MODEL DMOD D 
.TRAN .1MS 50MS 16.67ms 10US UIC 
.FOUR 60 I(RA) ; Fourier analysis of line current 
.PROBE 
.OPTIONS NOPAGE ITL5=0 
.END 
 
 
_____________________________________________________________________________________ 
 
5-22) The PSpice circuit file modification must include a very large resistor (e.g., one megaohm) 
connected between the neutral of the load to ground to prevent a “floating node” error because of the 
series capacitor. The steady-state phase A current has two pulses for each of the switches, assuming 
that the gate signal to the SCRs is continuously applied during the conduction interval. The rms current 
is approximately 5.52 A. The total average power for all three phases is approximately 1.28 kW. The THD 
for the load current is computed as 140% for harmonics through n = 9 in the .FOUR command. However, 
the current waveform is rich in higher-order harmonics and the THD is approximately 300% for n = 100. 
It should be noted that this load is not conducive for use with the voltage controller because the load 
voltage will get extremely large (over 5 kV) because of stored charge on the capacitor. 
 
 
 
_____________________________________________________________________________________ 
 
 
5-23) With the S1-S4 switch path open, the equivalent circuit is as shown. The current in phase A is zero, 
so the voltage across the phase-A resistor is zero. The voltage at the negative of V14 is then Vn, and the 
voltage at the positive of V14 is Va. The voltage across the phase B resistor is half of the voltage from 
phase B to phase C, resulting in 
 
 
 
 
 
CHAPTER 6 SOLUTIONS 
5/17/10 
6-1) 
 
 
6-2) 
 
 
 
6-3) 
 
 
6-4) 
 
 
 
6-5) 
 
 
6-6) 
 
 
 
 
 
 
 
 
 
 
6-7) 
 
 
6-8) 
 
 
 
 
 
 
 
6-9) 
 
 
 
6-10) 
 
Vo=5 V 
 
Vs, V D I, A. R, Ω Lmin, µH 
10 0.5 0.5 10 12.5 
10 0.5 1.0 5 6.25 
15 1/3 0.5 10 16.7 (worst case, D = 1/3, R = 10) 
15 1/3 1.0 5 8.33 
 
 
 
 
 
 
 
6-11) Example design: 
 
 
Other values of L and C are valid if the inductor current is continuous with margin. 
 
 
 
6-12) (Based on the example design in 6-11) 
 
 
Vmax, switch = Vs = 48 V 
Vmax, diode = Vs = 48 V 
Imax, switch = ILmax = 1.5 + 0.75/2 = 1.875 A 
Iavg, switch = 
Irms, switch 
 
Imax,diode = ILmax = 1.875 A 
Iavg,diode =IL- Iavg,switch = 1.875 – 0.586 = 1.289 A 
 
Irms,diode 
 
 
 
 
 
 
 
 
6-13) Example design: 
 
 
 
 
 
 
6-14) Example design: 
 
 
 
Other values of L and C are valid if the inductor current is continuous with margin. 
 
 
 
 
 
 
 
 
 
6-15) 
 
 
 The output voltage is mainly the dc term and the first ac term. 
 
 
 
6-16) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
6-17) 
 
 
 
 
6-18) 
 
 
 
Inductor current: (see Example 2-8) 
 
Capacitor current: (define t=0 at peak current) 
 
 
 
6-19) 
 
 
 
 
6-20) Example design: 
 
 
 
 
 
6-21) 
 
 
 
6-22) 
 
 
 
 6-23) 
 
 
6-24) 
 
 
 
 
 
 
 
 
Inductor current: (see Example 2-8) 
 
 
Capacitor current: For convenience, redefine t = 0 at the peak current. The current is then expressed as 
 
 
 
 
 
 
6-25) 
 
 
 
 
6-26) Example design: 
 
 
 
 
6-27) Example design: 
 
 
 
 
6-28) Using the equations 
 
 
 
 and using f = 100 kHz (designer’s choice), results are shown in the table. 
 
Vs, (V) P (W) D R (Ω) Lmin (µH) IL (A) C (µF) 
10 10 0.545 14.4 14.9 1.83 37.9 
10 15 0.545 9.6 9.9 2.75 56.8 
14 10 0.462 14.4 20.9 1.55 32.1 
14 15 0.462 9.6 13.9 2.32 48.1 
 
The value of L should be based on Vs = 14 V and P = 10 W, where Lmin = 20.9 µH. Select the value of L 
at least 25% larger than Lmin (26.1 µF). Using another common criterion of ΔiL = 40% of IL, again for 14 
V and 10 W, L = 104 µH. 
 
The value of C is 56.8 µF for the worst case of Vs = 10 V and P = 10 W. 
 
 
6-29) 
 
 
6-30) 
 
 
6-31) Example design: 
 
 
 
 
 
 
 
 
 
6-32) 
 
 
 
6-33) 
 
 
 
 
6-34) Equation (6-69) for the average voltage across the capacitor C1 applies: 
 
 
 
When the switch is closed, the voltage across L2 for the interval DT is 
 
 
 
Assuming that the voltage across C1 remains constant at its average value of Vs 
 
 
 
When the switch is open in the interval (1 - D)T, 
 
 
 
Since the average voltage across an inductor is zero for periodic operation, 
 
 
resulting in 
 
 
 
6-35) 
 
 
 
 
 
 
6-36) 
 
 
 
 
6-37) 
 
 
6-38) 
 
6-39) 
 
 
6-40) 
 
 
6-41) Discontinuous current for the buck-boost converter: Let DT be the time that the switch is closed 
and D1T be the time that the switch is open and the current in the inductor is positive. For a lossless 
converter, the output power is the same as the input power. 
 
 
 
 
6-42) When switches “1” are closed, C1 and C2 are connected in series, each having Vs/2 volts. When the 
“1” switches are opened and the “2” switches are closed, Vo = Vs of the source plus Vs/2 of C1, making Vo 
= 1.5Vs. 
 
 
6-43) 
 
 
 
 
 
 
 
 
 
 
 
 
 
6-44) Simulate the buck converter of Example 6-1 using PSpice. (a) Use an ideal switch and ideal diode. 
Determine the output ripple voltage. Compare your PSpice results with the analytic results in Example 6-
1. (b) Determine the steady-state output voltage and voltage ripple using a switch with an on resistance of 
2 Ω and the default diode model 
 
 
 
 
 
Using Ron =0.01 for the switch and n=0.01 for the diode, the p-p ripple voltage is 93.83 mV. 93.83/20 = 
0.469%, agreeing precisely with the analytical results. 
 
 
With Ron = 2 ohms, the p-p ripple is 90 mV, with a reduced average value. 
 
 
 
 
6-45) 
Note that for each converter topology, the average voltage across each inductor is zero, and the average 
current in each capacitor iszero. 
 
Buck Converter: 
Show from Eqs. (6-9) and (6-17) 
 
 
From the averaged circuit of Fig. 6.33b, 
 
 
 
 
 
Boost Converter: 
Show from Eqs. (6-27) and (6-28) that 
 
 
From the averaged circuit of Fig. 6.33c, 
 
 
 
 
 
 
 
 
Buck-Boost Converter: 
Show from Eqs. (6-47) and (6-49) and preceding equations that 
 
 
From the averaged circuit of Fig. 6.33d, 
 
 
 
 
 
 
 
 
Ćuk Converter: 
Show from Eqs. (6-59) and (6-61) that 
 
From the averaged circuit, 
 
 
 
 
 
 
CHAPTER 7 SOLUTIONS 
 
4/03/10 
7-1) 
 
 
 
7-2) 
 
 
 
 
 
 
 
7-3) 
 
 
 
7-4) Example design 
 
 
 
 
 
 
7-5) For continuous current 
 
 
 
 
7-6) Switch is closed for DT, current returns to zero at t = tx: 
 
 
 
7-7) 
 
 
 
7-8) 
 
 b) 
The currents in the converter are shown below. The winding currents are for the windings in the ideal 
transformer model, not the physical windings. The physical primary winding current is the sum of 
winding #1 and Lm currents. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
7-9) 
 
 
7-10) 
 
 b) 
The currents in the converter are shown below. The winding currents are for the windings in the ideal 
transformer model, not the physical windings. The physical primary winding current is the sum of 
winding #1 and Lm currents. 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
7-11) 
 
 
 
 
 
 
 
 
 
 
7-12) 
 
 
 
 
 
 
 
 
 
7-13) 
 
 
7-14) 
The current in the physical primary winding is the sum of iL1 and iLm in the model. The physical currents 
in windings 2 and 3 are the same as in the model. 
 
 
 
 
 
 
 
 
 
7-15) 
 
 
 
 
 
7-16) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
7-17) 
 
 
 
 
 
 
 
 
 
 
 
 
7-18) The input voltage vx to the filter is Vs(Ns / Np) when either switch is on, and vx is zero when both 
switches are off. (See Fig. 7-8.) The voltage across Lx is therefore 
 
7-19) 
 
7-20) 
 
 
 
7-21) 
 
 
7-22) 
The simulation is run using a Transient Analysis with a restricted time of 3 to 3.02 ms, representing two 
periods of steady-state operation. The steady-state output voltage has an average value of approximately 
30 V and peak-to-peak ripple of approximately 600 mV, ignoring the negative spike. The average 
transformer primary and secondary currents are 912 mA and 83.5 mA, respectively. The output voltage is 
lower than the predicted value of 36 V because of the nonideal switch and diode, mostly from the switch. 
The output voltage ripple is 2%, matching the predicted value. The converter would operate much better 
with a switch that has a lower on resistance. 
 
 
 
 
 
 
 
 
 
 
 
 
7-23) 
Using a nonideal switch and diode produces lower values for the currents. For iLx, the maximum, 
minimum, and average values in PSpice are 1.446 A, 0.900 A, and 1.17 A, compared to 1.56 A, 1.01 A, 
and 1.28 A, respectively. However, the peak-to-peak variation in iLx in PSpice matches that of the ideal 
circuit (0.55 A). 
 
 
 
 
 
7-24) 
Design for θco= -210° and a gain of 20 dB for a cross over frequency of 12 kHz. 
 
 
7-25) 
 
 
7-26) 
 Using Vs = 6 V as in Example 7-8, the frequency response of the open-loop system shows that the 
crossover frequency is approximately 16.8 kHz. The phase angle at the crossover frequency is 17°, which 
is much less than the desired value of at least 45°. Therefore, the system does not have the desired degree 
of stability. 
 
 
 
 
 
7-27) 
a) A frequency response of the circuit yields Vo ≈ -2.5 dB and θ ≈ 103° at 10 kHz. 
 
 
 
 
 
 
 
 
 
 
b) With Vp = 3, the gain of the PWM function is 20log10(1/3) = -9.54 dB. The required gain of the 
compensated error amplifier is then 2.5 + 9.54 = 12.06 dB, corresponding to a gain magnitude of 4.0. The 
phase angle of the compensated error amplifier at the crossover frequency to give a phase margin of 45° 
is 
 
 
 
From 7-75, 7-85, 7-86, and 7-87, 
 
 
 
c) Referring to Example 7-9, the PSpice simulation results are shown indicating a stable control system. 
The switching frequency was not specified, and 50 kHz was used here. Use initial conditions for the 
capacitor voltage at 8 V and the inductor current at 2 A. 
 
 
 
 
 
 
7-28) 
a) The gain at 8 kHz is approximately -2.44 dB, and the phase angle is -100°. 
 
 
 
 
 
b) This design is for fco = 8 kHz. With Vp = 3, the gain of the PWM function is 20log10(1/3) = -9.54 dB. 
The required gain of the compensated error amplifier is then 2.44 + 9.54 = 11.98 dB, corresponding to a 
gain magnitude of 3.97. The phase angle of the compensated error amplifier at the crossover frequency to 
give a phase margin of 45° is 
 
 
 
From 7-75, 7-85, 7-86, and 7-87, 
 
 
 
c) Referring to Example 7-9, the PSpice simulation results are shown indicating a stable control system. 
The switching frequency was not specified, and 50 kHz was used here. Use initial conditions for the 
capacitor voltage at 8 V and the inductor current at 1.6 A. 
 
 
 
 If designing for fco = 10 kHz, the gain of the converter is -4.38 dB, and θco = -98°. R1 = 1k, R2 = 4.97k, 
C1 = 9.58 nF, and C2 = 1.07 nF. 
 
 
 
7-29) 
 
7-30) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
7-31) 
 
 
 
 
 
CHAPTER 8 SOLUTIONS 
4/24/10 
8-1) 
 
 
 
 
8-2) 
 
c) PSpice results are consistent with parts (a) and (b). The current waveform reaches steady state after 
approximately 100 ms, corresponding to 5 time constants. 
 
 
 
8-3) 
 
 
 
 
 
 
 
 b) 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
8-4) 
 
 
 
8-5) 
 
n Vn Zn In,rms 
1 331 29.3 8.0 
3 110 77 1.02 
5 66 127 0.37 
 
 
8-6) 
 
 
 
n Vn Zn In,rms 
1 88.6 31.3 2.0 
3 29.5 61.8 0.34 
5 17.7 97.5 0.13 
 
 
 
Using PSpice, 
 
 
 
 
 
 
 
 
FOURIER COMPONENTS OF TRANSIENT RESPONSE I(L_L) 
 
 DC COMPONENT = -3.668708E-06 
 
 HARMONIC FREQUENCY FOURIER NORMALIZED PHASE NORMALIZED 
 NO (HZ) COMPONENT COMPONENT (DEG) PHASE (DEG) 
 
 1 1.200E+02 2.830E+00 1.000E+00 -3.716E+01 0.000E+00 
 2 2.400E+02 5.377E-06 1.900E-06 -1.203E+02 -4.594E+01 
 3 3.600E+02 4.778E-01 1.688E-01 -6.658E+01 4.490E+01 
 4 4.800E+02 3.589E-06 1.268E-06 -1.223E+02 2.629E+01 
 5 6.000E+02 1.818E-01 6.422E-02 -7.587E+01 1.099E+02 
 6 7.200E+02 2.858E-06 1.010E-06 -1.162E+02 1.068E+02 
 7 8.400E+02 9.427E-02 3.331E-02 -8.028E+01 1.798E+02 
 8 9.600E+02 2.523E-06 8.913E-07 -1.095E+02 1.878E+02 
 9 1.080E+03 5.743E-02 2.029E-02 -8.292E+01 2.515E+02TOTAL HARMONIC DISTORTION = 1.847695E+01 PERCENT 
 
 
8-7) 
Using a restricted time interval of 33.33 ms to 50 ms to analyze steady-state current, the peak value is 
8.26 A and the rms value is 4.77 A. The THD from the output file is 32%. 
 
 
 
 
8-8) 
 
n |Vn| Zn In,rms 
1 90 12.5 5.08 
3 51.6 24.7 1.5 
5 4.43 39 0.08 
 
 
 
 
8-9) 
 
 
 
 
 
 
8-10) 
 α = 30° 
Using the FFT function in Probe shows that voltages at frequencies at multiples of n = 3 are absent. 
 
 
 
 b) α = 15° 
Using the FFT function in Probe shows that voltages at frequencies at multiples of n = 5 are absent. 
 
 
 
 
 
 
 
 
 
 
 
8-11) 
 From Eq. (8-22), 
 
 
 Using the FFT function in Probe, the n = 7 harmonic is absent. 
 
 
 
 
8-12) 
 Letting T = 360 seconds and taking advantage of half-wave symmetry, 
 
 
 
 
8-13) 
The VPWL_FILE source is convenient for this simulation. A period of 360 seconds is used, making each 
second equal to one degree. A transient simulation with a run time of 360 second and a maximum step 
size of 1m gives good results. The FFT of the Probe output confirms that the 3rd and 5th harmonics and 
their multiples are eliminated. 
 
 
0 0 
30 0 
30.01 1 
54 1 
54.01 0 
66 0 
66.01 1 
114 1 
114.01 0 
126 0 
126.01 1 
150 1 
150.01 0 
210 0 
210.01 -1 
234 -1 
234.01 0 
246 0 
246.01 -1 
294 -1 
294.01 0 
306 0 
306.01 -1 
330 -1 
330 0 
360 0 
 
 
 
 
 
 
8-14) 
a) 
 
 
 
 
n 1 3 5 7 9 
Vn 149.5 0 -2.79 -3.04 -14.4 
 
 
 
 
8-15) 
 
α1 α2 α3 Mi 
15 25 55 0.815 
20 30 40 0.857 
10 30 50 0.831 
10 30 70 0.731 
 
 
8-16) 
This inverter is designed to eliminate harmonics n = 5, 7, 11, and 13. The normalized coefficients through 
n = 17 are 
 
n Vn/Vdc 
1 4.4593 
3 -0.8137 
5 0.0057 ≈ 0 
7 -0.0077 ≈ 0 
9 -0.3810 
11 0.0043 ≈ 0 
13 -0.0078 ≈ 0 
15 -0.0370 
17 0.1725 
The coefficients are not exactly zero for those harmonics because of rounding of the angle values. 
 
 
 
 
 
 
 
8-17) 
 
 
 
 
8-18) 
 
 
From Table 8-3, 
 n Vn/Vdc Vn Zn In=Vn/Zn 
 1 0.8 76.8 33.3 2.30 
mf 17 0.82 78.7 157 0.50 
mf - 2 15 0.22 21.1 139 0.151 
mf + 2 19 0.22 21.1 175 0.121 
 
 
 
 
 
8-19) 
 
 
From Table 8-3, 
 n Vn/Vdc Vn Zn In=Vn/Zn 
 1 0.9 225 27.5 8.18 
mf 31 0.71 178 585 0.305 
mf - 2 29 0.27 67 547 0.122 
mf + 2 33 0.27 67 622 0.108 
 
 
 
 
 
 
 
8-20) 
The circuit “Inverter Bipolar PWM Function” is suitable to verify the design results. The parameters are 
modified to match the problem values. 
 
 
Transient Analysis and Fourier Analysis are establish in the Simulation Setup menu: 
 
 
 
 
The output file contains the THD of the load current, verifying that the THD is less than 10%. 
 
TOTAL HARMONIC DISTORTION = 9.387011E+00 PERCENT 
 
8-21) 
Example solution: 
 
 
 
8-22) 
Example solution: 
 
 
 
8-23) 
Use the bipolar PWM function circuit of Fig. 8-23a, and use the unipolar PWM function circuit of Fig.8-
26 with mf = 10. Use ma = 0.8 for V1 = 120 V from the 150-V dc source. 
 
 
 
 
The THD for bipolar, mf = 21, is 10.2 %, for bipolar mf = 41 is 5.2%, and for unipolar mf = 10 is 5.9%. 
 
 
 
 
 
 
 
 
 
 
 
 
Bipolar mf = 21: 
 
 
Bipolar mf = 41: 
 
 
 
 
 
Unipolar, mf = 10: 
 
 
 
 
8-24) 
 
 
 
 
 
 
 
 
8-25) 
 
 
 For f = 25 Hz: 
n VnL-N Zn In In,rms 
1 255 11.1 23.0 16.3 
5 50.9 25.6 2.0 1.41 
7 36.4 34.5 1.06 0.75 
11 23.1 52.8 0.44 0.31 
13 19.6 62.0 0.32 0.22 
 
 
 
 
 
 
 For f = 100 Hz, 
n VnL-N Zn In In,rms 
1 255 21.3 11.9 8.43 
5 50.9 94.8 0.54 0.38 
7 36.4 132 0.27 0.19 
11 23.1 208 0.12 0.08 
13 19.6 245 0.08 0.06 
 
 
 
 
 
The THD for current is reduced from 10% to 5.19% as f is increased from 25 Hz to 100 Hz. The THD of 
the line-to-neutral voltage remains at 27.3%. 
 
These results can also be determined from a PSpice simulation for the six-step inverter. 
 
 
8-26) 
 
 
 
 
 
 
CHAPTER 9 SOLUTIONS 
3/13/10 
9-1) 
 
9-2) 
 
9-3) 
 
 
 
 
 
 
 
 
 
 
 
 
 
9-4) 
 
 
9-5) 
 
9-6) 
 
 
9-7) a) The circuit is shown with diode D2 added to make the switch unidirectional. 
 
 
 
(a) The average output (capacitor) voltage is 5.16 V, agreeing with the 5.17 V computed 
analytically. (b) Peak capacitor voltage= 20 V.; (c) Inductor currents: peak = 10.5 A.; average = 
2.59 A.; rms = 4.54 A. 
9-8) 
 
9-9) 
 
 
 
 
 
 
9-10) 
 
9-11) 
 
9-12) 
 
9-13) 
 
 
9-14) A suitable circuit is shown. The values of the output filter components L1 and C2 are not 
critical. The load resistor is chosen to give 10 A. The switch must be open for an interval 
between t2 and t3; 50 ns is chosen. 
 
 
Results from Probe for steady-state output: a) Vo ≈ 14.6 V., b) VC,peak= 120 V., c) Integrate 
instantaneous power, giving 72.7 μJ per period (supplied). 
9-15) 
 
9-16) 
 
 
 
The output file shows that the THD is 10.7%. Increase Q by increasing L, and adjust C 
accordingly. L=1.4 mH and C=12.6 µF gives THD=9.8%. Switching takes place when load 
(and switch) current is approximately 3.6 A. 
 
 
 
 
 
 
9-17) 
 
 
 
From the output file, THD = 10.8%. From Probe: VC,peak=149 V.; IL,peak=8.12 A. 
9-18) 
 
 
 
9-19) 
 
9-20) 
 
A PSpice simulation using the circuit of Fig. 9-6(a) gives an output voltage of approximately 5.1 
V. 
 
 
 
 
 
9-21) 
 
 
9-22) 
 
 
 
A PSpice simulation using the circuit of Fig. 9-6a shows a steady-state output voltage of 
approximately 14.4 V, slightly less than the target value of 15 V. Note that the current in Lr and 
Cr is not quite sinusoidal. 
 
 
9-23) 
 
A PSpice simulation using the circuit of Fig. 9-6a shows a steady-state output voltage of 
approximately 53 V, slightly less than the target value of 55 V. Note that the current in Lr and Cr 
is not quite sinusoidal. 
 
9-24) 
 
9-25) 
 
9-26) 
 
 
9-27) 
 
 
9-28) 
 
 
9-29) 
 
 
9-30) 
 
9-31) 
 
9-32) 
 
Using a circuit based on Fig. 9-11a but with a square-wave source implemented with Vpulse (see 
Fig. 9-6a), the result is approximately 9.4 V. 
 
 
9-33) 
 (a) A PSpice simulation using the circuit shown reveals that the capacitor voltage returns to zero 
at 15.32 μs and the switch must remain closed for 5.58 μs for the inductor current to return to 12 
A. Initial conditions for the inductor (12 A) and for the capacitor (0 V) must be applied. Ideal 
models for the switch and diode are used. 
b) Using the expression S(W(V1)) for energy (S is integration), 15.7 mJ are supplied by the 
voltage source in one period. 
c) Average power is 754 W, obtained by entering AVG(W(V1)). 
d) Average resistor power is 104 W. 
e) With R = 0, the capacitor voltage returnsto zero at 15.44 μs and the switch must remain 
closed for 5.45 μs. The source power and energy are not changed significantly. 
 
 
 
 
9-34) 
 
9-35) 
 
 
 
 
CHAPTER 10 SOLUTIONS 
3/20/10 
10-1) 
 a) For the elementary MOSFET drive circuit, losses can be determined from the energy 
absorbed by the transistor. In Probe, the integral of instantaneous power is obtained by entering 
the expression S(W(M1)) to get the energy absorbed by the transistor. For turn-off losses, 
restrict the data to 2.5 µs to 4.3 µs. The energy absorbed is 132 µJ. For turn-on losses, restrict 
the data to 5 µs to 5.6 µs. The energy absorbed by the MOSFET is 53.3 µJ. Power is 
determined as 
 
For the emitter-follower drive circuit restrict the data to 2.5 µs to 2.9 µs, giving 21.3 µJ for turn-
off. Restrict the data to 5 µs to 5.3 µs, giving 12.8 µJ for turn-on. Power is then 
 
b) For the first circuit, peak gate current is 127 mA, average gate current is zero, and rms gate 
current is 48.5 mA. For the second circuit, peak gate current is 402 mA (and -837 mA), average 
gate current is zero, and rms gate current is 109 mA. 
10-2) 
For R1 = 75 Ω, toff ≈ 1.2 μs, ton ≈ 0.6 μs, and PMOS ≈ 30 W. 
For R1 = 50 Ω, toff ≈ 0.88 μs, ton ≈ 0.42 μs, and PMOS ≈ 22 W. 
For R1 = 25 Ω, toff ≈ 0.54 μs, ton ≈ 0.24 μs, and PMOS ≈ 14 W. 
 
Reducing drive circuit resistance significantly reduces the switching time and power loss for the 
MOSFET. 
 
10-3) 
The values of Vi, R1, R2, and C must be selected for the BJT base drive circuit. First, select Vi: 
let Vi=20 V. then, the value of R1 is determined from the initial current spike requirement. 
Solving for R1 in Eq. 10-1, 
 
The steady-state base current in the on state determines R2. From Eq. 10-2, 
 
The value of C is determined from the required time constant. For a 50% duty ratio at 100 kHz, 
the transistor is on for 5 µs. Letting the on time for the transistor be five time constants, τ = 1µs. 
From Eq. 10-3, 
 
10-4) 
The values of Vi, R1, R2, and C must be selected for the BJT base drive circuit. First, select Vi; 
let Vi = 20 V. then, the value of R1 is determined from the initial current spike requirement. 
Solving for R1 in Eq. 10-1, 
 
The steady-state base current in the on state determines R2. From Eq. 10-2, 
 
The value of C is determined from the required time constant. For a 50% duty ratio at 120 kHz, 
the transistor is on for 4.17 µs. Letting the on time for the transistor be five time constants, 
τ = 1 µs. From Eq. 10-3, 
 
10-5) 
a) From Eq. 10-5 through 10-7 for t < tf, 
 
For tf < t < tx, 
 
Time tx is defined as when the capacitor voltage reaches Vs (50 V.): 
 
b) With tx > tf, the waveforms are like those in Fig. 10.12(d). 
c) Turn-off loss is the switch is determined from Eq. 10-12, 
 
Snubber loss is determined by the amount of stored energy in the capacitor that will be 
transferred to the snubber resistor: 
 
10-6) 
Switch current is expressed as 
 
Capacitor voltage at t = tf = 0.5 µs would be 100 volts, which is greater than Vs. Therefore, the 
above equations are valid only until vC reaches Vs: 
 
For tx < t < tf, 
 
 
b) With tx < tf, the waveforms are like those of Fig. 10.12(b). 
Equation 10-12 is not valid here because tx < tf. Switch power is determined from 
 
Snubber loss is determined by the amount of stored energy in the capacitor that will be 
transferred to the snubber resistor: 
 
10-7) 
 
10-8) 
 
10-9) 
 
 
 
10-10) 
 
10-11) 
Using the snubber circuit of Fig. 10-12(a), Eq. 10-12 yields 
 
10-12) 
Using the snubber circuit of Fig. 10-12(a), Eq. 10-12 yields 
 
 
 
 
 
 
 
10-13) 
 
10-14) 
 
10-15) 
 
10-16) 
 
10-17) 
 
 
10-18) 
 
 
 
10-19)