1_5014833385659433139

Prévia do material em texto

This is the PVT design
Schematic / PCB #'s
SCHEM,MLB_BAFFIN,X363G
1 OF 121
LAST_MODIFICATION=Wed Aug 24 09:57:44 2016
22
LPDDR3 DRAM Channel B (32-63)
11/06/2015
X362_MLB
Project Specific Constraints
Memory Bit/Byte Swizzle
11/06/2015
03/30/2016
J80_MLB
11/06/2015
04/29/2016
04/25/2016
03/15/2016
08/26/2015
WIFI/BT: MODULE 2
POLARIS GND
SMC Shared Support
37
12/04/2015
03/29/2016
04/29/2016
42
PCH PCI-E/USB
8
J80_DTUZMAN_MLB_BAFFIN
Power FETs
2
J80_MLB
16 PCH Power
J80_DTUZMAN_MLB_BAFFIN
12/08/2015
01/25/2016
11/06/2015
12/08/2015
12/09/2015
09/03/2015
11/18/2015
09/03/2015
12/10/2015
11/06/2015
11/06/2015
J80_DTUZMAN_MLB_BAFFIN
J80_DTUZMAN_MLB_BAFFIN
X363_ZIFENGSHEN
J80_MLB
J80_MLB
J80_MLB
X363_AUDIO
J80_MLB
J80_MLB
J80_SILUCHEN_MLB_BAFFIN
J80_DTUZMAN_MLB_BAFFIN
J80_DTUZMAN_MLB_BAFFIN
DC-In & Battery Connectors
PBUS Supply & Battery Charger
PMIC-1 Aliases & TPs
PMIC-1 & Power Control
CORE IMVP POWER BLOCK
AUDIO Speaker Amps & Conn
GT & GTX IMVP POWER BLOCK
PMIC-1 1V 1.8V VCCPCH
SA IMVP IC
AUDIO JACK CONNECTOR62
64
65
66 72
63
65
69
70
71
61
68
69
71
73
72
79
7367
76
81
80
78
74
02/01/2016
11/06/2015
11/06/2015
11/06/2015
01/21/2016
08/17/2015
04/14/2016
11/16/2015
11/22/2015
08/16/2015
07/07/2015
12/02/2015
08/09/2016
08/09/2016
08/09/2016
04/15/2016
11/06/2015
12/11/2015
05/18/2016
04/01/2016
12/03/2015
04/01/2016
04/01/2016
04/01/2016
01/20/2016
12/08/2015
08/22/2015
12/08/2015
01/27/2016
02/01/2016
01/28/2016
01/27/2016
01/27/2016
04/29/2015
04/29/2015
04/29/2015
05/18/2016
X363_JSAMUELS
J80_ZIFENGSHEN_MLB_BAFFIN
X363_JSAMUELS
X363_JSAMUELS
X363_JSAMUELS
J80_MLB
X363_JSAMUELS
X363_JSAMUELS
X363_JSAMUELS
X363_ZIFENGSHEN
J80_SAKKOC_MLB_BAFFIN
X363_SEAN
X363_SEAN
J80_DTUZMAN_MLB_BAFFIN
J80_SEAN
Constraints
dpmux
X363_SEAN
X363_SEAN
J80_DTUZMAN_MLB_BAFFIN
J80_SEAN
X363_SEAN
X363_BBABADI
X363_SEAN
J80_SEAN
11/06/2015
11/06/2015
11/06/2015
12/07/2015
11/06/2015
03/30/2016
03/29/2016
12/04/2015
08/16/2015
01/14/2016
01/13/2016
11/06/2015
04/14/2016
12/10/2015
01/26/2016
04/15/2016
05/18/2016
06/02/2016
07/23/2015
07/23/2015
X363_ZIFENGSHEN
J80_MLB
J80_MLB
J80_BBABADI_MLB_BAFFIN
X362_MLB
J80_MLB
J80_MLB
X363_SAKKOC
J80_MLB
X363_SAKKOC
J80_AGOTETI_MLB_BAFFIN
J80_MLB
X362_MLB
J80_ZIFENGSHEN_MLB_BAFFIN
X363_SAKKOC
X363_BBABADI
X363_ZIFENGSHEN
DESENSE
J80_MLB
J80_MLB
Baffin 1V05 GPU / 1V35 FB Power Supply
NAND 1/2
LCD Backlight Driver
POLARIS_CONTROLLER
eDP Display Connector
SSD NAND VR
SSD SUPPORT
POLARIS PMIC
NAND 2/2
TEMP SENSORS
Connector
Lifeboat
GDDR5 Frame Buffer B
Baffin FRAME BUFFER I/F
BAFFIN PCI-E
Baffin DP/GPIO
GDDR5 Frame Buffer A
GPU PCC
Constraints
Baffin VSS & MISC
Baffin GPIOs,CLK & Straps
eDP Mux
77
79
75
76
78
74 82
86
88
85
84
80 89
84
95
83
90
91
92
81
82
94
93
86
85
11/06/2015
11/06/2015
11/06/2015
01/25/2016
11/06/2015
01/14/2016
04/29/2016
11/06/2015
04/14/2016
968711/06/2015
90
97
93
88
89
92
102
98
101
100
99
94
95 104
106
109
98
108
107
105
103
100
99
97
96
03/22/2016
01/27/2016
08/08/2016
08/08/2016
USB-C Support
USB-C PORT CONTROLLER A
Signal Aliases
Power Aliases - 1
ICT & FCT 2
ICT & FCT 1
Power Aliases - 2
TBT 5V REGULATOR
USB-C CONNECTOR B
USB-C CONNECTOR A
USB-C HIGH SPEED 1
USB-C HIGH SPEED 2
USB-C PORT CONTROLLER B
NC & No Test
639 BOM Configuration 2
Desense Caps
Desense Caps
101
102
103
104
105
106
107 116
115
114
113
112
111
110
108
109
110
112
120
121
122
123
125
111
124
117
114
113
04/14/2016
04/14/2016
04/14/2016
01/08/2016
04/14/2016
11/19/2015
04/14/2016
04/14/2016
04/14/2016
04/14/2016
01/08/2016
06/30/2016
115
116
142
141
130
128
127
126
120
119
118
117
01/25/2016
01/25/2016
01/11/2016
11/06/2015
04/14/2016
05/19/2016
J80_ZIFENGSHEN_MLB_BAFFIN
J80_ZIFENGSHEN_MLB_BAFFIN
J80_MLB
J80_MLB
X363_AGOTETI
J80_MLB
J80_MLB
J80_MLB
J80_MLB
J80_MLB_BAFFIN_CLEAN
X363_SEAN
J80_MLB
PCH RTC/HDA/JTAG/SATA/CLK
CPU Decoupling 2 [11]
CPU DMI/PEG/FDI/RSVD
CPU Clock/Misc/JTAG/CFG
CPU Ground
CPU Power
PD Parts
BOM Configuration
BOM Configuration
PCH DMI/FDI/PM/GFX/PCI
MLB_BAFFIN
12
13
11
1
3
4
5
6 6
5
4
3
2
1
13
10
7
9
11
9
7
12
X363_SAKKOC
X363_SAKKOC
J80_MLB
J80_MLB
X363_SAKKOC
X363_SAKKOC
J80_MLB
X363_SAKKOC
J80_MLB
X363_SAKKOC
J80_MLB
J80_MLB
J80_MLB
J80_MLB
X363_SAKKOC
J80_MLB
X363_SAKKOC
X362_T208
X362_T208
X362_MLB
X363_AGOTETI
X362_GKOO
X362_T208
LPDDR3 DRAM Channel A (0-31)
LPDDR3 DRAM Channel A (32-63)
PCH GPIO/MISC/NCTF
PCH DECOUPLING
Chipset Support 2
LPDDR3 VREF MARGINING
CPU/PCH Merged XDP
USB-C HIGH SPEED 1
Berkelium - 1
Camera/DFR 3
Camera/DFR 2
Camera/DFR 1
WIFI/BT: MODULE 1
USB-C CONNECTOR A
USB-C PORT CONTROLLER A
USB-C CONNECTOR B
TBT 5V REGULATOR
USB-C PORT CONTROLLER B
X363_ZIFENGSHEN
J80_MLB
X363_SAMANTHA
X362_T208
X362_T208
X362_P49
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_AUDIO
J80_MLB
X363_ZIFENGSHEN
X363_ZIFENGSHEN
X363_AUDIO
X363_AUDIO
Power Sensors: Load Side
Power Sensors: Extended 2
Power Sensors: High Side
External A USB3 Connector
AUDIO Speaker Amps & Conn
Connectors&ESD
Berkelium - 2
SMBus Connections
SMC Project Support
T208 Support
Power Sensors: Extended
Thermal Sensors
SMC
MESA
AUDIO JACK CODEC
Sensor Extended 3
SPI Debug Connector
HDA Bridge
Fans
53
63
33
17
14
15
19
20
22
23
24
25
26
27
28
30
32
34
35
38
39
40
41
43
44
45
47
49
50
51
52
54
55
56
57
58
59
60
61
62
64
31
18
24
25
14
15
16
17
18
19
21
20
26
23
27
31
32
33
34
35
36
37
39
40
38
30
29
41
42
43
44
45
46
47
48
49
50
51
52
54
53
55
56
57
58
60
59
7010
639 BOM Configuration
PMIC-1 1.2V 0.6V VCCIO
CORE & SA IMVP IC
66
11/06/2015
11/06/2015
11/06/2015
X363_JSAMUELS
POLARIS POWER
Power - 5V 3.3V Supply
04/14/2016
Baffin CORE/FB POWER
91
USB-C HIGH SPEED 22928
Chipset Support 1
LPDDR3 DRAM Termination
LPDDR3 DRAM Channel B (0-31)
8
12/03/2015J80_DTUZMAN_MLB_BAFFIN
01/25/2016
04/29/2016
X363_SAKKOC
CPU DDR3 Interfaces
CPU Decoupling 1 [10]
87
01/27/2016
GFX IMVP VCore Regulator [106]
USB-C Support
SCHEM,MLB-BAFFIN,X363
051-00647
2016-08-24000689728910 ENGINEERING RELEASED
1 OF 145
dvt-fab10
10.0.0LAST_MODIFIED=Wed Aug 24 09:57:44 2016
CRITICALSCHSCHEM,MLB-BAFFIN,X363G051-00647 1
ABBREV=ABBREV
TITLE=MLB_BAFFIN
CRITICALPCBPCBF,MLB-BAFFIN,X363G820-00281 1
PROPRIETARY PROPERTY OF APPLE INC.
REVISION
ECNREV DESCRIPTION OF REVISION
DRAWING TITLE
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CK
APPD
2 1
1245678
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
R
SHEET
D
SIZEDRAWING NUMBER
BRANCH
7
B
3
 II NOT TO REPRODUCE OR COPY IT
 IV ALL RIGHTS RESERVED
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
NOTICE OF PROPRIETARY PROPERTY:
Apple Inc.
DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
DRAWING
X363 BOM Groups
Strategic Silicon
Sub-BOM DIPLEXER
Main DRAM Parts
Main DRAM SPD Straps
BOM Variants
GPU Options
Development/Base BOMs
FB VDRAM Parts
WIFI/BT Diplexers
Module Parts
639 BOMs have been moved to the end of the schematic
2 OF 121
2 OF 145
10.0.0
051-00647
dvt-fab10
CRITICAL
333S00050
338S00138
343S00137
343S00136
343S00135
T20810
DEBUG MUX09353S00795
359S00006 GREEN CLOCK08
ICEBOCK05339S00056
TUBA09353S00853
BANJO08338S00221
08353S4316 BAYSIDE
338S00142 CLIFDEN09
AUDIO AMP07353S00604
353S00961 09 ACE
ALPINE RIDGE08338S00254
02 SECURE ELEMENT338S00097
353S3978 02 MOJAVE
09338S00193 BERKELIUM
07
VIDEO MEMORY333S00078
333S00075
10
337S00229
MAIN MEMORY
CPU,SKY,SR2FT,R1,PRQ,4/2,2.9,BGA1440IC,SKL PCH-H,SFF,SR2NH,PRQ,D1,BGA939
338S00142
X363_COMMON4
998-04701
335S00149
SSD CONTROLLER
CRITICAL CPU_SKL:2.6
CPU_SKL:SOCKET
X363_PROGPARTS
337S00229
X363_DEVEL:PVT
U0500
U1100
1
985-00126
BOM Configuration
SYNC_DATE=07/07/2015SYNC_MASTER=J80_MLB
685-00076 COMMON PARTS,MLB-BAFFIN,X363 X363_COMMON
08 CPU
X363_COMMON3
CPU,SKY,SR2FQ,R1,PRQ,4/2,2.6,BGA14401 U0500
337S00227 U05001 CRITICAL CPU_SKL:2.9
X363_COMMON1
1 CRITICAL337S00258
ENGISNS
08337S00228 CPU
SSD NAND02
T20810
07
1 BASE685-00076 COMMON PARTS,MLB-BAF,X363 BASE_BOMCRITICAL
16G_SAMSUNG_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG0:LRAM_16G_SAMSUNG_2133
16G_MICRON_2133,RAMCFG4:L,RAMCFG3:L,RAMCFG1:LRAM_16G_MICRON_2133
16G_MICRON_21334 U2300,U2400,U2500,U2600 CRITICALIC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178333S00070
CRITICALU2300,U2400,U2500,U26004 16G_SAMSUNG_2133IC,SDRAM,LPDDR3-2133,32GBIT,20NM,BGA178333S00050
FB_4GB_MICRON,VRAM:GRP14GB_MC_BAFFIN
08337S00227 CPU
CRITICAL1 U7800IC,PMU,P650839,7X7MM.BGA168338S00221
02 SSD PMIC338S00166
08 GPU337S00225
T208
FB_2GB_HYNIXUA400,UA450,UA500,UA550IC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA4 CRITICAL333S00043
2GB_MC_BAFFIN FB_2GB_MICRON,VRAM:GRP1
INTERPOSER,INTEL,BGA1440,MM9409891 CRITICAL
2GB_SM_BAFFIN FB_2GB_SAMSUNG,VRAM:GRP2
685-00085 DIPLEXERS,MURATA,X363G DIPLEXER:MURATA
2GB_HY_BAFFIN FB_2GB_HYNIX,VRAM:GRP1
333S00075 FB_4GB_MICRONUA400,UA450,UA500,UA5504 CRITICALIC,GDDR5,8Gb,7Gbps,1.5V,25NM,A,170 BGA
333S00074 FB_4GB_SAMSUNG4 CRITICALUA400,UA450,UA500,UA550IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA
333S00078 IC,GDDR5,8Gb,7Gbps,1.5V,25NM,B,170 BGA4 UA400,UA450,UA500,UA550 FB_2GB_SAMSUNGCRITICAL
FB_2GB_MICRONIC,GDDR5,4Gb,7Gbps,1.5V,25NM,A,170 BGA UA400,UA450,UA500,UA5504 CRITICAL333S00044
335S00205 02 SSD NAND
SSD NAND335S00204 02
DEVEL_BOM1 CRITICALDEVELDEV,MLB-BAF,X363
T20810
4GB_SM_BAFFIN FB_4GB_SAMSUNG,VRAM:GRP1
CPU_SKL:2.7337S00228 U0500CPU,SKY,SR2FU,R1,PRQ,4/2,2.7,BGA1440 CRITICAL
U63001 IC,CODEC,CLIFDEN,CS42L83A,B0,WLCSP49
1 UA000998-04867 INTERPOSER,AMD,C988,BGA769,VDDC CRITICAL STARDUST:VDDC
SSD NAND335S00219 02
SSD CONTROLLER339S00154 02
339S00155 02
08 GPU337S00285
08 GPU337S00286
07 VIDEO MEMORY333S00044
07 VIDEO MEMORY333S00043
07
VIDEO MEMORY333S00074
07 VIDEO MEMORY
CRITICAL3155S0979 U3810,U3820,U3830 DIPLEXER:MURATAFLTR,DIPLEXER,2.45/5.54GHZ,0805
IC,ISL9239HIZ,PMU,TUBA,WCSP40,2.1X3.3MM1 U7000 CRITICAL353S01016
333S00070 07 MAIN MEMORYU2800,UB000IC,TBT,ALPINE RIDGE DP,QT5S,QS,C1,BGA337338S00254 CRITICAL2
4 IC,CD3215,ACE,C0,USB PWR SW,BLNK,BGA96 U3100,U3200,UB300,UB400 CRITICAL353S00961
1 BAFFIN_ULA337S00330 IC,GPU,BAFFIN,ULA,A1,PS,BGA769
1 BAFFIN_LEA337S00332 CRITICALUA000IC,GPU,BAFFIN,LEA,A1,PS,BGA769
1 BAFFIN_PROACRITICAL337S00331
998-04866 STARDUST:VDDCI_MVDDUA0001 CRITICALINTERPOSER,AMD,C989,BGA769,VDDCI/MVDD
SUBASSY (T&R) PCBA, AMR, INTERPOSER, X3632677-04532 CRITICALJ5250,J5260
X363_COMMON2
UA000IC,GPU,BAFFIN,PROA,A1,PS,BGA769
X363_DEVEL:DVT
X363_DEVEL:ENG
ALTERNATE,COMMON,X363_COMMON1,X363_COMMON2,X363_COMMON3,X363_COMMON4,X363_PROGPARTS
EDP:YES,CPUPEG:X8X4X4,TBTTHRM_SNS,GPUTHRM_SNS,S3_STATE:YES,GPU_ROM:YES,SVID_PU:CORE
ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG,GPUROM:BLANK,PCC:YES
BOOTROM_PROG:DVT,BT_PROG:DVT,WIFI_PROG:DVT,UPCROM_PROG:DVT,SMC_PROG:PVT,DPMUXMCU:PROG,PCC:NO
CPUTHRM:ALRT,TBTTHRM:ALRT,LOADRC:NO,OTHERRC:YES,DDRRC:YES,TBTRC:YES,TPADRC:YES,LID_FEATURE_ON
ALTERNATE,ENGISNS,DBGLED,XDP_CONN,USBC_DBG,DBG_BTN,DBG_FAN,DBG_XTAL,DPMUX_DEBUG,WIFI_DBG,SSD_DEBUG
TBTISNS,LOADISNS,TPADISNS,DDRISNS,OTHERISNS
ALTERNATE,XDP_CONN,USBC_DBG
CRITICALUA000
X363_DEVEL:PVT
985-00232 X363_DEVEL:PVTDEV,MLB-BAFFIN,PVT,X363
985-00126
DEV,MLB-BAFFIN,X363
X363_COMMON
XDP:YES,SAMCONN,SOC_BOOT:SPI,DPMUX_XTAL:NO,GPUCLK:OSC,BAFFIN,AP_TEMP,VCCPLLOC:S3,WIFI_SAK:NO
SOC:HYNIX,SE:PROD,SKIP_5V3V3:AUDIBLE,DIPLEXER:MURATA,T208_PROG:REV5,BOARD_ID:17,VCCHDA:S0
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
STRATEGIC VALUE
TABLE_STRATEGIC_HEAD
PART# COMMENT
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_BOMGROUP_ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_BOMGROUP_ITEM
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
TABLE_STRATEGIC__ITEM
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
Macronix/Winbond
Winbond
Blank
Winbond
Blank
Blank
TI
Blank
Blank
Macronix/Winbond
Rohm/On Semi
Programmable Parts
3 OF 121
3 OF 145
10.0.0
051-00647
dvt-fab10
CRITICAL
CRITICAL GPUROM:BLANK
DPMUXMCU:PROG
WIFI ROM (P107) DVT,NEW,WW1,X362/X363
IC,BT ROM (V28), DVT, X362/X363
335S00024
341S00708
341S00707
353S00926 IC,CD3215,ACE,B03,BLNK,BGA96
T29,AR1 (V10.5) PVT, X363G
T29,AR2 (V10.5) PVT, X363G
IC,1Mbit SERIAL FLASH 2X3X0.6MM UFDFPN8 PKG
IC, EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2
1
2
UB090
341S00699
335S00013
341S00701
UPCROM_PROG:DVT
U3750
IC,SPI SERIAL FLASH,64M BITS,3V,8P SOIC,QE=1
IC,SMC-B1,EXT (v2.37F7) PVT,X363G
U6100
IC,SERIAL-FLASH,2MBIT,4V,8-USON,2x3x,6MM
1
IC,EFI ROM (V0193), DVT, X363G
IC,SMC12,40MHZ/50DMIPS MCU,7X7,168BGA
U2890,UB090
U2890
CRITICAL
CRITICAL
CRITICAL
CRITICAL
341S00709
341S3565
1
CRITICAL
CRITICAL
CRITICAL
U5000
U6100
UPCROM_PROG:BLANK
CRITICAL SMC_PROG:BLANK
BOOTROM_PROG:DVT
BOOTROM_PROG:BLANKCRITICAL
WIFI_PROG:DVT
BT_PROG:BLANK
1341S00695
U3710
1
1
1 U9800
1
1
1
SYNC_MASTER=J80_MLB_BAFFIN_CLEAN SYNC_DATE=12/02/2015
BOM Configuration
U3750
335S0724 1 UA701
338S1231
CRITICAL
UPCROM_PROG:DVT
SMC_PROG:PVT
U5000
BT_PROG:DVT
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
SSD - TOP side
APN 806-06584APN 806-07814
T208 - TOP side
SSD - BOT side
APN 806-06585
Frame Buffer Memory - BOT side - Right
Shield Can Omit Table
T208 - TOP side - North
SSD - TOP side - North
APN 806-08026
VRAM - BOT side
BOT side - Right
Diplexer - BOT side
Frame Buffer Memory - BOT side - Left
APN 806-07958
TOP side - Left
eDP
BOT side - North
Pogo Pins
Keyboard
BOT side - Left
BOT side - South
BOT side
AR Right - BOT side
APN 806-06586
APN 806-06588
Shield Can Fence
TBT Left - BOT side - North
System Memory - BOT side - Left
TBT Left - BOT side - South
APN 998-2691
USB-C Right
DFR Display
BOT side - Right
BOT side - South
Lifeboat
BOT side - Left
Keyboard
T208 - TOP side - South
SSD - BOT side - North
Trackpad
Lifeboat
eDP
Trackpad
TBT Right - BOT side - South
TBT Right - BOT side - North
APN 806-06591
APN 860-00469
USB-C Left
SMT Bosses Rubber Mount
APN 860-00500
BOT side - South
APN 870-01772
APN 870-01771
APN 860-00500
APN 806-06520
DFR Touch - TOP side
System Memory - BOT side - Right
Standoffs
BOT side - Right
APN 860-00452
SSD - BOT side - South
AR Left - BOT side
Shield Can TH
APN 806-06590
DRAM - BOT side
SSD - TOP side - South
T208 through holes are non-plated... for now
APN 860-00435
DFR Display
APN 860-00413
BOT side - Left
APN 806-06521
DFR Touch
APN 806-06600
BOT side - North
USB-C Right
BOT side - North
USB-C Left
APN 860-00392
USB-C Right
BOT side - Left
TOP side - Right
4 OF 121
4 OF 145
10.0.0
051-00647
dvt-fab10
SYNC_DATE=11/16/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=MECHANICALS
PD Parts
806-08023 1 SH0400 CRITICALSHIELD,FENCE,DRAM,X378
SHIELD,FENCE,ALPINE RIDGE,LEFT,X3781 CRITICALSH0420806-08021
SHIELD,FENCE,ALPINE RIDGE,RIGHT,X3781 CRITICALSH0410806-08019
806-08024 CRITICALSH04601 SHIELD,DIPLEX,EG,X378
SH0440 CRITICAL1 SHIELD,NAND,TOP,ALT,X363806-07918
1 SH0450 CRITICAL806-07917 SHIELD,NAND,BOTTOM,ALT,X363
SH0470 CRITICAL1806-08026 FENCE,VRAM,EG,X378
SM
SHLD-FENCE-MLB-M8-X379
OMIT_TABLE
SH0400
1
SHLD-FENCE-M8-X379
SM
SH0430
1
3.09OD1.4ID-3.25H-SM
BM0400
1
2
3.4OD1.75ID-2.12H-SM
BS0480
1
3.4OD1.75ID-1.57H-SM
BS0461
1
SL-1.1X0.4-1.4X0.7
TH-NSP
TH0400
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0401
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0410
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0411
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0420
1
SL-1.1X0.4-1.4X0.7
TH-NSP
TH0421
1
SL-1.1X0.4-1.4X0.7
TH-NSP
TH0440
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0441
1
SL-1.1X0.4-1.4X0.7
TH-NSP
TH0450
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0451
1
3.4OD1.75ID-1.12H-SM
BS0400
1
3.4OD1.75ID-1.12H-SM
BS0401
1
3.4OD1.75ID-1.12H-SM
BS0410
1
3.4OD1.75ID-1.12H-SM
BS0411
1
POGO-2.3OD-4.63H-SM
SM
PG0411
1
POGO-2.3OD-4.63H-SM
SM
PG0421
1
POGO-2.3OD-4.63H-SM
SM
PG0410
1
SM
POGO-2.3OD-4.63H-SM
PG0430
1
SM
POGO-2.3OD-4.63H-SM
PG0420
1
3.4OD1.75ID-1.45H-SM
BS0420
1
3.4OD1.75ID-1.9H-SM
BS0430
1
3.4OD1.75ID-1.9H-SM
BS0431
1
3.4OD1.75ID-1.9H-SM
BS0440
1
3.4OD1.75ID-1.9H-SM
BS0441
1
3.4OD1.75ID-1.9H-SM
BS0450
1
3.4OD1.75ID-1.9H-SM
BS0451
1
2.8OD1.2ID-3.5H-SM
BM0487
1
2
SM
SHLD-FENCE-MLB-M8-X379
OMIT_TABLE
SH0470
1
SM
TOUCH-COWLING-HOOK-X378
BS07041
2.8OD1.2ID-3.5H-SM
BM0486
1
2
2.8OD1.2ID-3.5H-SM
BM0485
1
2
2.8OD1.2ID-3.5H-SM
BM0484
1
2
2.8OD1.2ID-1.55H-SM
BM0483
1
2
2.8OD1.2ID-1.55H-SM
BM0406
1
2
POGO-2.3OD-4.63H-SM
SM
PG0470
1
POGO-2.3OD-4.63H-SM
SM
PG0471
1
TH-NSP
SL-1.1X0.4-1.4X0.7
TH0461
1
SL-1.1X0.4-1.4X0.7
TH-NSP
TH0460
1
2.7X1.8R-1.4ID-0.91H-SM
BS0701
1
2.7X1.8R-1.4ID-0.91H-SM
BS0470
1
SM
POGO-2.3OD-4.06H-SM
PG0400
1
2.8OD1.2ID-1.55H-SM
BM0411
1
2
2.8OD1.2ID-1.55H-SM
BM0410
1
2
2.8OD1.2ID-1.55H-SM
BM0409
1
2
2.8OD1.2ID-1.55H-SM
BM0408
1
2
2.8OD1.2ID-1.55H-SM
BM0407
1
2
2.8OD1.2ID-1.55H-SM
BM0405
1
2
2.8OD1.2ID-1.55H-SM
BM0404
1
2
2.8OD1.2ID-1.55H-SM
BM0403
1
2
2.8OD1.2ID-1.55H-SM
BM0402
1
2
2.8OD1.2ID-1.55H-SM
BM0401
1
2
POGO-2.3OD-4.06H-SM
SM
PG0401
1
SHLD-FENCE-MLB-M8-X379
SM
OMIT_TABLE
SH0460
1
OMIT_TABLE
SM
SHLD-FENCE-MLB-M8-X379
SH0450
1
SM
SHLD-FENCE-MLB-M8-X379
OMIT_TABLE
SH0440
1
SHLD-FENCE-MLB-M8-X379
SM
OMIT_TABLE
SH0420
1
SM
OMIT_TABLE
SHLD-FENCE-MLB-M8-X379
SH0410
1
3.4OD1.75ID-1.57H-SM
BS0460
1
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
CPU Daisy-Chain Strategy:
exist between both TP's on each corner.
Other corner test signals connected in
daisy-chain fashion. Continuity should
Each corner of CPU has two testpoints.
Port D pins out of order
to match Intel symbol.
dvt-fab10
051-00647
10.0.0
5 OF 145
5 OF 121
PEG_GPU_D2R_P<0>
PEG_GPU_D2R_P<1>
NC_DDI2_ML_C_N<2>111 
NC_DDI2_ML_C_P<2>111 
NC_DDI2_ML_C_P<3>111 
PEG_GPU_R2D_C_P<7>
PEG_GPU_R2D_C_N<6>
PEG_GPU_R2D_C_N<7>
PCIE_TBT_X_R2D_C_N<0>
PEG_GPU_R2D_C_N<5>
PEG_GPU_D2R_P<3>
PCIE_TBT_T_R2D_C_P<3>
PEG_GPU_D2R_N<0>
PCIE_TBT_X_D2R_P<3>
PCH_DISPA_BCLK
NC_DDI3_ML_P<1>111 
PCIE_TBT_T_D2R_P<2>
NC_DDI2_AUXCH_C_P 111 
NC_DDI3_ML_N<2>111 
PEG_GPU_D2R_N<3>
PEG_GPU_D2R_N<2>
PPVCCIO_S0_CPU 5 8 109 
NC_DDI1_ML_C_N<3>111 
NC_DDI1_ML_C_P<2>111 
PEG_GPU_D2R_N<1>
PEG_GPU_D2R_N<4>
PCIE_TBT_T_D2R_P<1>
PEG_GPU_D2R_P<6>
PEG_GPU_D2R_P<2>
PCIE_TBT_T_D2R_N<3>
PCIE_TBT_T_D2R_N<2>
PCIE_TBT_T_D2R_N<1>
PCIE_TBT_T_D2R_N<0>
PEG_GPU_D2R_N<5>
PEG_GPU_D2R_N<6>
PEG_GPU_D2R_N<7>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_D2R_N<2>
PCH_DISPA_SDO
PCIE_TBT_X_R2D_C_N<3>
PEG_GPU_D2R_P<4>
PEG_GPU_D2R_P<7>
PCIE_TBT_X_R2D_C_P<3>
PEG_GPU_R2D_C_P<3>
PCIE_TBT_T_R2D_C_N<2>
PCIE_TBT_X_D2R_P<1>
PEG_GPU_R2D_C_N<1>
PCIE_TBT_X_R2D_C_P<1>
PCIE_TBT_T_R2D_C_N<0>
PEG_GPU_R2D_C_N<4>
PEG_GPU_R2D_C_P<6>
PCIE_TBT_X_D2R_N<3>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_P<2>
PEG_GPU_R2D_C_N<0>
PEG_GPU_R2D_C_P<0>
PCIE_TBT_T_R2D_C_P<1>
PCIE_TBT_T_D2R_P<0>
NC_DDI1_AUXCH_C_N 111 
PEG_GPU_R2D_C_P<1>
PEG_GPU_R2D_C_P<2>
NC_DDI3_ML_N<1>111 
NC_DDI3_AUXCH_P 111 
PEG_GPU_R2D_C_P<4>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_T_R2D_C_P<2>
PCIE_TBT_T_R2D_C_P<0>
PCIE_TBT_T_D2R_P<3>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_T_R2D_C_N<3>
PCIE_TBT_X_R2D_C_P<2>
PCIE_TBT_X_R2D_C_N<1>
PCH_DISPA_SDI
NC_DDI1_ML_C_N<1>111 
PEG_GPU_D2R_P<5>
NC_DDI1_ML_C_P<3>111 
NC_DDI1_AUXCH_C_P 111 
NC_DDI2_AUXCH_C_N 111 
NC_DDI3_ML_N<3>111 
NC_DDI2_ML_C_P<1>111 
NC_DDI3_ML_N<0>111 
NC_DDI1_ML_C_P<0>111 
NC_DDI2_ML_C_P<0>111 
NC_DDI2_ML_C_N<0>111 
NC_DDI2_ML_C_N<3>111 
NC_DDI3_ML_P<2>111 
NC_DDI1_ML_C_N<2>111 
NC_DDI1_ML_C_P<1>111 
NC_DDI3_ML_P<3>111 
NC_DDI1_ML_C_N<0>111 
NC_DDI3_ML_P<0>111 
NC_DDI2_ML_C_N<1>111 
PPVCCIO_S0_CPU 5 8 109 
PCIE_TBT_X_R2D_C_P<0>
PEG_GPU_R2D_C_P<5>
NC_DDI3_AUXCH_N 111 
PCIE_TBT_T_R2D_C_N<1>
PEG_GPU_R2D_C_N<2>
PEG_GPU_R2D_C_N<3>
CPU_PCH_PM_DOWN_R
CPU_DC_C38_B38
CPU_DC_C1_B2
DMI_S2N_P<3>
DMI_S2N_N<2>
DP_INT_IG_ML_P<0>
DMI_S2N_N<1>
DP_INT_IG_ML_N<0>
DP_INT_IG_ML_N<1>
DP_INT_IG_ML_N<3>
DP_INT_IG_ML_P<1>
DP_INT_IG_ML_P<2>
CPU_PEG_RCOMP
DMI_S2N_P<0>
DMI_N2S_N<3>
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_N2S_P<0>
CPU_PCH_TRIGGER_R
PM_MEMVTT_EN
CPU_PROC_AUD_SDO_R
CPU_OPC_OPIO_RCOMP_ED2
CPU_OPC_OPIO_RCOMP
CPU_EOPIO_RCOMP
PCH_CPU_TRIGGER
DMI_S2N_P<1>
DMI_N2S_P<2>
CPU_EDP_RCOMP
CPU_DC_BR2_BR1
CPU_DC_B38_C38
CPU_DC_B2_C1
CPU_PCH_PM_DOWN_R
CPU_PROC_AUD_SDO_R
CPU_PCH_PM_DOWN
CPU_PCH_TRIGGERCPU_PCH_TRIGGER_R
DP_INT_IG_ML_N<2>
DMI_N2S_P<3>
DMI_N2S_N<0>
DMI_S2N_P<2>
DMI_S2N_N<0>
DMI_S2N_N<3>
DMI_N2S_N<2>
DP_INT_IG_AUX_N
DP_INT_IG_AUX_P
DP_INT_IG_ML_P<3>
BOM_COST_GROUP=CPU & CHIPSET
CPU DMI/PEG/FDI/RSVD
SYNC_MASTER=X363_AGOTETI SYNC_DATE=01/21/2016
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
1%
402
24.9
1/16W
MF-LFPLACE_NEAR=U0500.G2:5mm
R05101
2
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
113 13 
TP-P5 TP0505 1
TP-P5 TP0504 1
TP-P5 TP0503 1
TP-P5 TP0502 1
201
MF
20
5%
1/20W
R0526
1 2 20 
TP-P5 TP0501 1
1/20W
5%
20
MF
201
R0525
1 2 13 
71 
20 
20 
13 
201
MF
1/20W
30
5%
R0524
1 2
13 
1%
MF
49.9
1/20W
201
R05231
2
1%
49.9
MF
1/20W
201
R05211
2
49.9
1%
1/20W
MF
201
R05221
2
SKYLAKE-4+4E
OMIT_TABLE
BGA
U0500
BT13
AW13
B2
B38
BP1
BR2
C1
C38
BT29
BR25
BP25
BP31
G27
G25
G29
H23
J23
BR33
AT13
OMIT_TABLE
SKYLAKE-4+4E
BGA
U0500
E27
D27
K37
J34
H36
J38
K36
J35
H37
J37
E26
F26
H33
G38
F35
E36
H34
F37
F34
E37
B27
A27
D34
B34
E33
B33
C34
B36
F33
C33
B26
C26
A33
D37
E29
E28
B29
B28
D29
F28
A29
C28
SKYLAKE-4+4E
OMIT_TABLE
BGA
U0500
E8
F6
E5
J9
D8
E6
D5
J8
A8
B6
A5
B4
B8
C6
B5
D4
G2
D25
F24
D23
F22
D21
F20
D19
F18
E17
E16
E15
E14
E13
E12
E11
E10
E25
E24
E23
E22
E21
E20
E19
E18
D17
F16
D15
F14
D13
F12
D11
F10
A25
C24
A23
C22
A21
C20
A19
C18
B17
B16
B15
B14
B13
B12
B11
B10
B25
B24
B23
B22
B21
B20
B19
B18
A17
C16
A15
C14
A13
C12
A11
C10
MF-LF
1%
24.9
1/16W
402
PLACE_NEAR=U0500.D37:5mm
R05301
2
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
5 
113 89 
113 89 
113 89 
113 89 
113 89 
113 89 
5 
5 
5 
5 
5 
113 89 
113 89 
113 89 
113 89 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
TP
TP
TP
TP
NC
NC
OUT
TP
OUT
OUT
IN
IN
OUT
IN
SYM 13 OF 13
NCTF
NCTF
DDR_VTT_CNTL
PROC_AUDIO_SDI
PROC_AUDIO_CLK
NCTF
NCTF
ZVM*
SKTOCC*
NCTF
NCTF
PM_DOWN
PROC_AUDIO_SDO
OPC_RCOMP
PROC_TRIGIN
PROC_TRIGOUT
OPCE_RCOMP
OPCE_RCOMP2
MSM*
SYM 11 OF 13
E
D
P
D
IG
IT
A
L 
D
IS
P
LA
Y
 IN
T
E
R
F
A
C
E
S
EDP_TXN3
EDP_TXP3
EDP_TXP0
EDP_TXP1
DDI1_AUXP
DDI1_AUXN
EDP_TXN2
EDP_TXN1
EDP_DISP_UTIL
EDP_TXN0
EDP_AUXP
EDP_AUXN
EDP_TXP2
DDI3_AUXP
DDI3_AUXN
DDI2_AUXP
DDI2_AUXN
EDP_RCOMP
DDI1_TXP2
DDI1_TXN2
DDI1_TXP1
DDI1_TXN1
DDI1_TXP0
DDI1_TXN3
DDI1_TXN0
DDI2_TXP3
DDI2_TXP1
DDI2_TXP0
DDI2_TXN2
DDI2_TXN1
DDI2_TXN0
DDI1_TXP3
DDI2_TXN3
DDI2_TXP2
DDI3_TXP3
DDI3_TXP2
DDI3_TXN3
DDI3_TXN2
DDI3_TXN0
DDI3_TXP0
DDI3_TXN1
DDI3_TXP1
P
C
I E
X
P
R
E
S
S
 B
A
S
E
D
 IN
T
E
R
F
A
C
E
 S
IG
N
A
LS
D
M
I
SYM 1 OF 13 PEG_RCOMP
PEG_RXN15
PEG_RXP5
DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0
DMI_TXN2
DMI_TXN1
DMI_RXP3
DMI_RXP2
DMI_TXN3
DMI_TXN0
DMI_RXN3
DMI_RXP1
DMI_RXP0
PEG_TXN13
PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0
PEG_TXN15
PEG_TXN14
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_RXP6
PEG_RXP1
PEG_RXP0
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXN7
PEG_RXN6
DMI_RXN2
DMI_RXN1
DMI_RXN0
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
(IPU)
(IPU)
These can be placed close to
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
(IPU)
(IPU)
(IPU)
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
(IPU)
(IPU)
(IPU)
Note: Confirm values for 0603 and 0601. Different for J145
J1800 and only for debug access
To use PEG X16 configuration, simply remove CPUPEG:X8X8 and CPUPEG:X8X4X4 from BOMs.
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 
6 OF 121
PPVCC_S0_CPU8 55 109 
PP1V0_S0SW8 11 18 110 
PP1V0_S36 8 11 110 
PP1V0_S36 8 11 110 
6 OF 145
10.0.0
051-00647
dvt-fab10
TP_CPU_RSVD_AA14
TP_CPU_RSVD_AA14
TP_CPU_RSVD_AE29
TP_CPU_RSVD_N29
TP_CPU_RSVD_R14
CPU_CFG<1>
TP_CPU_RSVD_TP_D1
CPU_CFG<0>
TP_CPU_RSVD_TP_BL33
TP_CPU_RSVD_TP_BM33
CPU_CFG<18>
CPU_CFG_RCOMP
CPU_CFG<17>
CPU_CFG<16>
CPU_CFG<9>
CPU_CFG<3>
CPU_CFG<6>
CPU_CFG<7>
CPU_CFG<1>
CPU_CLK24M_NSSC_CLK_N
CPU_PWRGD
XDP_CPU_TRST_L
XDP_CPU_TDI
XDP_CPU_TCK
XDP_CPU_PRDY_L
XDP_BPM_L<3>
CPU_SM_RCOMP<1>
CPU_CLK100M_BCLK_N
CPU_CLK100M_BCLK_P
PM_THRMTRIP_L
CPU_CFG<0>
CPU_CLK100M_PCIBCLK_N
CPU_PROCHOT_L
CPU_RESET_L
CPU_CLK100M_PCIBCLK_P
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<2>
CPU_CFG<13>
CPU_CFG<8>
CPU_CFG<2>
CPU_CFG<7>
CPU_CFG<3>
CPU_CFG<9>
CPU_CFG<11>
XDP_CPU_PREQ_L
XDP_CPU_TDO
XDP_CPU_TMS
CPU_CFG<2>
CPU_CFG<4>
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
CPU_CFG<15>
CPU_CFG<14>
CPU_CFG<12>
CPU_CFG<10>
CPU_CFG<5>
CPU_CFG<6>
CPU_CFG<5>
CPU_CFG<4>
CPU_CFG<16>
TP_CPU_RSVD_TP_BT2
CPU_DC_BR1_BR2
TP_CPU_RSVD_TP_BJ34
CPU_CLK24M_NSSC_CLK_P
TP_CPU_RSVD_TP_BK24
TP_CPU_RSVD_TP_BK16
TP_CPU_RSVD_TP_BJ16
TP_CPU_RSVD_TP_BJ24
PM_SYNC
TP_CPU_RSVD_TP_BJ33
CPU_CFG<19>
CPU_PROCHOT_R_L
CPU_PECI
CPU_CATERR_L
TP_CPU_RSVD_AE29
TP_CPU_RSVD_N29
TP_CPU_RSVD_R14
BOM_COST_GROUP=CPU & CHIPSET
CPU Clock/Misc/JTAG/CFG
SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015
CPUCFG5_PDCPUPEG:X8X8
CPUPEG:X8X4X4 CPUCFG6_PD,CPUCFG5_PD
18 
18 
18 
13 
13 
115 18 13 
115 18 
115 18 
115 18 
115 18 
115 18 13 
115 18 13 
P2MM
SM
PP0603 1
P2MM
SM
PP0602
1
P2MM
SM
PP0601
1
P2MM
SM
PP0600 1
TP-P5 TP0610
1
MF-LF
1%
1/16W
402
162
R06141
2
121
MF-LF
1/16W
1%
402
R06131
2
1%
1/16W
MF-LF
402
200
R06121
2
1K
MF-LF
1/16W
402
1%
R06051
2
1%
1K
MF-LF
402
1/16W
R06011
2
PLACE_NEAR=U0500.BR30:5mm
1/16W
1%
499
MF-LF
402
R0603
1 2
201
1%
49.9
PLACE_NEAR=U0500.BM30:10mm
MF
1/20W
R06041
2
OMIT_TABLE
BGA
SKYLAKE-4+4E
U0500
BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19
BP23
BN23
BN22
BP22
BT25
BN33
BN35
BP16
BP17
BR16
BR17
BR31
BR35
BT16
BT17
C30
E30
F30
G3
G13
H24
J3
J24
BJ16
BJ24
BJ33
BJ34
BK16
BK24
BL33
BM33
BR1
BT2
D1
Y35
V6
V12
V29
V30
W1
W2
W3
AA14
AE29
N29
R14
AU13
AY13
BGA
SKYLAKE-4+4E
OMIT_TABLE
U0500
A32
B31
BR27
BT27
BM31
BT30
BM30
D31
E31
G1
H1
J2
C36
D35
BT34
BM34
BP27
BL30
BN1
BR28
BL32
BT28
BP28
BP30
BR30
BT31
BP35
J31
5%
MF
1/20W
201
NOSTUFF
1K
R06481
2
1K
5%
NOSTUFF
MF
1/20W
201
R06421
2
EDP:YES
MF
201
1/20W
1K
5%
R06441
2
CPUCFG5_PD
1K
MF
1/20W
201
5%
R06451
2
CPUCFG6_PD
1K
MF
1/20W
201
5%
R06461
2
5%
1K
NOSTUFF
MF
1/20W
201
R06471
2
NOSTUFF
201
5%
1K
1/20W
MF
R06401
2
NOSTUFF
201
1/20W
MF
1K
5%
R06411
2201
1K
5%
1/20W
MF
NOSTUFF
R06431
2
NOSTUFF
1K
5%
MF
1/20W
201
R06491
2
1%
MF-LF
1/16W
49.9
402
R06901
2
113 12 
113 12 
113 12 
113 12 
113 12 
113 12 
65 47 46 
46 
47 13 
48 47 46 1313 
MF-LF
10K
402
5%
1/16W
PLACE_NEAR=U0500.BT31:157mm
R06111
2
18 
6 
6 
6 
6 
6 
18 6 
18 6 
18 
18 
18 6 
18 6 
115 18 6 
18 6 
18 6 
18 6 
18 6 
18 
18 
18 6 
18 6 
115 18 6 
18 6 
18 
18 6 
18 6 
18 
18 
18 
18 
18 6 
18 6 
18 6 
18 6 
18 6 
18 
6 
6 
6 
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
BI
IN
IN
IN
OUT
IN
IN
IN
OUT
IN
PP
PP
PP
PP
NC
NC
TP
NC
NC
NC
NC
NC
RESERVED
SYM 12 OF 13
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CFG12
CFG15
CFG13
CFG14
CFG11
CFG10
CFG9
CFG8
CFG7
CFG6
CFG5
CFG2
CFG3
CFG4
CFG1
CFG0
RSVD
RSVD
RSVD
RSVD
VCC
VSS
VSS
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
CFG19
CFG18
CFG17
CFG16
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
CFG_RCOMP
RSVD_TP
C
LO
C
K
P
W
R
T
H
E
R
M
A
L
SYM 2 OF 13
JT
A
G
D
D
R
3
PM_SYNC
RESET*
PROC_SELECT*
PROCPWRGD
PCI_BCLKP
BCLKN
BCLKP
CLK24N
CLK24P
THERMTRIP*
PROCHOT*
PECI
CATERR*
PROC_TDO
BPM0*
BPM1*
BPM2*
BPM3*
PROC_PRDY*
PROC_PREQ*
PROC_TDI
PROC_TMS
PROC_TRST*
DDR_RCOMP2
DDR_RCOMP1
DDR_RCOMP0
PCI_BCLKN
PROC_TCK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
IN
IN
IN
IN
IN
BI
OUT
NC
BI
OUT
IN
BI
051-00647
dvt-fab10
10.0.0
7 OF 145
7 OF 1217 OF 121
7 OF 145
10.0.0
051-00647
dvt-fab10
MEM_A_DQ<25>
MEM_A_DQ<41>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<5>
MEM_A_CAB<2>
MEM_A_CAA<9>
MEM_A_CAA<4>
MEM_A_CAA<3>
MEM_A_CAA<1>
MEM_A_DQS_N<3>
MEM_A_DQS_P<3>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<49>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<26>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<14>
MEM_A_DQ<9>
MEM_A_DQ<7>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_CS_L<0>
MEM_A_CLK_P<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CKE<3>
MEM_A_CKE<2>
MEM_A_CKE<0>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<58>
MEM_A_DQ<55>
MEM_A_DQ<4>
MEM_A_CLK_N<1>
MEM_A_DQS_N<5>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQS_N<6>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<17>
MEM_A_DQ<10>
MEM_A_DQ<62>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<33>
MEM_A_CKE<1>
MEM_A_DQ<46>
MEM_A_ODT<0>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQS_N<4>
MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_CAA<5>
MEM_A_CAA<6>
MEM_A_CAA<7>
MEM_A_DQS_P<0>
MEM_A_DQS_N<7>
MEM_A_DQS_P<5>
MEM_A_DQS_N<2>
MEM_A_DQ<56>
MEM_A_CAA<8>
MEM_A_DQ<50>
MEM_A_DQ<13>
MEM_A_DQ<8>
MEM_A_DQ<6>
MEM_A_DQ<0>
MEM_A_CAB<3>
MEM_A_CAB<6>
MEM_A_CS_L<1>
MEM_A_DQ<57>
MEM_A_DQ<59>
MEM_A_CAA<2>
MEM_A_CAA<0>
CPU_DIMMB_VREFDQ
CPU_DIMMA_VREFDQ
CPU_DIMM_VREFCA
MEM_A_ALERT
DDR0_PAR
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<0>
MEM_B_CLK_N<1>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_ODT<0>
MEM_B_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CKE<1>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CKE<3>
MEM_B_DQS_P<6>
MEM_B_CAB<0>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>
MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_CAB<1>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<5>
MEM_B_CAB<4>
MEM_B_CAB<3>
MEM_B_CAB<2>
MEM_B_DQ<2>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<9>
MEM_B_DQ<4>
MEM_B_DQ<8>
MEM_B_DQ<3>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<29>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<21>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<20>
MEM_B_DQ<22>
MEM_B_DQ<30>
MEM_B_DQ<36>
MEM_B_DQ<32>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<34>
MEM_B_DQ<31>
MEM_B_DQ<33>
MEM_B_DQ<35>
MEM_B_DQ<40>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<47>
MEM_B_DQ<56>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_CAA<0>
MEM_B_CAA<1>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_B_CAA<5>
MEM_B_CAA<6>
MEM_B_CAA<7>
MEM_B_CAA<8>
MEM_B_CAA<9>
MEM_B_CAA<2>
MEM_B_DQ<61>
MEM_B_ALERT
DDR1_PAR
MEM_A_DQ<5>
MEM_A_CAB<7>
MEM_A_CAB<4>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_DQ<63>
MEM_A_DQS_P<7>
MEM_B_DQ<53>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4>
MEM_A_DQS_P<2>
MEM_A_DQS_P<1>
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
CPU DDR3 Interfaces
BOM_COST_GROUP=CPU & CHIPSET
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
26 25 24 
26 25 24 
26 25 24 
26 24 
113 26 25 
113 26 25 
26 24 
113 26 24 
113 26 24 
113 26 22 
26 23 22 
26 23 22 
26 23 22 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
26 22 
113 26 23 
113 26 23 
26 22 
113 26 22 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
113 112 
201
5%
0
1/20W
MF
R07041 2
NOSTUFF
5%
0
MF
1/20W
201
R07031 2
0
MF
201
1/20W
5%
R07011 2
5%
1/20W
MF
201
0 R07021 2
26 25 
26 25 
26 23 
26 23 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 25 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 24 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 23 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
113 26 22 
BGA
SKYLAKE-4+4E
OMIT_TABLE
U0500
AR8
AM6
AR11
AN7
AN8
AN10
AR9
AR10
AN11
AT9
AR7
AF9
AF8
AH11
AH10
AH8
AK5
AH9
AH7
AK6
AJ9
AT8
AT10
AT7
AT11
AN9
AM8
AM9
AM7
AM10
AJ11
AM11
AJ10
AF11
AE7
AF10
AE10
AB1
AB2
AA4
AA5
AB5
AB4
AA2
AA1
V5
V2
U1
U2
V1
V4
U5
U4
AA11
AA10
AC11
AC10
AA7
AA8
AC8
AC7
W8
W7
V10
V11
W11
W10
V7
V8
R2
P5
R4
P4
R5
P2
R1
P1
M4
M1
L4
L2
M5
M2
L5
L1
R11
P11
P7
R8
R10
P10
R7
P8
L11
M11
L7
M8
L10
M10
M7
L8
AA3
U3
AC9W9
P3
L3
R9
M9
AY9
AB3
V3
AA9
V9
R3
M3
P9
L9
AW9
AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7
AL5
AL6
AF7
AE8
AE9
AE11
AJ7
BJ27
BJ28
BJ35
BJ36
BK21
BK23
BK26
BK27
BK28
Y38
SKYLAKE-4+4E
OMIT_TABLE
BGA
U0500
AU5
AP1
AT4
AP3
AN3
AN1
AU1
AU4
AN2
AU3
AU2
AE3
AD1
AG4
AH4
AH5
AN4
AH1
AH2
AP4
AH3
AT1
AT2
AT3
AT5
AG2
AK1
AG1
AK2
AK3
AL1
AL3
AL2
AD5
AE2
AD2
AE5
BR6
BT6
BP3
BR3
BN5
BP6
BP2
BN3
BL4
BL5
BL2
BM1
BK4
BK5
BK1
BK2
BT11
BR11
BT8
BR8
BP11
BN11
BP8
BN8
BL12
BL11
BL8
BJ8
BJ11
BJ10
BL7
BJ7
BG4
BG5
BF4
BF5
BG2
BG1
BF1
BF2
BD2
BD1
BC4
BC5
BD5
BD4
BC1
BC2
BG11
BG10
BG8
BF8
BF11
BF10
BG7
BF7
BB11
BC11
BB8
BC8
BC10
BB10
BC7
BB7
BR5
BL3
BP9
BL9
BG3
BD3
BG9
BC9
BA3
BP5
BK3
BR9
BJ9
BF3
BC3
BF9
BB9
AY3
BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2
AP5
AP2
AD3
AE4
AE1
AD4
AG3
BP13
BR13
BN13
AJ8
B30
BH30
BJ21
BJ23
BJ26
U38
BJ13
BJ14
21 
21 
21 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
M
E
M
O
R
Y
 C
H
A
N
N
E
L 
D
D
R
1
SYM 4 OF 13
DDR1_CKN0
RSVD
DDR1_CKP0
DDR1_CKE0
DDR1_CKN1
DDR1_DQ7
DDR1_DQ6
DDR1_DQ5
DDR1_CLKP3
DDR1_MA4
DDR1_MA3
DDR1_ODT3
DDR1_ODT2
DDR1_ODT1
DDR1_ODT0
RSVD
DDR1_CLKP2
DDR1_CKP1
DDR1_CLKN3
DDR1_CLKN2
DDR1_CKE2
DDR1_CKE1
DDR1_CS3*
DDR1_CS2*
DDR1_CS1*
DDR1_CS0*
DDR1_CKE3
VSS
DDR1_DQSP6
DDR1_CAB0
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DDR1_DQSP7
DDR1_DQSP8
DDR1_ECC7
DDR1_ECC6
DDR1_ECC5
DDR1_ECC4
DDR1_ECC3
DDR1_ECC2
DDR1_DQSN0
DDR1_DQSN1
DDR1_DQSN5
DDR1_DQSN4
DDR1_DQSN6
DDR1_DQSN8
DDR1_DQSN7
DDR1_DQSP0
DDR1_DQSP1
DDR1_DQSP2
DDR1_DQSP3
DDR1_DQSP4
DDR1_DQSP5
DDR1_DQSN2
DDR1_DQSN3
DDR1_ECC1
DDR1_ECC0
DDR1_CAB1
DDR1_CAB9
DDR1_CAB8
DDR1_CAB7
DDR1_CAB6
DDR1_CAB5
DDR1_CAB4
DDR1_CAB3
DDR1_CAB2
DDR1_DQ2
DDR1_DQ0
DDR1_DQ1
DDR1_DQ9
DDR1_DQ4
DDR1_DQ8
DDR1_DQ3
DDR1_DQ14
DDR1_DQ13
DDR1_DQ12
DDR1_DQ10
DDR1_DQ11
DDR1_DQ15
DDR1_DQ16
DDR1_DQ17
DDR1_DQ18
DDR1_DQ19
DDR1_DQ29
DDR1_DQ23
DDR1_DQ24
DDR1_DQ25
DDR1_DQ26
DDR1_DQ21
DDR1_DQ27
DDR1_DQ28
DDR1_DQ20
DDR1_DQ22
DDR1_DQ30
DDR1_DQ36
DDR1_DQ32
DDR1_DQ39
DDR1_DQ38
DDR1_DQ37
DDR1_DQ34
DDR1_DQ31
DDR1_DQ33
DDR1_DQ35
DDR1_DQ40
DDR1_DQ50
DDR1_DQ49
DDR1_DQ48
DDR1_DQ46
DDR1_DQ45
DDR1_DQ44
DDR1_DQ43
DDR1_DQ42
DDR1_DQ41
DDR1_DQ47
DDR1_DQ56
DDR1_DQ58
DDR1_DQ57
DDR1_DQ60
DDR1_DQ59
DDR1_DQ55
DDR1_DQ54
DDR1_DQ53
DDR1_DQ52
DDR1_DQ51
DDR1_DQ63
DDR1_DQ62
DDR1_DQ61
DDR1_PAR
DDR1_ALERT*
DDR1_CAA0
DDR1_CAA1
DDR1_CAA3
DDR1_CAA4
DDR1_CAA5
DDR1_CAA6
DDR1_CAA7
DDR1_CAA8
DDR1_CAA9
DDR1_CAA2
M
E
M
O
R
Y
 C
H
A
N
N
E
L 
D
D
R
0
SYM 3 OF 13
DDR0_CAB1
VSS
DDR0_CKE2
DDR0_CAA9
DDR0_CAA8
DDR0_CAA7
DDR0_CAA6
DDR0_CAA4
DDR0_CAA3
DDR0_CAA2
DDR0_CAA5
DDR0_CAA1
RSVD
DDR0_CAA0
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR0_DQ63
DDR0_DQ61
DDR0_PAR
DDR0_ALERT*
DDR_VREF_CA
DDR0_DQ62
DDR0_DQ60
DDR0_DQ58
DDR0_DQ57
DDR0_DQ56
DDR0_DQ55
DDR0_DQ54
DDR0_DQ53
DDR0_DQ52
DDR0_DQ51
DDR0_DQ59
DDR0_DQ41
DDR0_DQ49
DDR0_DQ45
DDR0_DQ44
DDR0_DQ43
DDR0_DQ42
DDR0_DQ50
DDR0_DQ46
DDR0_DQ47
DDR0_DQ48
DDR0_DQ40
DDR0_DQ32
DDR0_DQ33
DDR0_DQ34
DDR0_DQ37
DDR0_DQ39
DDR0_DQ38
DDR0_DQ36
DDR0_DQ35
DDR0_DQ31
DDR0_DQ30
DDR0_DQ20
DDR0_DQ29
DDR0_DQ25
DDR0_DQ28
DDR0_DQ27
DDR0_DQ26
DDR0_DQ24
DDR0_DQ23
DDR0_DQ22
DDR0_DQ21
DDR0_DQ19
DDR0_DQ18
DDR0_DQ17
DDR0_DQ16
DDR0_DQ15
DDR0_DQ14
DDR0_DQ13
DDR0_DQ12
DDR0_DQ11
DDR0_DQ10
DDR0_DQ0
DDR0_DQ9
DDR0_DQ8
DDR0_DQ7
DDR0_DQ5
DDR0_DQ1
DDR0_DQ4
DDR0_DQ6
DDR0_DQ2
DDR0_CAB9
DDR0_CAB8
DDR0_CAB7
DDR0_CAB6
DDR0_CAB5
DDR0_CAB4
DDR0_CAB3
DDR0_CAB2
DDR0_ECC0
DDR0_DQSN7
DDR0_ECC7
DDR0_ECC6
DDR0_ECC5
DDR0_ECC4
DDR0_ECC3
DDR0_ECC2
DDR0_ECC1
DDR0_DQSN4
DDR0_DQSN3
DDR0_DQSN2
DDR0_DQSN1
DDR0_DQSN0
DDR0_DQSP4
DDR0_DQSP3
DDR0_DQSP2
DDR0_DQSP1
DDR0_DQSP0
DDR0_DQSN5
DDR0_DQSN6
DDR0_DQSN8
DDR0_DQSP5
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
DDR0_CAB0
DDR0_DQSP7
DDR0_DQSP6
DDR0_DQSP8
RSVD
DDR0_CS3*
DDR0_CS2*
DDR0_CS1*
DDR0_CS0*
DDR0_CLKP3
DDR0_CLKP2
DDR0_CKP0
DDR0_CLKN3
DDR0_CLKN2
DDR0_CKN0
DDR0_CKE3
DDR0_CKE0
DDR0_CKN1
DDR0_MA3
DDR0_MA4
DDR0_ODT3
DDR0_ODT2
DDR0_ODT1
DDR0_ODT0
DDR0_DQ3
DDR0_CKP1
DDR0_CKE1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NC
NC
NC
NC
NCNC
NC
NC
OUT
OUT
OUT
PULL-UPS FOR SENSE LINES
051-00647
8 OF 121
10.0.0
dvt-fab10
8 OF 145
PPVCCGT_S0_CPU 8 55 109 
PP1V0_S36 8 11 110 
PP1V0_S36 8 11 110 
PP1V0_S0SW6 11 18 110 
PP1V0_S36 8 11 110 
PPVCC_S0_CPU6 8 55 109 
PPVCCSA_S0_CPU 8 53 109 
PPVCC_S0_CPU 6 8 55 109 PPVCCGT_S0_CPU 8 55 109 
PPVCC_S0_CPU 6 8 55 109 
PPVCC_S0_CPU6 8 55 109 
PPVCCIO_S0_CPU 5 8 109 
PPVCCIO_S0_CPU 5 8 109 
PP1V0_S3 11 110 
PPVCCSA_S0_CPU 8 53 109 
PP1V2_S0SW109 
PP1V2_S3_CPUDDR8 109 
PP1V2_S3_CPUDDR8 109 
TP_CPU_RSVD_TP78
TP_CPU_RSVD_TP76
TP_CPU_RSVD_TP75
CPU_VIDALERT_R_L
CPU_VIDSOUT_R
CPU_VIDSCLK_R
CPU_VCCST_PWRGD_R
CPU_VCCGTSENSE_P
CPU_VCCGTSENSE_N
CPU_VIDSCLK
CPU_VCCST_PWRGD
CPU_VCCSENSE_P
CPU_VCCST_PWRGD_R
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VIDALERT_L
CPU_VCCIOSENSE_P
CPU_VIDSOUT
CPU_VCCSASENSE_P
CPU_VCCGTSENSE_P
CPU_VCCSASENSE_N
CPU_VCCSASENSE_P
CPU_VCCIOSENSE_N
CPU_VCCIOSENSE_P
SYNC_DATE=08/16/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=CPU & CHIPSET
CPU Power
70 
1%
MF-LF
1/16W
1K
402
R08401
2
1%
60.4
MF
201
1/20W
R0841
1 2
65 9 
65 9 
65 9 
71 9 
MF
5%
100
1/20W
PLACE_NEAR=U0500.M38:50.4mm
201
R08661
2
5%
MF
100
PLACE_NEAR=U0500.AH38:50.8mm
1/20W
201
R08651
2
1/20W
MF
5%
PLACE_NEAR=U0500.AG37:50.8mm
100
201
R08641
2
MF
100
201
1/20W
5%
PLACE_NEAR=U0500.H14:50.8mm
R08611
2
1UF
X6S-CERM
Place on bottom side of U05006.3V20%
0201
C08031
2
Place on bottom side of U0500
1UF
X6S-CERM
6.3V
20%
0201
C08021
2
65 8 
5%
MF
100
201
1/20W
R08021
2
56.2
1/20W
1%
MF
201
R08001
2
5%
1/20W
MF
220
201
R0810
1 2
65 8 
71 8 
PLACE_NEAR=U0500.Y12:5mm
10UF
20%
X5R-CERM
10V
0402-7
C08011
2
OMIT_TABLE
SKYLAKE-4+4E
BGA
U0500
BL22
BL23
BL24
BL25
BL26
BL27
BL28
BL31
BL34
BM22
BM24
BN16
E1
E2
E3
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
AG37
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y36
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR6
AR12
AT12
AW6
AY6
J5
J6
K6
K12
L6
L12
R6
T6
W6Y12
BH31
BH32
BH29
W4
W5
W12
W33
W34
Y7
Y8
Y9
Y10
Y11
Y13
Y14
Y37
AG38
OM
IT
_T
AB
LE
SK
YL
AK
E-
4+
4E
BG
A
U0
50
0
AJ
29
AJ
30
AJ
31
AJ
32
AJ
33
AJ
34
AJ
35
AJ
36
AK
31
AK
32
AK
33
AK
34
AK
35
AK
36
AK
37
AK
38
AL
13
AL
29
AL
30
AL
31
AL
32
AL
35
AL
36
AL
37
AL
38
AM
13
AM
14
AM
29
AM
30
AM
31
AM
32
AM
33
AM
34
AM
35
AM
36
AN
13
AN
14
AN
31
AN
32
AN
33
AN
34
AN
35
AN
36
AN
37
AN
38
AP
13
AP
14
AP
29
AP
30
AP
31
AP
32
AP
35
AP
36
AP
37
AP
38
AR
29
AR
30
AR
31
AR
32
AR
33
AR
34
AR
35
AR
36
AT
14
AT
31
AT
32
AT
33
AT
34
AT
35
AT
36
AT
37
AT
38
AU
14
AU
29
AU
30
AU
31
AU
32
AU
35
AU
36
AU
37
AU
38
AV
29
AV
30
AV
31
AV
32
AV
33
AV
34
AV
35
AV
36
AW
14
AW
31
AW
32
AW
33
AW
34
AW
35
AW
36
AW
37
AW
38
AY
29
AY
30
AY
31
AY
32
AY
35
AY
36
AY
37
AY
38
BA
13
BA
14
BA
29
BA
30
BA
31
BA
32
BA
33
BA
34
BA
35
BA
36
BB
13
BB
14
BB
31
BB
32
BB
33
BB
34
BB
35
BB
36
BB
37
BB
38
BC
29
BC
30
BC
31
BC
32
BC
35
BC
36
BC
37
BC
38
BD
13
BD
14
BD
29
BD
30
BD
31
BD
32
BD
33
BD
34
BD
35
BD
36
BE
31
BE
32
BE
33
BE
34
BE
35
BE
36
BE
37
BE
38
BF
13
BF
14
BF
29
BF
30
BF
31
BF
32
BF
35
BF
36
BF
37
BF
38
BG
29
BG
30
BG
31
BG
32
BG
33
BG
34
BG
35
BG
36
BH
33
BH
34
BH
35
BH
36
BH
37
BH
38
BJ
37
BJ
38
BL
36
BL
37
BM
36
BM
37
BN
36
BN
37
BN
38
BP
37
BP
38
BR
37
BT
37
AH
38
AH
37
OMIT_TABLE
SKYLAKE-4+4E
BGA
U0500
BL14
BM14
BP15
BR15
BT15
BN15
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH36
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
H14
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BL15
H28
J28
BH13
G11
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
M38
H30
H13
G30
H29
BM15
AH35 J14
BM16
M37
65 8 
65 
65 
0
5%
1/16W
MF-LF
402
R0811
1 2
65 
0
402
5%
MF-LF
1/16W
R0812
1 2
8 
65 8 
8 
65 8 
65 8 
71 8 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 5 OF 13
VCC
VCC
VSS_SENSE
VCC_SENSE
RSVD
RSVD
RSVD
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
RSVD_TP
RSVD_TP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_TP
RSVD
VIDALERT*
VSS
VSS
VIDSOUT
VIDSCK
RSVD
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
P
O
W
E
R
S
Y
M
 7
 O
F
 1
3
VS
SG
T_
SE
NS
E
VC
CG
T
VC
CG
T
VC
CG
T_
SE
NS
E
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
VC
CG
T
SYM 6 OF 13
POWER
VCCGTX
VCCSA
VCCSA
VCCOPC
VCCOPC
VCCOPC_SENSE
VSSOPC_SENSE
VCCSA_SENSE
VCCGTX
VCCIO
VSSEOPIO_SENSE
VCCEOPIO_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO
VCCSTG
VCCSTG
VCCST_PWRGD
VCCST
VCCIO
VCCIO
VCCIO
VCCGTX
VCCIO
VCCGTX
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCGTX
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VSSSA_SENSE
VCCPLL
VCCPLL
VCCPLL_OC
VCCPLL_OC
VCC_OPC_1P8
VCC_OPC_1P8
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCIO_SENSE
VSSIO_SENSE
VCCGTX_SENSE
VSSGTX_SENSE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
IN
OUT
BI
9 OF 145
dvt-fab10
051-00647
10.0.0
9 OF 121
CPU_DC_BR38_BT36
CPU_DC_BT36_BR38
CPU_VCCSASENSE_N
CPU_VCCIOSENSE_N
CPU_VCCGTSENSE_N
CPU_VCCSENSE_N
CPU Ground
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=J80_MLB SYNC_DATE=08/17/2015
TP-P5TP09001
TP-P5TP09011
100
5%
1/20W
MF
201
R09661
2201
5%
1/20W
MF
100
R09651
2201
5%
100
1/20W
MF
R09631
2201
5%
100
1/20W
MF
R09611
2
65 8 
71 8 
65 8 
BG
A
SK
YL
AK
E-
4+
4E
OM
IT
_T
AB
LE
U0
50
0
A3A4A3
4
B3 B3
7
BR
38
BT
3
BT
4
BT
35
BT
36
C2 D3
8
BM
35
BM
38
BN
4
BN
7
BN
9
BN
12
BN
14
BN
18
BN
29
BN
30
BN
31
BN
34
BP
7
BP
12
BP
14
BP
18
BP
21
BP
24
BP
26
BP
29
BP
33
BP
34
BR
7
BR
12
BR
14
BR
18
BR
21
BR
24
BR
26
BR
29
BR
34
BR
36 BT
5
BT
9
BT
12
BT
14
BT
18
BT
21
BT
24
BT
26
BT
32 C5 C8 C9C1
1
C1
3
C1
5
C1
7
C1
9
C2
1
C2
3
C2
5
C2
7
C2
9
C3
1
C3
7 D3 D6 D9D1
0
D1
2
D1
4
D1
6
D1
8
D2
0
D2
2
D2
4
D2
6
D2
8
D3
0
D3
3 E4 E9E3
4
E3
5
E3
8 F2 F3 F4 F5 F8 F9F1
1
F1
3
F1
5
F1
7
F1
9
F2
1
F2
3
F2
5
F2
7
F2
9
F3
1
F3
6
G
4
G
5
G
6
G
10
G
12
G
14
G
16
G
18
G
20
G
22
G
23
G
24
G
26
G
28
H2
2
H2
5
H3
2
H3
5
J4 J7J1
0
J1
8
J2
2
J2
5
J3
2
J3
3
J3
6
K1 K2 K3 K4 K5 K7 K8 K9K1
0
K1
1
K3
8
L2
9
L3
0
L3
3
L3
4
M
6
M
12
M
13
M
14
N1 N2 N3N4 N5 N6 N7 N8N9N1
0
N1
1
N1
2
N3
3
N3
4
P6P1
2
P3
7
P3
8
R1
2
R2
9
R3
0
T1 T2T3 T4 T5 T7 T8 T9T1
0
T1
1
T1
2
T1
3
T1
4
T3
3
T3
4
U3
7
A3
6
A3
7
SKYLAKE-4+4E
OMIT_TABLE
BGA
U0500
AV37
AV38
AW1
AW2
AW3
AW4
AW5
AW12
AW29
AW30
AY12
AY14
AY33
AY34
B9
BA6
BA7
BA8
BA9
BA10
BA11
BA12BA37
BA38
BB1
BB2
BB3
BB4
BB5
BB6
BB12
BB29
BB30
BC6
BC12
BC13
BC14
BC33
BC34
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD37
BD38
BE1
BE2
BE3
BE4
BE5
BE6
BE29
BE30
BF6
BF12
BF33
BF34
BG6
BG12
BG13
BG14
BG37
BG38
BH1
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
BH10
BH11
BH12
BH14
BJ12
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BK6
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BL6
BL13
BL29
BL35
BL38
BM2
BM3
BM5
BM6
BM7
BM8
BM9
BM11
BM12
BM13
BM18
BM21
BM23
BM25
BM26
BM27
BM28
BM29
BN2
BN19
BN20
BN21
BN24
G8
G9
H11
H12
H18
U6
OMIT_TABLE
SKYLAKE-4+4E
BGA
U0500
A6
A9
A10
A12
A14
A16
A18
A20
A22
A24
A26
A28
A30
AA12
AA29
AA30
AB6
AB33
AB34
AC1
AC2
AC3
AC4
AC5
AC6
AC12
AC37
AC38
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD29
AD30
AE6
AE33
AE34
AF1
AF2
AF3
AF4
AF12
AF13
AF14
AG6
AG7
AG8
AG10
AG11
AG29
AG30
AH6
AH12
AH33
AH34
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AJ37
AJ38
AK4
AK29
AK30
AL4
AL7
AL8
AL9
AL10
AL12
AL14
AL33
AL34
AM1
AM2
AM3
AM4
AM5
AM12
AM37
AM38
AN5
AN6
AN12
AN29
AN30
AP8
AP9
AP10
AP11
AP12
AP33
AP34
AR1
AR2
AR3
AR4
AR5
AR13
AR14
AR37
AR38
AT6
AT29
AT30
AU6
AU7
AU8
AU9
AU10
AU11
AU12
AU33
AU34
65 8 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
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SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
TP
TP
OUT
OUT
OUT
S
Y
M
 1
0 
O
F
 1
3
VS
S
VS
S
VS
S
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
NC
TF
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
NC
TF
VS
S
NC
TF
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
VS
S
SYM 9 OF 13
GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GROUND
SYM 8 OF 13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OUT
CPU VDDQ Decoupling
Intel recommendation: 10x 10uF 0402, 4x 22uF 0602 
CPU VCCIO Decoupling
Intel recommendation: 3x 10uF 0402 (opposite CPU)
Apple Implementation: 
Apple Implementation: 
CPU VCORE Decoupling
Apple Implementation: 
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884) 
Vcc CPU Core Decoupling from 20140905 BOM
Intel recommendation: 5x 220uF ESR 5m ohms ESL 1.9nH each,4x 47uF 0805 8x22uF 0603, 28x 10uF 0402, 3x 10uF 0402, 69x 1uF 0201 Board Edge: 2x 220uF, 4x 47uF rest on the back side
Noise Floor caps 
10 OF 121
dvt-fab10
10 OF 145
10.0.0
051-00647
PP1V2_S3_CPUDDR109 116 
PPVCC_S0_CPU109 
PPVCCIO_S0_CPU
SYNC_DATE=11/22/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN
CPU Decoupling 1 [10]
BOM_COST_GROUP=CPU & CHIPSET
2V
ELEC
220UF
20%
SM-COMBO
C10731
232V
ELEC
SM-COMBO
220UF
20%
C10721
232V
ELEC
SM-COMBO
220UF
20%
C10711
232V
ELEC
SM-COMBO
220UF
20%
C10701
23
220UF
2V
ELEC
SM-COMBO
20%
C10691
232V
ELEC
SM-COMBO
220UF
20%
C10681
23
X6S-CERM
Place near U0500 on bottom side
2.5V
20UF
20%
0402-1
C108A1
2X6S-CERM
Place near U0500 on bottom side
20UF
20%
0402-1
2.5V
C10891
2
20UF
X6S-CERM
2.5V
0402-1
Place on bottom side of U0500
20%
C10901
2
20UF
X6S-CERM
2.5V
0402-1
20%
C10951
2
0402-1
20UF
X6S-CERM
2.5V
20%
C10941
2
0402-1
20UF
X6S-CERM
2.5V
20%
C10931
2
20UF
X6S-CERM
2.5V
0402-1
Place on bottom side of U0500
20%
C10921
2
20UF
X6S-CERM
2.5V
0402-1
Place on bottom side of U0500
20%
C10911
2
0201
12PF
NP0-C0G
25V
5%
C10N71
2NP0-C0G
12PF
5%
25V
0201
C10N61
2NP0-C0G
25V
12PF
5%
0201
C10N51
225V
5%
NP0-C0G
12PF
0201
C10N41
2NP0-C0G
25V
5%
12PF
0201
C10N31
2NP0-C0G
12PF
5%
25V
0201
C10N21
225V
5%
NP0-C0G
12PF
0201
C10N11
2
NOSTUFF
20UF
20%
0402-1
2.5V
X6S-CERM
C10E31
2
NOSTUFF
X6S-CERM
2.5V
20%
0402-1
20UF
C10E21
2
NOSTUFF
0402-1
20UF
X6S-CERM
2.5V
20%
C10E11
2
20UF
20%
2.5V
NOSTUFF
0402-1
X6S-CERM
C10E01
2
20UF
20%
0402-1
2.5V
X6S-CERM
C10C11
2
20UF
2.5V
X6S-CERM
0402-1
20%
C10C01
2
X6S-CERM
Place near U0500 on bottom side
2.5V
20UF
20%
0402-1
C10881
2X6S-CERM
Place near U0500 on bottom side
2.5V
20UF
20%
0402-1
C10871
2
X6S-CERM
2.5V
0402-1
20%
Place on bottom side of U0500.
20UF
C10831
2
0402-1
20UF
X6S-CERM
2.5V
20%
Place on bottom side of U0500.
C10821
2
20%
0402-1
20UF
2.5V
X6S-CERM
C10D71
2
20UF
0402-1
X6S-CERM
2.5V
20%
C10D61
2
NOSTUFF
20UF
2.5V
0402-1
X6S-CERM
20%
C10D51
2
0402-1
2.5V
X6S-CERM
20UF
20%
C10D01
2
20%
0402-1
20UF
X6S-CERM
2.5V
C10D41
22.5V
20%
X6S-CERM
20UF
0402-1
C10D31
2X6S-CERM
2.5V
20%
20UF
0402-1
C10D21
2
20UF
2.5V
20%
0402-1
X6S-CERM
C10D11
2
0402-1
2.5V
X6S-CERM
20UF
20%
C10C71
2
20%
20UF
2.5V
0402-1
X6S-CERM
C10C61
22.5V
20UF
20%
0402-1
X6S-CERM
NOSTUFF
C10C51
2
0402-1
X6S-CERM
20UF
2.5V
20%
NOSTUFF
C10C41
2
20UF
2.5V
20%
0402-1
X6S-CERM
NOSTUFF
C10C31
2
NOSTUFF
20UF
0402-1
X6S-CERM
2.5V
20%
C10Z11
2
20UF
X6S-CERM
20%
0402-1
2.5V
C10Z21
2
20UF
0402-1
X6S-CERM
2.5V
20%
C10Z31
2
20UF
X6S-CERM
2.5V
20%
0402-1
C10Z41
2
20UF
X6S-CERM
2.5V
20%
0402-1
C10Z51
2 2.5VX6S-CERM
0402-1
20UF
20%
NOSTUFF
C10Z61
2
0402-1
2.5V
X6S-CERM
20%
20UF
NOSTUFF
C10B91
2
20UF
0402-1
2.5V
X6S-CERM
20%
NOSTUFF
C10B81
2
20UF
2.5V
X6S-CERM
0402-1
20%
NOSTUFF
C10B71
2X6S-CERM
20UF
0402-1
2.5V
20%
NOSTUFF
C10B61
2
20UF
0402-1
2.5V
X6S-CERM
20%
C10B51
2
20UF
0402-1
X6S-CERM
2.5V
20%
C10B41
2
20UF
X6S-CERM
20%
2.5V
0402-1
C10B31
2
20UF
0402-1
2.5V
X6S-CERM
20%
NOSTUFF
C10B21
2
20UF
0402-1
2.5V
X6S-CERM
20%
C10B11
2
0402-1
X6S-CERM
20UF
2.5V
20%
NOSTUFF
C10B01
2
0402-1
2.5V
20UF
20%
X6S-CERM
NOSTUFF
C10A91
2X6S-CERM
20UF
0402-1
2.5V
20%
NOSTUFF
C10A81
2X6S-CERM
2.5V
20UF
20%
0402-1
C10A71
2X6S-CERM2.5V
20%
20UF
0402-1
C10A61
2
20UF
0402-1
2.5V
X6S-CERM
20%
C10A51
2X6S-CERM
20UF
20%
2.5V
0402-1
C10A41
2X6S-CERM
2.5V
20%
0402-1
20UF
NOSTUFF
C10A31
2
20%
2.5V
X6S-CERM
0402-1
20UF
NOSTUFF
C10A21
2
20UF
X6S-CERM
2.5V
0402-1
20%
C10A11
2
20UF
20%
0402-1
2.5V
X6S-CERM
NOSTUFF
C10A01
2
4V
CERM-X6S
0201
1UF
20%
C10451
24VCERM-X6S
0201
1UF
20%
C10441
24VCERM-X6S
0201
1UF
20%
C10431
2
4V
CERM-X6S
0201
1UF
20%
C10221
24VCERM-X6S
0201
1UF
20%
C10211
24VCERM-X6S
0201
1UF
20%
C10201
2
CERM-X6S
1UF
20%
0201
4V
C10461
2
1UF
4V
CERM-X6S
0201
20%
C10471
2 4VCERM-X6S
0201
1UF
20%
C10481
2 4VCERM-X6S
1UF
20%
0201
C10491
2 4V
0201
1UF
20%
CERM-X6S
C10501
2
Place on bottom side of U0500
20%
4V
CERM-X6S
0201
1UF
C10511
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10521
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10531
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10541
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10551
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10561
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10571
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10581
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10591
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10601
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10611
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10621
2
4V
CERM-X6S
0201
1UF
20%
C10231
2
1UF
4V
CERM-X6S
0201
20%
C10241
2 4VCERM-X6S
1UF
20%
0201
C10251
2 4VCERM-X6S
0201
1UF
20%
C10261
2 4VCERM-X6S
0201
1UF
20%
C10271
2 4VCERM-X6S
0201
1UF
20%
C10281
2 4VCERM-X6S
0201
1UF
20%
C10291
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10301
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10311
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10321
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10331
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10341
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10351
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10361
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10371
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10381
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10391
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10401
2
Place on bottom side of U0500
4V
CERM-X6S
0201
20%
1UF
C10411
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10421
2
2.5V
X6S-CERM
Place near inductors on bottom side.
0402-1
20UF
20%
NOSTUFF
C10ZC1
2X6S-CERM0402-1
20UF
2.5V
Place near inductors on bottom side.
20%
NOSTUFF
C10Z71
2
0402-1
20UF
X6S-CERM
2.5V
Place near inductors on bottom side.
20%
NOSTUFF
C10Z81
2
0402-1
20UF
X6S-CERM
2.5V
Place near inductors on bottom side.
20%
NOSTUFF
C10Z91
2
20UF
0402-1
X6S-CERM
2.5V
Place near inductors on bottom side.
20%
NOSTUFF
C10ZA1
2
0402-1
20UF
20%
X6S-CERM
2.5V
Place near inductors on bottom side.
NOSTUFF
C10ZB1
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10101
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10111
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10121
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10131
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10141
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10151
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10161
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10171
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10181
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10191
2
0402-1
20UF
X6S-CERM
2.5V
20%
Place on bottom side of U0500
C10801
2
0402-1
20UF
X6S-CERM
2.5V
20%
Place on bottom side of U0500.
C10811
2
20UF
X6S-CERM
2.5V
0402-1
20%
Place on bottom side of U0500
C10841
2
Place on bottom side of U0500
20%
0402-1
20UF
X6S-CERM
2.5V
C10851
2
X6S-CERM
Place near U0500 on bottom side
2.5V
20UF
20%
0402-1
C10861
2
0201
Place on bottom side of U0500
4V
CERM-X6S
1UF
20%
C10001
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10011
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10021
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10031
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10041
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10051
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10061
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10071
2
Place on bottom side of U0500
4V
CERM-X6S
0201
1UF
20%
C10081
2 4VCERM-X6S
0201
1UF
Place on bottom side of U0500
20%
C10091
2
109 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CPU VCCPLL and VCCST Decoupling
Apple Implementation: 
Board Edge: 4x220uF, 7x 47uF rest on back side 
CPU VCCSA Decoupling
CPU VGTSlice Decoupling
Apple Implementation: 
Intel recommendation: 2x 220uF, 1x 47uF 0805. 1x 22uF. 7x 10uF 0402, 3x 1uF 0201_ 
2x 220uF, 1x 22uF on board edge, everything else on back side 
Vcc GT Slice Core Decoupling from 20140905 BOM
Intel recommendation: 7x 220uF, 6x 47uF 0805, 6x 22uF 0603, 35x 10uF 0402, 68 1uF 0201
NOTE: Intel decoupling recommendations from CBR schematics for Skylake H doc#557227 and PDG section 48.1 (document# 546884) 
CPU VCCSTG Decoupling
11 OF 121
11 OF 145
10.0.0
051-00647
dvt-fab10
PPVCCSA_S0_CPU109 
PP1V0_S38 110 
PP1V0_S0SW6 8 18 110 PP1V0_S36 8 110 
PPVCCGT_S0_CPU109 116 
BOM_COST_GROUP=CPU & CHIPSET
CPU Decoupling 2 [11]
SYNC_MASTER=X363_SEAN SYNC_DATE=02/01/2016
20%
CERM-X6S
4V
1UF
0201
C11481
2
20%
220UF
SM-COMBO
ELEC
2V
C11701
23
20%
220UF
SM-COMBO
ELEC
2V
C11K91
23
20%
220UF
SM-COMBO
ELEC
2V
C11721
23
20%
220UF
SM-COMBO
ELEC
2V
C11711
23
20%
220UF
SM-COMBO
ELEC
2V
C11691
23
20%
220UF
SM-COMBO
ELEC
2V
C11681
23
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11E01
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11E11
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11E21
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11E31
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11E41
2
NOSTUFF
20%
20UF
0402-1
X6S-CERM
2.5V
C11E51
2
20%
1UF
0201
CERM-X6S
4V
Place near U0500 on bottom side
C11M21
2
20%
1UF
0201
CERM-X6S
4V
Place near U0500 on bottom side
C11M11
2
20%
1UF
0201
CERM-X6S
4V
Place near U0500 on bottom side
C11L21
2
20%
1UF
0201
CERM-X6S
4V
Place near U0500 on bottom side
C11L11
220%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11I71
2
20%
POLY-TANT
NOSTUFF
0805
47UF
6.3V
C11J11
2
20%
POLY-TANT
NOSTUFF
0805
6.3V
47UF
C11J01
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11I01
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11I11
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11I21
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11I31
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11I41
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11I51
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11I61
220%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11H01
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U100.
C11H11
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11H21
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11D41
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11D31
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11D21
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11D11
2
20%
2.5V
X6S-CERM
0402-120UF
C11D01
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11C91
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11C81
2
20%
1UF
0201
CERM-X6S
4V
C11471
2
20%
1UF
0201
CERM-X6S
4V
C11231
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11F71
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11F61
2
20%
0402-1
2.5V
X6S-CERM
20UF
C11F51
2
20UF
NOSTUFF
20%
X6S-CERM
0402-1
2.5V
C11F01
2
20%
0402-1
2.5V
X6S-CERM
20UF
C11F41
2
20%
0402-1
NOSTUFF
2.5V
20UF
X6S-CERM
C11F31
2
20%
0402-1
X6S-CERM
20UF
2.5V
C11F21
2
20%
0402-1
X6S-CERM
2.5V
20UF
C11F11
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11C71
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11C61
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11C51
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11C41
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11C31
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11C21
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11C11
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11C01
2X6S-CERM
20%
2.5V
0402-1
20UF
C11B91
22.5VX6S-CERM
20%
0402-1
20UF
C11B81
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11B71
2
20UF
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
C11B61
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11B51
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11B41
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11B31
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11B21
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11B11
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11B01
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11A91
2
20%
NOSTUFF
2.5V
X6S-CERM
20UF
0402-1
C11A81
2
20%
2.5V
X6S-CERM
0402-1
20UF
C11A71
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11A61
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11A51
2
20%
NOSTUFF
2.5V
X6S-CERM
0402-1
20UF
C11A41
2
20%
NOSTUFF
2.5V
X6S-CERM
20UF
0402-1
C11A31
2
20%
NOSTUFF
2.5V
20UF
0402-1
X6S-CERM
C11A21
2
20%
NOSTUFF
2.5V
20UF
0402-1
X6S-CERM
C11A11
2
20%
NOSTUFF
X6S-CERM
2.5V
20UF
0402-1
C11A01
2
20%
1UF
0201
CERM-X6S
4V
C11461
2
20%
1UF
0201
CERM-X6S
4V
C11451
2
20%
1UF
0201
CERM-X6S
4V
C11441
2
20%
1UF
0201
CERM-X6S
4V
C11221
2
20%
1UF
0201
CERM-X6S
4V
C11211
2
20%
1UF
0201
CERM-X6S
4V
C11201
2
20%
4V
CERM-X6S
0201
1UF
C11491
2
20%
1UF
0201
CERM-X6S
4V
C11501
2
20%
1UF
0201
CERM-X6S
4V
C11511
2
20%
1UF
0201
CERM-X6S
4V
C11521
2
20%
CERM-X6S
Place on bottom side of U0500
1UF
4V
0201
C11531
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11541
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11551
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11561
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11571
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11581
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11591
2 CERM-X6S
20%
1UF
0201
4V
Place on bottom side of U0500
C11601
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11611
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11621
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11631
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11641
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11651
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11661
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11671
2
20%
1UF
0201
CERM-X6S
4V
C11241
2
20%
0201
4V
CERM-X6S
1UF
C11251
2
20%
1UF
0201
CERM-X6S
4V
C11261
2
20%
1UF
0201
CERM-X6S
4V
C11271
2
1UF
20%
0201
CERM-X6S
4V
C11281
2
20%
1UF
0201
CERM-X6S
4V
C11291
2
20%
1UF
0201
CERM-X6S
4V
C11301
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11311
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11321
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11331
2
1UF
20%
0201
CERM-X6S
4V
Place on bottom side of U0500
C11341
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11351
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11361
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11371
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11381
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11391
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11401
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11411
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11421
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11431
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11101
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11111
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11121
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11131
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11141
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11151
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11161
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11171
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11181
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11191
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11001
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11011
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11021
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11031
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11041
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11051
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11061
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11071
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11081
2
20%
1UF
0201
CERM-X6S
4V
Place on bottom side of U0500
C11091
2
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
(IPD-DeepSx)
(IPU)
(IPU)
(OD)
(IPU-RSMRST#)
12 OF 145
051-00647
dvt-fab10
12 OF 121
10.0.0
PP1V0_SUS 110 
SYSCLK_CLK24M_PCH
NC_PCH_SLP_A_L 20 
NC_ITPXDP_CLK100MN
NC_ITPXDP_CLK100MP
EG_CLKREQ_OUT_L 111 
SSD_CLKREQ_L_R
AP_CLKREQ_L_R
TBT_X_CLKREQ_L_R
TBT_T_CLKREQ_L_R
PM_PWRBTN_L
SMC_PCH_SUSWARN_L
SYSCLK_CLK32K_PCH
PP3V3_S0 14 20 73 110 
NC_PCH_PME_L20 
NC_PCH_SLP_WLAN_L111 
EG_PEG_CLK100M_P
EG_PEG_CLK100M_N
NC_PCH_CLK24M_XTALOUT
SMC_PCH_SUSACK_L
PP3V3_SUS14 16 17 110 
PP3V3_S012 13 15 110 
NC_PCH_CLK32K_RTCX2
PP3V0_G3H 16 17 109 
PM_PWRBTN_L12 48 
PP3V3_S4110 
PP3V3_S012 13 15 110 
PP3V3_SUS15 16 17 110 
PP3V3_S516 17 110 
NC_PCH_SLP_LAN_L 20 
NC_PCH_GPD7 20 
NC_PCH_LANPHYPC 20 
LPC_CLK24M_DPMUX_UC_R 20 
NC_CLKOUT_PCIE_2_N
PCIE_WAKE_L
LPC_CLKRUN_L
LPC_SERIRQ
AP_S0IX_WAKE_L
PCIE_WAKE_L
TBT_T_CIO_PWR_EN
ENETSD_CLKREQ_L
CAMERA_CLKREQ_L
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
TBT_T_USB_PWR_EN
TBT_W_CIO_PWR_EN
AP_S0IX_WAKE_SEL
PM_SLP_S3_L
PM_SYSRST_L
PM_PCH_SYS_PWROK
SSD_SR_EN_L
PM_RSMRST_L
CPU_CLK100M_PCIBCLK_N
PM_BATLOW_L
TBT_W_USB_PWR_EN
TBT_W_CLKREQ_L
LPC_AD<1>
PCH_DIFFCLK_BIASREF
PM_BATLOW_L
NC_CLKOUT_PCIE_12_P
NC_CLKOUT_PCIE_12_N
NC_CLKOUT_PCIE_13_P
NC_CLKOUT_PCIE_13_N
PCIE_CLK100M_SSD_N
PCIE_CLK100M_AP_N
PCIE_CLK100M_TBT_X_P
PCIE_CLK100M_TBT_X_N
PCIE_CLK100M_AP_P
NC_CLKOUT_PCIE_6_P
NC_CLKOUT_PCIE_2_P
NC_CLKOUT_PCIE_14_P
PCIE_CLK100M_TBT_T_P
NC_CLKOUT_PCIE_15_P
AP_S0IX_WAKE_L
CPU_CLK100M_PCIBCLK_P
CPU_CLK24M_NSSC_CLK_N
CPU_CLK100M_BCLK_N
PM_SLP_S5_L
AP_S0IX_WAKE_SEL
NC_CLKOUT_PCIE_6_N
PM_SLP_S3_L
NC_CLKOUT_PCIE_10_N
PM_SLP_SUS_L
CPU_CLK24M_NSSC_CLK_P
CPU_CLK100M_BCLK_P
NC_CLKOUT_PCIE_8_N
NC_CLKOUT_PCIE_10_P
NC_CLKOUT_PCIE_14_N
NC_CLKOUT_PCIE_8_P
NC_CLKOUT_PCIE_1_P
NC_CLKOUT_PCIE_1_N
NC_CLKOUT_PCIE_9_NNC_CLKOUT_PCIE_11_N
NC_CLKOUT_PCIE_15_N
RTC_RESET_L
PM_SLP_S4_L
PM_SLP_S0_L
PM_DSW_PWRGD
PM_CLK32K_SUSCLK_R
LPC_PWRDWN_L
LPC_CLKRUN_L
RTC_RESET_L
PCH_INTRUDER_L
PLT_RST_L
PCH_INTRUDER_L
NC_CLKOUT_PCIE_9_P
NC_CLKOUT_PCIE_11_P
PCIE_CLK100M_TBT_T_N
PCH_SRTCRST_L
AUD_PWR_EN
PM_SLP_SUS_L
PM_SLP_S5_L
PM_SLP_S4_L
LPC_AD<0>
LPC_SERIRQ
LPC_FRAME_R_L
LPC_AD<2>
PM_PCH_PWROK
PM_SYSRST_L
PCIE_CLK100M_SSD_P
PCH_SRTCRST_L
CAMERA_PWR_EN
PM_SLP_S0_L
LPC_AD<3>
SSD_SR_EN_L
CAMERA_PWR_EN
SMC_WAKE_SCI_L
NC_PCH_DRAM_RESET_L
LPC_AD_R<2>
LPC_AD_R<0>
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
BT_LOW_PWR_L
AUD_PWR_EN
PCH_RCIN_L_PU
SMC_RUNTIME_SCI_L
LPC_AD_R<3>
LPC_AD_R<1>
PCH_RCIN_L_PU
LPC_FRAME_L
BT_LOW_PWR_L
LPC_CLK24M_SMCLPC_CLK24M_SMC_R
SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC
PCH RTC/HDA/JTAG/SATA/CLK
BOM_COST_GROUP=CPU & CHIPSET
1/20W
MF
0
5%
0201
NOSTUFF
R12041
2
103 46 29 12 
114 35 20 
115 73 46 18 
115 70 
114 73 46 
115 46 18 12 
48 12 
OMIT_TABLE
FCBGA
H65946
SKL-PCH-SFF
U1100
AM11
AF8
AM12
AL12
AL9
AM10 AK9
AK10
AG11
AL11
AH12
AH10
AG10
AJ13
AM13
AK12
AK13
AG20
AM14
AL14
AH14
AJ18
AK14
AG16
AG18
AJ16
AM15
AL15
AH20
AM22
AG23
AJ10
AJ11
AF12
AH8
AL8
AM8
AK11
AH13
AJ8
AK3
AJ4
AG12
H65946
SKL-PCH-SFF
FCBGA
OMIT_TABLE
U1100
J3
J4
H1
H2
J1
J2
L6
L5
J5
F2
K6
F3
G2
E2
K2
L1
M3
M2
R6
T6
N3
P5
N5
M6
J6
F1
K5
F4
G3
E1
K3
L2
M4
M1
R7
T5
N2
P6
N6
M7
AJ14
AH15
AL16
AL20
AM19
AK20
AL19
AH22
AK22
AM25
AH26
AL25
AF26
AK26
AL26
AJ27
AH27
AM26
AK27
E4
B4
B3
PLACE_NEAR=U1100.E4:1.25mm
2.7K
1%
MF
201
1/20W
R1234
2 1
115 113 18 
115 113 18 
10%
1UF
X5R
10V
402-1
C1202 1
2
10%
1UF
X5R
10V
402-1
C12031
2
1/20W
5%
MF
201
20K
R12031
2
1/20W
20K
5%
201
MF
R12021
21/20W
201
5%
MF
1M
R12011
2
MF1/20W5% 201
100KR1251 1 2
5% MF
100K
1/20W 201
R1248 1 2
2011/20W MF5%
3.0KR1247 1 2
20
1
10
0K
R1
24
6
1
2
20
1
10
0K
R1
24
5
1
2
20
1
10
0K
R1
24
4
1
2
20
1
10
0K
R1
24
3
1
2
20
1
10
0K
R1
24
2
1
2
20
1
10
0K
R1
24
1
1
2
20
1
47
K
R1
24
0
1
2
20
1
47
K
R1
23
8
1
2
20
1
47
K
R1
23
9
1
2
29 
20 
20 
20 
20 
20 
103 
103 
29 
19 12 
19 12 
20 
20 
20 
20 
20 
20 
113 35 
113 35 
27 
27 
113 87 
113 87 
5%
100K
201MF1/20W
R1237 1 2
20 
20 
5% MF1/20W 201
100KR1216 1 2
5%
100K
1/20W MF 201
R1236 1 2
5% 1/20W MF
100K
201
R1215 1 2 5% 1/20W MF 201
100KR1214 1 2
1/20W MF 201
100K
5%
R1233 1 2
5% MF 2011/20W
10KR1213 1 2
10K
201MF1/20W5%
R1212 1 2
2015% 1/20W MF
100KR1211 1 2
5% 201MF
1K
1/20W
R1210 1 2 1/20W
100K
MF 2015%
R1209 1 2
100K
2011/20W MF5%
R1232 1 2 1/20W
100K
201MF5%
R1231 1 2
100K
201MF1/20W5%
R1230 1 2
5% 1/20W MF 201
10KR1208 1 2
10K
5% 1/20W MF 201
R1206 1 2
5% MF 2011/20W
100KR1207 1 2
46 12 
70 46 20 12 
35 12 
46 
48 
48 
46 
PLACE_NEAR=U1100.AJ14:1.4mm
22
1/20W MF 2011%
R1235
1 2
46 12 
113 6 
113 6 
113 6 
113 6 
113 6 
113 6 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
111 
101 
101 
111 
111 
111 
111 
113 20 
20 
89 46 
PLACE_NEAR=U1100.AL14:1.25mm
1/20W MF
33
2015%
R1444 1 2 1/20W5% MF
33
201
R1443 1 2 1/20W 2015%
33
MF
R1442 1 2 1/20W 2015% MF
33R1441 1 2
89 46 
89 46 
89 46 
1/20W 201MF5%
33R1440 1 2 89 46 
46 12 
73 70 12 
114 101 89 76 73 70 46 27 20 12 
73 70 46 43 20 12 
73 46 20 12 
47 
46 12 
19 12 
46 
201
MF
5%
100K
1/20W
R12051
2
19 12 
46 12 
46 12 
19 12 
114 101 89 76 73 70 46 27 20 12 
12 
103 46 29 12 
73 46 20 12 
19 12 
73 70 12 
12 
73 70 46 43 20 12 
70 46 20 12 
12 
12 
12 
12 
59 12 
115 46 18 12 
12 
12 
12 
12 
20 
46 12 
46 12 
35 12 
59 12 
12 
12 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
OUT
IN
IN
IN
IN
IN
SYM 4 OF 12
E
S
P
I/L
P
C
R
T
C
SYSTEM POWER MANAGEMENT
/SUSPWRDNACK
/SX_EXIT_HOLDOFF*
GPD10/SLP_S5*
GPP_A14/SUS_STAT*/ESPI_RESET*
GPP_A8/CLKRUN*
DSW_PWROK
GPP_A13/SUSWARN*
GPD3/PWRBTN*
GPD1/ACPRESENT
SRTCRST*
RTCRST*
INTRUDER*
RSMRST*
RTCX1
RTCX2
SYS_PWROK
GPP_B13/PLTRST*
GPP_A11/PME*
GPD9/SLP_WLAN*
GPP_A12/BMBUSY*/ISH_GP6
GPP_B12/SLP_S0*
GPD0/BATLOW*
GPP_A15/SUSACK*
SYS_RESET*
PCH_PWROK
SLP_SUS*
GPD8/SUSCLK
GPP_A0/RCIN*/ESPI_ALERT1*
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPD7/RSVD
GPP_A7/PIRQA*/ESPI_ALERT0*
GPP_A6/SERIRQ/ESPI_CS1*
GPP_A5/LFRAME*/ESPI_CS0*
GPP_B2/VRALERT*
GPD11/LANPHYPC
GPD2/LAN_WAKE*
SLP_LAN*
GPD6/SLP_A*
GPD4/SLP_S3*
GPD5/SLP_S4*
DRAM_RESET*
WAKE*
C
LO
C
K
 S
IG
N
A
LS
PCI EXPRESS
CLOCKS & CONTROL
SYM 2 OF 12
/ESPI_CLK
CLKOUT_PCIE_P2
CLKOUT_PCIE_P15
CLKOUT_PCIE_P14
CLKOUT_PCIE_P13
CLKOUT_PCIE_P12
CLKOUT_PCIE_P11
CLKOUT_PCIE_P10
CLKOUT_PCIE_P9
CLKOUT_PCIE_P7
CLKOUT_PCIE_P6
CLKOUT_PCIE_P5
CLKOUT_PCIE_P4
CLKOUT_PCIE_P3
CLKOUT_PCIE_P1
CLKOUT_PCIE_P0
CLKOUT_PCIE_N15
CLKOUT_PCIE_N14
CLKOUT_PCIE_N13
CLKOUT_PCIE_N12
CLKOUT_PCIE_N11
CLKOUT_PCIE_N10
CLKOUT_PCIE_N9
CLKOUT_PCIE_N7
CLKOUT_PCIE_N6
CLKOUT_PCIE_N5
CLKOUT_PCIE_N4
CLKOUT_PCIE_N3
CLKOUT_PCIE_N2
CLKOUT_PCIE_N1
CLKOUT_PCIE_N0
CLKOUT_PCIE_N8
CLKOUT_PCIE_P8
GPP_A10/CLKOUT_LPC1
CLKOUT_ITPXDP_P
GPP_A9/CLKOUT_LPC0
CLKOUT_ITPXDP_N
GPP_A16/CLKOUT_48
XCLK_BIASREF
XTAL24_IN
XTAL24_OUT
GPP_B10/SRCCLKREQ5*
GPP_B8/SRCCLKREQ3*
GPP_B9/SRCCLKREQ4*
GPP_H1/SRCCLKREQ7*
GPP_H2/SRCCLKREQ8*
GPP_H3/SRCCLKREQ9*
GPP_H4/SRCCLKREQ10*
GPP_B5/SRCCLKREQ0*
GPP_B6/SRCCLKREQ1*
GPP_H0/SRCCLKREQ6*
GPP_B7/SRCCLKREQ2*
CLKOUT_CPUNSSC_P
CLKOUT_CPUPCIBCLK_P
CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUNSSC_N
CLKOUT_CPUBCLK_P
CLKOUT_CPUBCLK_N
GPP_H9/SRCCLKREQ15*
GPP_H7/SRCCLKREQ13*
GPP_H6/SRCCLKREQ12*
GPP_H5/SRCCLKREQ11*
GPP_H8/SRCCLKREQ14*
OUT
OUT
OUT
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
OUT
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
IN
IN
(IPD)
(IPU)
(IPD)
(Undriven)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
10.0.0
051-00647
dvt-fab10
13 OF 121
13 OF 145
NC_PCH_TP1_AH920 
NC_CLINK_CLK 115 
NC_CLINK_RESET_L 115 
PCH_JTAGX
NC_CLINK_DATA 115 
NC_PCH_TP1_AG920 
NC_PCH_STRP_BSSB_SEL_GPIO
PP3V3_S0 12 13 15 110 
PP3V3_SUS 16 17 110 
NC_PCH_STRP_BSSB_SEL_GPIO 13 20 
PP3V3_S0 12 13 15 110 
NC_SPI_CS2_L
NC_SPI_CS1_L
NC_HDA_SDIN1 115 
CPU_PCH_TRIGGER
PM_SYNC_R
CPU_PCH_PM_DOWN
XDP_PCH_OBSDATA_B2
DMI_N2S_N<1>
DMI_S2N_P<0>
DMI_N2S_P<1>
DMI_S2N_N<3>
DMI_N2S_N<0>
SPI_MOSI_R
SPI_MISO
SPI_IO<3>
DMI_S2N_N<2>
DMI_S2N_P<2>
DMI_N2S_N<3>
DMI_N2S_P<2>
DMI_S2N_N<0>
SPI_IO<2>
DMI_N2S_P<0>
DMI_N2S_P<3>
DMI_S2N_N<1>
DMI_S2N_P<1>
DMI_N2S_N<2>
TPAD_SPI_MISO_R
AUD_SPI_MOSI
CPU_PWRGD
HDA_BIT_CLK_R
HDA_RST_R_L
TPAD_SPI_MOSI
TP_PCH_DMIC_DATA1
PCH_DISPA_BCLK_R
BT_I2S_R2D_R
TP_PCH_DMIC_CLK1
BT_I2S_D2R_R
BT_I2S_CLK_R
TP_PCH_DMIC_DATA0
DMI_S2N_P<3>
XDP_PCH_TCK
ITP_PMODE
XDP_PCH_TDI
BT_I2S_SYNC_R
PCH_DISPA_SDO_R
TPAD_SPI_MISO
TPAD_SPI_CS_L_R
XDP_CPU_PREQ_L
PM_THRMTRIP_L_R
BT_I2S_SYNC
PM_SYNC
HDA_BIT_CLK
BT_PWRRST_L
AUD_SPI_MOSI
TP_PCH_DMIC_CLK0
PCH_PROCPWRGD
AUD_SPI_CS_L
TPAD_SPI_CLK_R
TPAD_SPI_MOSI_R
AUD_SPI_CLK
HDA_SDOUT_R
HDA_SYNC_R
AUD_SPI_CLK
TPAD_SPI_CLK
TPAD_SPI_MISO
AUD_SPI_MISO
CPU_PECI
PM_THRMTRIP_L
XDP_CPU_PRDY_L
CPU_RESET_L
TPAD_SPI_CS_L
SPI_CS0_R_L
AUD_SPI_CS_L
XDP_PCH_TMS
SPI_CLK_R
SPI_CS0_R_L
HDA_SDIN0HDA_SYNC
HDA_SDOUT
BT_I2S_CLK
BT_I2S_D2R
BT_I2S_R2D
PCH_DISPA_SDO
PCH_DISPA_SDI
HDA_RST_L
PCH_CPU_TRIGGER_R PCH_CPU_TRIGGER
XDP_CPU_TRST_L
BT_TIMESTAMP
BT_PWRRST_L
PCH_PECI
PCH_DISPA_BCLK
XDP_PCH_OBSDATA_A2
BT_TIMESTAMP
TPAD_SPI_CLK
TPAD_SPI_MOSI
AUD_SPI_MISO
TPAD_SPI_CS_L
XDP_PCH_TDO
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015
PCH DMI/FDI/PM/GFX/PCI
1/20W 201MF5%
1KR1341 1 2
NO STUFF
5%
1/20W
100K
201
MF
R13311
2
35 
35 
35 
35 
33
MF201 1/20W 5%
R1330 12
33
201 1/20WMF 5%
R1329 12
33
1/20WMF 5%201
R1328 12201
33
5%MF 1/20W
R1327 12
150K
201
5%
1/20W
MF
R13261
2
114 43 13 
114 43 13 
114 43 13 
43 13 
201 MF 5%
33
1/20W
R132512MF 1/20W 5%
0
201
R132412201
33
MF 5%1/20W
R132312201
33
1/20W 5%MF
R132212
20 
20 
MF201 5%
33
1/20W PLACE_NEAR=U1100.AD4:1.27mm
R132112
5%
33
1/20WMF201 PLACE_NEAR=U1100.AE3:1.27mm
R132012
20 
5 
5 
1/20W
33
PLACE_NEAR=U1100.AB6:1.27mm 2015% MF
R1314 1 2
5 
PLACE_NEAR=U1100.AE7:1.27mm 1/20W 201
33
5% MF
R1319 1 2 6 
1/20W 201MF5%
1K
OMIT
R1318 1 2
100K
MF 2011/20W5%
R1317 1 2
MF5% 201
100K
1/20W
R1316 1 2 MF 201
150K
5% 1/20W
R1307 1 2
47K
5% 1/20W 201MF
R1306 1 2 1/20W
47K
MF 2015%
R1305 1 2
1/20W
47K
5% MF 201
R1304 1 2
1/20W5% MF 201
47KR1302 1 2 2011/20W MF
47K
5%
R1301 1 2
1/20W
1K
MF5% 201
R1303 1 2 1/20W
47K
5% MF 201
R1300 1 2
115 18 6 
115 18 6 
115 18 6 
6 
5% 1/20W
201MF
620R1309 1 2 MF
1/20W
0201
0
5%
R1308 1 2
48 47 46 6 
6 
47 6 13
1/20W5%
201MF
R1315 1 2
20 13 
14 
18 
35 13 
111 
111 
57 
57 18 
57 
57 18 
57 13 
57 
PLACE_NEAR=U1100.AJ7:1.27mm
33
1/20WMF 5%201
R131012
58 
33
1/20W201 5%MF PLACE_NEAR=U1100.AM5:2.27mm
R131212
58 
58 
58 
33
201 MF 1/20W 5% PLACE_NEAR=U1100.AJ6:1.5mm
R131312 58 
PLACE_NEAR=U1100.AM6:1.27mm5%
33
201 1/20WMF
R131112
115 18 
20 
115 18 
115 18 
115 18 
OMIT_TABLE
FCBGA
H65946
SKL-PCH-SFF
U1100
AE3
AE1
AD4
AC30
AD31
AE30
AC31
AB32
AB31
AA33
AA32
AJ7
AM5
AK5
AK6
AJ6
AM6
AF1
AG6
AF5
AF6
AG5
AF4
A25
AA6
AA7
AF24
AH11
AL4
AL5
B11
B25
C11
C19
C2
D19
D2
H5
H6
W5
Y5
Y6
AH9
AG9
OMIT_TABLE
H65946
SKL-PCH-SFF
FCBGA
U1100
AG3
AG2
AH4
AK21
AJ21
AJ20
AK19
AL23
AJ23
AH23
AH24
AJ26
AJ24
AK25
AG25
AM24
AK24
AH25
AM23
OMIT_TABLE
SKL-PCH-SFF
FCBGA
H65946
U1100
AF2E20
F19
F21
G22
F20
G19
E21
F22
B19
C20
A21
C22
A19
B20
B21
D22
AH21
AM21
AK23
W28
U29
AD7
AB6
AB5
AC6
AD5
AE7
AE4
AE6
AC4
AC5
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
113 5 
13 
114 43 13 
20 
20 
20 
18 
13 
13 
20 
13 
13 
13 
114 43 13 
114 43 13 
13 
43 13 
57 13 
13 
13 
35 13 
13 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
IN
BI
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
BI
OUT
OUT
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
BI
BI
BI
BI
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
JT
A
G
SYM 1 OF 12
A
U
D
IO
R
S
V
D
 &
 T
P
 P
IN
S
TP1
TP2
GPP_D8/I2S0_SCLK
GPP_D7/I2S0_RXD
GPP_D5/I2S0_SFRM
DISPA_BCLK
HDA_RST*
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
JTAG_TDO
JTAG_TMS
JTAGX
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
ITP_PMODE
JTAG_TCK
JTAG_TDI
GPP_D20/DMIC_DATA0
GPP_D19/DMIC_CLK0
GPP_D18/DMIC_DATA1
GPP_D17/DMIC_CLK1
HDA_SDO
GPP_D6/I2S0_TXD
DISPA_SDO
DISPA_SDI
HDA_SDI0
HDA_SDI1
HDA_SYNC
HDA_BCLK
G
S
P
I
C
-L
IN
K
S
P
I
SYM 3 OF 12
SPI0_CLK
SPI0_CS1*
SPI0_CS2*
SPI0_MOSI
SPI0_MISO
SPI0_IO2
SPI0_IO3
SPI0_CS0*
CL_RST*
CL_DATA
CL_CLK
GPP_B19/GSPI1_CS*
GPP_B20/GSPI1_CLK
GPP_B21/GSPI1_MISO
GPP_B22/GSPI1_MOSI
GPP_B16/GSPI0_CLK
GPP_B15/GSPI0_CS*
GPP_B17/GSPI0_MISO
GPP_B18/GSPI0_MOSI
C
P
U
/M
IS
C
D
M
I
SYM 5 OF 12
THERMTRIP*
PECI
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B23/SML1ALERT*/PCHHOT*
CPU_TRST*
PLTRST_PROC*
PRDY*
PREQ*
PCH_TRIGIN
PCH_TRIGOUT
PM_DOWN
PROCPWRGD
PM_SYNC
DMI_RXP3
DMI_TXN1
DMI_TXP0
DMI_TXN2
DMI_TXP2
DMI_TXN3
DMI_TXP3
DMI_RXN0
DMI_RXP0
DMI_RXN1
DMI_RXP1
DMI_RXN2
DMI_RXN3
DMI_RXP2
DMI_TXP1
DMI_TXN0
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
14 OF 121
NC_PCH_CAM_EXT_BOOT_L
XDP_PCH_OBSDATA_C2 14 103 
XDP_PCH_OBSDATA_C0 14 29 
XDP_PCH_OBSDATA_C1 14 29 
XDP_PCH_OBSDATA_C114 29 
PP3V3_S0 12 20 73 110 
NC_PCH_GPP_F17
NC_PCH_GPP_F16
XDP_PCH_OBSDATA_C0 14 29 
NC_PCH_GPP_F18
PCIE_SSD_D2R_P<3> 14 113 
PCIE_SSD_D2R_P<2> 14 
PCIE_SSD_D2R_N<2> 14 
NC_HDD_PWR_EN
XDP_PCH_OBSDATA_C3 14 103 
NC_PCH_GPP_F15
XDP_PCH_OBSDATA_C1 14 29 
NC_WOL_EN
PCIE_SSD_D2R_N<1> 14 
PCIE_SSD_D2R_P<1> 14 
PCIE_SSD_D2R_P<0> 14 113 
XDP_PCH_OBSDATA_C2 14 103 
PP3V3_SUS
12 16 17 110 
XDP_PCH_OBSDATA_C014 29 
NC_PCH_CAM_RESET
PCIE_SSD_D2R_N<1>14 
PCIE_SSD_D2R_P<1>14 
PCIE_SSD_D2R_N<0> 14 113 
PCIE_SSD_D2R_N<2>14 
PCIE_SSD_D2R_N<3> 14 113 
PCIE_SSD_D2R_P<0>14 113 
PCIE_SSD_D2R_N<3>14 113 
PCIE_SSD_D2R_P<2>14 
PCIE_SSD_D2R_N<0>14 113 
PCIE_AP_D2R_P14 
PCIE_SSD_D2R_P<3>14 113 
PCIE_AP_D2R_N14 
PCIE_AP_D2R_P14 
PCIE_AP_D2R_N14 
XDP_PCH_OBSDATA_C3 14 103 
XDP_PCH_OBSDATA_C214 103 
XDP_PCH_OBSDATA_C314 103 
14 OF 145
10.0.0
051-00647
dvt-fab10
XDP_PCH_OBSDATA_D3
XDP_PCH_OBSDATA_A0
XDP_PCH_OBSFN_C0
TBT_POC_RESET
XDP_PCH_OBSFN_C1
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSFN_C0
SSD_RESET_L
TBT_T_PCI_RESET_L
TBT_X_PCI_RESET_L
PCIE_SSD_R2D_C_P<2>
SSD_PWR_EN
XDP_PCH_OBSDATA_B3
PCIE_SSD_R2D_C_P<3>
PCIE_SSD_R2D_C_N<3>
PCIE_SSD_R2D_C_N<2>
PCIE_SSD_R2D_C_N<1>
SSD_PWR_EN
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_D1
XDP_PCH_OBSDATA_D0
USB2_VBUSSENSE
PCIE_SSD_R2D_C_N<0>
USB3_TEST_D2R_P
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
USB3_TEST_R2D_P
USB3_TEST_R2D_N
USB3_TEST_D2R_N
USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
PCIE_SSD_R2D_C_P<1>
USB2_COMP
USB2_ID
XDP_PCH_OBSDATA_A0
XDP_PCH_OBSDATA_B1
XDP_PCH_OBSDATA_B3
XDP_PCH_OBSDATA_B2
XDP_PCH_OBSDATA_A1
XDP_PCH_OBSDATA_C0 MAKE_BASE=TRUE
XDP_PCH_OBSDATA_C1 MAKE_BASE=TRUE
MAKE_BASE=TRUE PCIE_SSD_D2R_N<2>
MAKE_BASE=TRUE PCIE_SSD_D2R_N<3>
PCIE_SSD_D2R_N<1>MAKE_BASE=TRUE
PCH_PCIE_RCOMPP
MAKE_BASE=TRUE PCIE_SSD_D2R_P<2>
PCH_PCIE_RCOMPN
PCIE_SSD_D2R_P<1>MAKE_BASE=TRUE
PCIE_SSD_D2R_P<3>MAKE_BASE=TRUE
MAKE_BASE=TRUE PCIE_SSD_D2R_P<0>
MAKE_BASE=TRUE PCIE_SSD_D2R_N<0>
PCIE_AP_D2R_PMAKE_BASE=TRUE
PCIE_AP_D2R_NMAKE_BASE=TRUE
PCIE_SSD_R2D_C_P<0>PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
USB_UPC_PCH_XA_N
USB_CAMERA_DFR_P
USB_UPC_PCH_XB_N
USB_CAMERA_DFR_N
USB_UPC_PCH_TA_P
USB_UPC_PCH_TA_N
USB_TEST_P
USB_TEST_N
USB_UPC_PCH_XA_P
USB_UPC_PCH_TB_N
USB_UPC_PCH_XB_P
NC_USB2N_6
NC_USB2P_6
NC_USB2N_8
NC_USB2N_12
NC_USB2P_12
NC_USB2N_13
NC_USB2P_13
NC_USB2N_14
NC_USB2P_14
NC_USB2P_10
NC_USB2N_10
NC_USB2P_9
NC_USB2N_9
NC_USB2P_8
USB_UPC_PCH_TB_P
MAKE_BASE=TRUEXDP_PCH_OBSDATA_C3
MAKE_BASE=TRUEXDP_PCH_OBSDATA_C2
SYNC_DATE=04/14/2016SYNC_MASTER=X363_SAKKOC
PCH PCI-E/USB
BOM_COST_GROUP=CPU & CHIPSET
18 
18 
18 
18 
114 
114 
114 
114 
114 
114 
77 
113 77 
77 
113 77 
113 77 
77 
87 
113 87 
113 35 
113 35 
113 87 
113 87 
113 77 
113 77 
113 77 
113 77 
113 77 
113 77 
13 
TP-P5 TP1887
1TP-P5 TP1886
1TP-P5 TP1885
1TP-P5 TP1884
1TP-P5 TP1883
1TP-P5 TP1882
1
1/20W
5%
1K
MF
201
R14111
2
5%
1K
1/20W
MF
201
R14101
2
115 114 87 14 
20 
115 114 87 20 
20 
20 
20 
103 29 15 
20 
18 
18 
20 
18 
18 
18 
18 
18 
201
MF
113
1%
PLACE_NEAR=U1100.V1:10.0mm
1/20W
R14701
2
111 
111 
111 
111 
113 38 
11338 
29 
FCBGA
H65946
SKL-PCH-SFF
OMIT_TABLE
U1100
W31
Y30
W29
V32
V33
W33
U27
U30
T32
T30
T28
R32
T33
P27
P29
R29
N28
T29
R31
M29
P33
E10
F10
B12
A12
E11
F11
D12
C12
G12
F12
B13
C13
E13
F13
B14
A14
G14
F14
D14
C14
E15
F15
A15
B15
G15
G16
C16
B16
F18
E18
B18
C18
F23
E23
B22
A22
E24
F24
B23
C23
F25
G25
A24
B24
F26
E26
C25
D25
D27
D28
B26
C26
E28
F27
A27
B27
H27
G27
A28
B28
G28
F29
B29
C29
G29
G30
B30
C30
H29
H28
C31
B31
J29
J28
D32
C32
K28
K29
E31
E32
B10
A10
SKL-PCH-SFF
H65946
OMIT_TABLE
FCBGA
U1100
W30
U31
U33
V31
P30
N29
P31
L29
V1
W6
U2
V4
W2
U6
Y1
U4
AA4
T1
AA2
R3
AB3
R2
AC1
P1
AD2
V3
W3
U7
Y2
T4
AA3
T2
AA1
R4
AB2
R1
AC2
P2
AD1
F5
G5
D4
D5
G6
F6
B6
A6
G7
H7
C6
B7
D7
E7
C8
B8
F8
G8
B9
A8
F9
G9
C9
D9
29 
29 
29 
1/20W MF 2015%
10KR1421 1 2 MF 201
10K
5% 1/20W
R1420 1 2
100
1%
1/20W
MF
201
R14001
2
1/20W5%
10K
MF 201
R1460 1 2
1/20W
100K
5% 201MF
R1462 1 2
10K
1/20W 201MF5%
R1461 1 2
103 
103 
103 
103 
29 
29 
29 
29 
113 35 
113 35 
14 
14 
14 
14 
14 
115 114 87 14 
14 
14 
14 
14 
14 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
BI
BI
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
IN
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
TP
TP
TP
TP
TP
TP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
BI
IN
PCIE/SATA/USB3
SYM 8 OF 12
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXP/SATA4_TXP
PCIE17_TXN/SATA4_TXN
PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN
PCIE18_RXN/SATA5_RXN
PCIE18_TXP/SATA5_TXP
PCIE18_TXN/SATA5_TXN
PCIE18_RXP/SATA5_RXP
PCIE10_TXP/SATA1A_TXP
PCIE10_TXN/SATA1A_TXN
PCIE10_RXP/SATA1A_RXP
PCIE9_TXP/SATA0A_TXP
PCIE9_TXN/SATA0A_TXN
PCIE9_RXP/SATA0A_RXP
PCIE10_RXN/SATA1A_RXN
PCIE13_RXN/SATA0B_RXN
PCIE14_RXN/SATA1B_RXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXP/SATA0B_RXP
PCIE13_TXN/SATA0B_TXN
PCIE14_RXP/SATA1B_RXP
PCIE14_TXP/SATA1B_TXP
PCIE15_RXN/SATA2_RXN
PCIE14_TXN/SATA1B_TXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE9_RXN/SATA0A_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
PCIE_RCOMPP
PCIE_RCOMPN
GPP_F12/SDATAOUT1
GPP_F13/SDATAOUT0
GPP_F11/SLOAD
GPP_F10/SCLOCK
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F4/SATAXPCIE7/SATAGP7
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E0/SATAXPCIE0/SATAGP0
PCIE4_TXP/USB3_10_TXP
PCIE4_RXP/USB3_10_RXP
PCIE4_TXN/USB3_10_TXN
PCIE4_RXN/USB3_10_RXN
PCIE3_TXP/USB3_9_TXP
PCIE3_TXN/USB3_9_TXN
PCIE3_RXP/USB3_9_RXP
PCIE3_RXN/USB3_9_RXN
PCIE2_TXP/USB3_8_TXP
PCIE2_TXN/USB3_8_TXN
PCIE2_RXP/USB3_8_RXP
PCIE2_RXN/USB3_8_RXN
PCIE1_TXP/USB3_7_TXP
PCIE1_TXN/USB3_7_TXN
PCIE1_RXP/USB3_7_RXP
PCIE1_RXN/USB3_7_RXN
PCIE12_TXN
PCIE12_TXP
PCIE12_RXN
PCIE12_RXP
PCIE11_TXP
PCIE11_TXN
PCIE11_RXP
PCIE11_RXN
PCIE8_TXP
PCIE8_RXP
PCIE8_TXN
PCIE8_RXN
PCIE7_TXP
PCIE7_TXN
PCIE7_RXP
PCIE7_RXN
PCIE6_RXN
PCIE5_TXN
PCIE5_TXP
PCIE5_RXP
PCIE5_RXN
GPP_E8/SATALED*
GPP_F9/DEVSLP7
GPP_F7/DEVSLP5
GPP_F8/DEVSLP6
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
SYM 7 OF 12
U
S
B
3
U
S
B
2
USB2_VBUSSENSE
USB2_ID
USB2_COMP
USB2N_10
USB2P_10
USB2N_13
USB2P_13
USB2N_12
USB2P_12
USB2N_11
USB2P_11
USB2N_14
GPP_E9/USB2_OC0*
GPP_E10/USB2_OC1*
GPP_E11/USB2_OC2*
GPP_E12/USB2_OC3*
GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7
USB2P_14
USB2N_1
USB2P_2
USB2N_3
USB2P_3
USB2P_1
USB2N_2
USB2P_6
USB2N_6
USB2P_4
USB2N_5
USB2P_5
USB2N_4
USB2N_7
USB2P_8
USB2N_8
USB2P_7
USB2P_9
USB2N_9
USB3_5_RXP
USB3_5_RXN
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXP
USB3_4_TXN
USB3_5_TXN
USB3_5_TXP
USB3_6_RXN
USB3_6_TXN
USB3_6_RXP
USB3_6_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_TXP/SSIC_2_TXP
OUT
OUT
IN
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
 0x16 = 1 0 1 1 0
PVT = 0x17 = 1 0 1 1 1 (-10 PCB)
DVT1-1 = 0x18 = 1 1 0 0 0 (-09 PCB)
 EVT2 = 0x1A = 1 1 0 1 0 (-07 PCB)
 DVT = 0x19 = 1 1 0 0 1 (-08 PCB)
RAM Configuration Straps
 0x14 = 1 0 1 0 0
 0x15 = 1 0 1 0 1
 EVT1 = 0x1B = 1 1 0 1 1 (-06 PCB)
PROTO 1 = 0x1D = 1 1 1 0 1 (-03 PCB)
PROTO 2 = 0x1C = 1 1 1 0 0 (-04 & -05 PCB)
PROTO 0B = 0x1E = 1 1 1 1 0 (-02 PCB)
PROTO 0 = 0x1F = 1 1 1 1 1 (-01 PCB)
MLB BOARD ID Configuration Straps
PROJ-SPECIFIC PULLUP, GPPBCH RAIL
15 OF 121
051-00647
dvt-fab10
15 OF 145
10.0.0
NC_PCH_DDPB_CTRLCLK
NC_PCH_DDPC_CTRLCLK
NC_ISOLATE_CPU_MEM_L
PP3V3_SUS 16 17 110 
PP3V3_S0 12 13 110 
PP3V3_SUS 12 16 17 110 
TBT_T_CIO_PLUG_EVENT_L 15 103 
ALS_SOC_UART_R2D 15 20 
ALS_SOC_UART_D2R 15 20 
TBT_X_CIO_PLUG_EVENT_L 15 29 
NC_AUD_IPHS_SWITCH_EN
NC_AUD_IP_PERIPHERAL_DET
ALS_SOC_UART_D2R 15 20 
NC_TP_PCH_GPP_G8 111 
NC_AUD_I2C_INT_L
NC_TP_PCH_GPP_G3 111 
NC_SDCONN_STATE_CHANGE
NC_BKLT_FAULT_INT_L
NC_PCH_DDPD_CTRLCLK
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
ALS_SOC_UART_R2D 15 20 
TBT_T_CIO_PLUG_EVENT_L
NC_TBT_W_PLUG_EVENT_L
NC_CAMERA_RESET_L
NC_PCH_STRP_TLSCONF
NC_I2C_UPC_SDA
NC_ENET_MEDIA_SENSE
NC_I2C_UPC_SCL
NC_TP_PCH_GPP_G1 111 
NC_TP_PCH_GPP_G2 111 
NC_TCON_RESET_L
NC_ENET_LOW_PWR
NC_SDCONN_OC_L
DPMUX_UC_IRQ
NC_EDP_IG_BKLT_PWM
NC_TP_PCH_GPP_G7 111 
NC_TP_PCH_GPP_G6 111 
NC_TP_PCH_GPP_G5 111 
NC_TP_PCH_GPP_G4 111 
SOC_SWD_CLK 15 20 42 
NC_PCH_BSSB_DATA
NC_SPKR_ID1 15 20 
NC_PCH_BSSB_CLK
NC_SPKR_ID1
NC_PCH_STRP_ESPI
SOC_PCH_DBELL_L 15 20 38 
PCH_SOC_DBELL_L 15 20 37 
PCH_SOC_DBELL_L15 20 37 
SOC_SWD_CLK15 20 42 
PP1V8_SUS16 17 109 
SOC_PCH_DBELL_L15 20 38 
TBT_X_CIO_PLUG_EVENT_L
20 
BOARD_ID:17
BOARD_ID:18
BOARD_ID:16
RAMCFG4:L,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
RES,MF,1/20W,1KOHM,5%,0201,SMD
29 
BOARD_ID:1A
BOARD_ID:19
PCH_DDPB_CTRLDATA
PCH_DDPC_CTRLDATA
PCH_DDPD_CTRLDATA
JTAG_ISP_TDO
PCH_SWD_IO
SOC_S2R_ACK_L
TBT_X_DPMUX_SEL
MLB_BOARD_ID1
JTAG_ISP_TDI
LCD_PSR_EN
DP_INT_IG_HPD
AP_DEV_WAKE
DEBUGUART_SEL_SOC
SOC_PANIC_L
SOC_PANIC_L
PCH_SOC_WDOG
PP1V8_SSD_FMC
PCH_SOC_FORCE_DFU
PCH_SWD_MUX_SEL
PCH_BT_ROM_BOOT
PCH_SWD_MUX_SEL
SMBUS_PCH_CLK
PCH_SWD_IO
SML_PCH_0_CLK
SMBUS_PCH_DATA
SML_PCH_0_DATA
DEBUGUART_SEL_SOC
PCH_SOC_DFU_STATUS
MLB_BOARD_ID3
TPAD_SPI_IF_EN
SSD_DEBUGI2C_SEL_PCH
PCH_STRP_TOPBLK_SWP_L
SPKR_ID0_NC
EDP_IG_BKLT_EN
EDP_IG_BKLT_EN
EDP_IG_PANEL_PWR_EN
EDP_IG_PANEL_PWR_EN
PCH_BT_UART_D2R
DP_X_SNK1_HPD_IG
DP_X_SNK0_HPD_IG
SPIROM_USE_MLB
DP_T_SNK0_HPD_IG
DP_T_SNK1_HPD_IG
MLB_RAMCFG3
MLB_RAMCFG4
MLB_RAMCFG2
MLB_RAMCFG1
MLB_RAMCFG0
PCH_UART2_CTS_L
MLB_BOARD_ID4
TBT_W_PCI_RESET_L
JTAG_TBT_W_TMS
PCH_BT_UART_CTS_L
PCH_UART2_CTS_L
SOC_UART_CTS_L
MLB_RAMCFG0
MLB_BOARD_ID0
MLB_RAMCFG2
SOC_UART_D2R
SOC_UART_R2D
I2C_SSD_SDA
I2C_SSD_SCL
PCH_BT_UART_RTS_L
PCH_BT_UART_R2D
MLB_RAMCFG1
MLB_RAMCFG3
MLB_BOARD_ID1
JTAG_ISP_TDI
AP_DEV_WAKE
JTAG_TBT_T_TMS
SSD_BOOT_L
MLB_RAMCFG4
MLB_BOARD_ID2
LCD_PSR_EN
SOC_UART_RTS_L
JTAG_ISP_TCK
JTAG_TBT_X_TMSMLB_BOARD_ID4
SOC_S2R_ACK_L
PCH_BT_ROM_BOOT
MLB_BOARD_ID3
TBT_POC_RESET
SPKR_ID0_NC
JTAG_ISP_TCK
MLB_BOARD_ID2
MLB_DEV_L
MLB_BOARD_ID0
JTAG_TBT_X_TMS
JTAG_TBT_T_TMS
JTAG_TBT_W_TMS
PCH_BT_UART_D2R
PCH_BT_UART_CTS_L
I2C_SSD_SDA
I2C_SSD_SCL
SOC_UART_D2R
SOC_UART_R2D
SOC_UART_RTS_L
PCH_BT_UART_R2D
JTAG_ISP_TDO
MLB_DEV_L
PCH_BT_UART_RTS_L
SSD_DEBUGI2C_SEL_PCH
SOC_UART_CTS_L
LCD_IRQ_L
TPAD_SPI_INT_L
SPIROM_USE_MLB
TPAD_SPI_IF_EN
AP_RESET_L
LCD_IRQ_L
TBT_T_DPMUX_SEL
TPAD_SPI_INT_L
PCH GPIO/MISC/NCTF
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016
BOARD_ID:15R1543,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD
RAMCFG_SLOT
117S0006 0 RES,MF,1/20W,1KOHM,5%,0201,SMD
RES,MF,1/20W,1KOHM,5%,0201,SMD1117S0006 R1540
RES,MF,1/20W,1KOHM,5%,0201,SMD1 R1541117S0006 BOARD_ID:1D
R1542,R15412117S0006 RES,MF,1/20W,1KOHM,5%,0201,SMD
2117S0006 R1541,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD
R1543,R1541,R15403117S0006 BOARD_ID:14
RES,MF,1/20W,1KOHM,5%,0201,SMD2117S0006 R1543,R1540
117S0006 3 RES,MF,1/20W,1KOHM,5%,0201,SMD
R1542,R1540RES,MF,1/20W,1KOHM,5%,0201,SMD117S0006 2
RES,MF,1/20W,1KOHM,5%,0201,SMD R1542 BOARD_ID:1B1117S0006
117S0006 R15431 RES,MF,1/20W,1KOHM,5%,0201,SMD
100K
5% 1/20W MF 201
NO STUFFR1599 1 2 5%
100K
1/20W 201MF
R1526 1 2
2015%
100K
1/20W MF
R1563 1 2
1/20W 201MF5%
100KR1561 1 2
1/20W5% MF
100K
201
R1562 1 2
MF 2015% 1/20W
100KR1560 1 2
MF 2011/20W5%
100KR1559 1 2
1/20W 201MF5%
100KR1558 1 2
38 15 
111 
89 15 
89 15 
100K
1/20W5%
R1557 1 2
5%
MF
1/20W
100K
201
R15561
2
37 
201MF1/20W5%
10KR1553 1 2
1/20W 201MF5%
10KR1555 1 2
10K
5% 1/20W 201MF
R1554 1 2
100K
1/20W MF 2015%
R1552 1 2
114 87 15 
1/20W5% MF 201
100KR1550 1 2
5% 1/20W MF 201
47KR1551 1 2
MF
1K
2011/20W
BOMOPTION=OMIT
5%
R1528 1 2
5% MF
1K
2011/20W
R1509 1 2 MF
1K
2015% 1/20W
R1508 1 2
MF 2011/20W5%
100KR1513 1 2
MF5% 1/20W
10K
201
R1512 1 2
MF
1K
2015% 1/20W
BOMOPTION=OMITR1527 1 2
1/20W5% MF 201
100KR1535 1 2
1/20W MF 2015%
100KR1524 1 2
5% MF 201
100K NO STUFF
1/20W
R1525 1 2
1/20W MF 2015%
100KR1515 1 2
1/20W 201MF5%
100KR1529 1 2
1/20W MF 201
100K
5%
R1548 1 2 MF
100K
1/20W5% 201
R1536 1 2
100K
201MF1/20W5%
R1549 1 2
201MF5% 1/20W
100KR1511 1 2
5% MF
100K
1/20W
R1546 1 2
NO STUFF
MF 2011/20W5%
100KR1539 1
1/20W 2015% MF
100KR1547 1 2
5%
100K
1/20W MF
R1538 1 2
100K
MF 2011/20W5%
R1537 1 2
20 
20 
20 
1/20W
5%
MF
1K NOSTUFF
201
R15451
2
201
1K
MF
1/20W
MLB_ID4:L
5%
R15441
2
1K
5%
MF
1/20W
MLB_ID0:L
201
R15401
2
1/20W
5%
1K
201
MLB_ID1:L
MF
R15411
2
5%
201
1K
1/20W
MLB_ID2:L
MF
R15421
2
5%
201
MF
MLB_ID3:L
1/20W
1K
R15431
2
201
1K
MF
1/20W
5%
RAMCFG4:L
R15341
2
20 15 
MF5% 201
47K
1/20W
R1522 1 2 2015% 1/20W MF
47KR1521 1 2 2015% 1/20W
47K
MF
R1520 1 2
MF 2011/20W5%
47KR1523 1 2
1K
5%
1/20W
MF
201
RAMCFG0:L
R15301
2
201
MF
1K
5%
1/20W
RAMCFG3:L
R15331
2
MF
201
1K
5%
1/20W
RAMCFG2:L
R15321
2
1/20W
MF
1K
5%
201
RAMCFG1:L
R15311
2
MF5%
47K
1/20W 201
R1507 1 2 201MF
47K
1/20W5%
R1506 1 2
47K
MF5% 1/20W 201
R1505 1 2
47K
5% MF1/20W 201
R1504 1 2 MF1/20W5%
47K
201
R1503 1 2
20 
20 
20 
20 
20 
89 
89 
89 
89 
89 
20 
103 15 
15 
20 
20 
20 
20 
20 
101 29 
103 29 15 
20 
20 
20 
114 57 15 
20 
20 
20 
20 
86 15 
86 15 
35 15 
35 15 
35 15 
35 15 
20 
86 15 
43 15 
91 
43 15 
114 76 15 
91 
114 36 35 20 
20 
49 
20 
20 
49 
49 
49 
49 
49 
FCBGA
SKL-PCH-SFF
U1100
AK16
AM18
AL18
AH16
AH18
AK15
AG15
AG22
AG21
AM20
AL22
AJ30
AK31
AK32
AJ32
AH31
AH33
AH32
AG32
AG29
AF28
AF30
AF29
AG33
AH30
AG31
AF33
AE33
AF31
AE29
AE27
AD33
AD32
AE32
AE31
AD28
AD29
AC27
AC29
AC33
AB28
AB29
AB30
Y31
Y27
AA29
AA28
Y29
Y33
AA31
AC32
SKL-PCH-SFF
H65946
FCBGA
OMIT_TABLE
U1100
R28
M28
P32
N31
N30
L27
N33
M33
M32
M31
L30
L33
L32
L31
J32
J33
K30
K33
H32
H31
K31
J31
F31
G31
G33
H33
E33
E30
F32
F33
AM27
AK28
AJ29
AG27
AH28
AG28
AM28
AL28
AK29
AM29
AL29
AH29
AL30
AL31
AH3
AJ5
AH7
AH2
AH1
AG1
AJ2
AK2
AL3
AH5
5% 1/20W MF
47K
201
R1502 1 2
29 15 
29 15 
27 15 
SSD_BOOT_L
H65946
R1542,R1541,R1540
AG7
BOARD_ID:1C
15 
29 
115 
OMIT_TABLE
BOARD_ID:1E
BOARD_ID:1F
201MF
201
2012
103 
42 15 
38 15 
15 
29 15 
15 
15 
15 
38 15 
37 
84 83 81 80 78 77 
115 114 15 
38 
42 15 
35 15 
42 15 
42 15 
15 
15 
47 
15 
89 15 
89 15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
20 15 
20 15 
15 
15 
15 
15 
15 
15 
15 
15 
15 
38 15 
35 15 
15 
103 29 14 
15 
29 15 
15 
15 
15 
29 27 15 
103 101 29 15 
15 
35 15 
35 15 
86 15 
86 15 
20 15 
20 15 
15 
35 15 
103 29 15 
15 
35 15 
86 15 
15 
114 76 15 
43 15 
114 57 15 
43 15 
82 114 
87 
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
PART# DESCRIPTIONQTY
TABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
TABLE_BOMGROUP_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
BI
BI
BI
OUT
OUT
OUT
OUT
BI
OUT
BI
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
BI
OUT
BI
BI
SYM 6 OF 12
G
P
P
D
/IN
T
E
G
R
A
T
E
D
 S
E
N
S
O
R
/U
A
R
T
/I2
C
G
P
P
C
/S
M
LI
N
K
/I2
C
/U
A
R
T
G
P
P
B
G
P
P
A
/
IN
T
E
G
R
A
T
E
D
 S
E
N
S
O
R
GPP_C23/UART2_CTS*
GPP_C22/UART2_RTS*
GPP_C21/UART2_TXD
GPP_C19/I2C1_SCL
GPP_C20/UART2_RXD
GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA
GPP_C15/UART1_CTS*/ISH_UART1_CTS*
GPP_C16/I2C0_SDA
GPP_C14/UART1_RTS*/ISH_UART1_RTS*
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C11/UART0_CTS*
GPP_C10/UART0_RTS*
GPP_C9/UART0_TXD
GPP_C8/UART0_RXD
GPP_C7/SML1DATA
GPP_C6/SML1CLK
GPP_C5/SML0ALERT*
GPP_C4/SML0DATA
GPP_C2/SMBALERT*
GPP_C3/SML0CLK
GPP_C1/SMBDATA
GPP_C0/SMBCLK
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_B0
GPP_D10
GPP_D11
GPP_D12
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL
GPP_D15/ISH_UART0_RTS*
GPP_D16/ISH_UART0_CTS*
GPP_A17/ISH_GP7
GPP_B1
GPP_B11
GPP_B14/SPKR
GPP_D9
GPP_D0/SPI1_CS*
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL
G
P
P
I/D
IS
P
LA
Y
G
P
P
H
/I2
C
/IN
T
E
G
R
A
T
E
D
 S
E
N
S
O
R
/S
M
LI
N
K
G
P
P
G
G
P
P
F
/
B
A
C
K
LI
G
H
T
SYM 9 OF 12
GPP_F19/EDP_VDDEN
GPP_F14
GPP_F22
GPP_F23
GPP_I0/DDPB_HPD0
GPP_I2/DDPD_HPD2
GPP_I1/DDPC_HPD1
GPP_F21/EDP_BKLTCTL
GPP_I3/DDPE_HPD3
GPP_F20/EDP_BKLTEN
GPP_I4/EDP_HPD
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_H10/SML2CLK
GPP_H11/SML2DATA
GPP_H12/SML2ALERT*
GPP_H13/SML3CLK
GPP_H14/SML3DATA
GPP_H15/SML3ALERT*
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H19/ISH_I2C0_SDA
GPP_H18/SML4ALERT*
GPP_H21/ISH_I2C1_SDA
GPP_H20/ISH_I2C0_SCL
GPP_H22/ISH_I2C1_SCL
GPP_H23
GPP_G16/GSXCLK
GPP_G17/ADR_COMPLETE
GPP_G18/NMI*
GPP_G19/SMI*
GPP_G15/GSXSRESET*
GPP_G13/GSXSLOAD
GPP_G0/FAN_TACH_0
GPP_G14/GSXDIN
GPP_G12/GSXDOUT
GPP_G8/FAN_PWM_0
GPP_G10/FAN_PWM_2
GPP_G9/FAN_PWM_1
GPP_G11/FAN_PWM_3
GPP_G7/FAN_TACH_7
GPP_G6/FAN_TACH_6
GPP_G4/FAN_TACH_4
GPP_G5/FAN_TACH_5
GPP_G3/FAN_TACH_3
GPP_G1/FAN_TACH_1
GPP_G2/FAN_TACH_2GPP_G21
GPP_G20
GPP_G22
GPP_G23
OUT
IN
OUT
GPPD 1.8V
Current data from LPT EDS (doc #486708, Rev 1.0).
dvt-fab10
051-00647
10.0.0
16 OF 145
16 OF 121
PP1V0_SUS 17 110 
PP1V0_SUS17 110 
PP3V0_G3H 12 17 109 
PP3V3_SUS 17 110 
PP1V0_SUS110 PP3V3_SUS 17 110 
PP3V3_SUS 17 110 
PP3V3_SUS 13 17 110 
PP3V3_S017 110 
PP1V8_SUS 15 16 17 109 
PP3V3_SUS 15 16 17 110 
PP3V3_SUS 15 16 17 110 
PP1V_SUSSW_PCH_VCCAMPHYPLL_F 17 
PP3V3_SUS12 14 17 
110 
PP1V0_SUS110 
PP1V_SUS_PCH_VCCCLK5_F17 
PP1V_SUSSW_PCH_VCCAMPHYPLL_F 17 
PP3V3_SUS 12 15 17 110 
PP1V0_SUS110 
PP1V0_SUS110 
PP1V_SUS_PCH_VCCUSB2HDAPLL_F
17 
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.0V
PP3V3_S5 12 17 110 
PP1V0_SUS17 110 
PP1V8_S017 109 
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
PP1V_SUS_PCH_VCCUSB2HDAPLL_F 17 
PP1V8_SUS15 16 17 
109 
PP1V_S5_PCH_DCPDSW
PPDCPRTC_PCH
PP1V_SUS_PCH_VCCHDAPLL_F
PP1V8_S0_PCH_VCCHDA_F
SYNC_DATE=01/25/2016SYNC_MASTER=X363_SAKKOC
PCH Power
BOM_COST_GROUP=CPU & CHIPSET
0603
FERR-220-OHM-2A
VCCHDA:SUS
L1602
1 2
0201
NP0-C0G
+/-0.1PF
25V
3.0PF
C1601 1
2
0201
25V
3.0PF
+/-0.1PF
NP0-C0G
C1600 1
2
0.1UF
10%
X5R
6.3V
0201
C16031
2
X5R
6.3V
10%
0201
0.1UF
C16021
2
0603
FERR-220-OHM-2A
VCCHDA:S0
L1601
1 2
0603
FERR-220-OHM-2A
L1600
1 2
FCBGA
H65946
SKL-PCH-SFF
OMIT_TABLE
U1100
J7
K1
K11
K12
K14
K15
K16
K17
K18
K20
K23
K27
K32
K4
K7
L10
L11
L13
L20
L21
L23
L28
L3
L4
L7
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M27
M30
M5
N1
N10
N11
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N27
N32
N4
N7
P12
P13
P14
P21
P22
P24
P28
P3
P4
P7
R10
R11
R12
R13
R14
R21
R22
R23
R24
R27
R30
R33
R5
T10
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T24
T27
T3
T31
T7
U1
U10
U11
U12
U13
U20
U21
U22
U24
U28
U3
U32
U5
V10
V11
V12
V13
V2
V20
V21
V23
V24
V27
V28
V29
V30
V5
V6
V7
W1
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W24
W27
W32
W4
W7
Y10
Y11
Y12
Y13
Y20
Y21
Y22
Y23
Y24
Y28
Y3
Y32
Y4
Y7
D1
C1
B1
A2
A3
A4
B2
A30
A31
A32
A33
B33
C33
D33
B32
AJ33
AK33
AL33
AM33
AM32
AM31
AM30
AL32
AM4
AM3
AM2
AM1
AL1
AK1
AJ1
AL2
H65946
SKL-PCH-SFF
OMIT_TABLE
FCBGA
U1100
A11
A13
A16
A18
A20
A23
A26
A29
A5
A7
A9
AA10
AA11
AA12
AA13
AA20
AA21
AA24
AA27
AA30
AA5
AB1
AB11
AB13
AB14
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB24
AB27
AB33
AB4
AB7
AC12
AC13
AC15
AC16
AC18
AC21
AC23
AC24
AC28
AC3
AC7
AD10
AD11
AD12
AD15
AD17
AD21
AD23
AD24
AD27
AD3
AD30
AD6
AE2
AE28
AE5
AF10
AF11
AF13
AF14
AF15
AF16
AF18
AF19
AF20
AF21
AF22
AF23
AF25
AF27
AF3
AF32
AF7
AF9
AG13
AG14
AG19
AG24
AG26
AG30
AG4
AG8
AH19
AH6
AJ12
AJ15
AJ19
AJ22
AJ25
AJ28
AJ3
AJ31
AJ9
AK18
AK30
AK4
AK7
AK8
AL10
AL13
AL21
AL24
AL27
AL6
AL7
AM16
AM7
AM9
B5
C10
C15
C21
C24
C27
C28
C3
C4
C5
C7
D10
D11
D13
D15
D16
D18
D20
D21
D23
D24
D26
D29
D3
D30
D31
D6
D8
E12
E14
E16
E19
E22
E25
E27
E29
E3
E5
E6
E8
E9
F16
F28
F30
F7
G1
G10
G11
G13
G18
G20
G21
G23
G24
G26
G32
G4
H3
H30
H4
J10
J13
J14
J15
J16
J17
J18
J19
J20
J21
J22
J23
J24
J27
J30
SKL-PCH-SFF
H65946
OMIT_TABLE
FCBGA
U1100
AD19
AD18
K24
L24
K22
L22
T12
K10
M10
M11
K13
L12
J11
J12
AC20
AD20
P10
P11
AD13
AC11
K21
K19
L14
L15
L16
L17
L18
L19
AC19
AA22
AA23
AB23
V22
W22
W23
T23
U23
P23
AA14
AA15
AA16
AA17
AA18
AA19
AB15
N12
N13
P15
P16
P17
P18
P19
P20
R15
R16
R17
R18
R19
R20
T11
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
V18
V19
Y14
Y15
Y16
Y17
Y18
Y19
AB12
AC14
AD14
AC17
AD16
AC22
AD22
AB10
AC10
17 
17 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
SYM 12 OF 12
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_24
VSS_NCTF_23
VSS_NCTF_22
VSS_NCTF_21
VSS_NCTF_20
VSS_NCTF_19
VSS_NCTF_18
VSS_NCTF_17
VSS_NCTF_16
VSS_NCTF_15
VSS_NCTF_14
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_11
VSS_NCTF_10
VSS_NCTF_9
VSS_NCTF_8
VSS_NCTF_7
VSS_NCTF_6
VSS_NCTF_5
VSS_NCTF_4
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 11 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SYM 10 OF 12
DEEP SX WELL
POWER
PRIMARY WELL
PRIMARY WELL HVCMOS
PCIE PLL EBB PRIMARY
THERMAL SENSOR PW
HD AUDIO POWER
C
LO
C
K
 B
U
F
F
E
R
S
 P
R
IM
A
R
Y
 1
.0
 V
ANALOG PLL USB2/VRM
RTC LOGIC PW/VRM
SPI
RTC WELL SUPPLY
GPPG PRIMARY WELL
PRIMARY WELL
GPPE/GPPEF
GPPD PRIMARY WELL
PRIMARY WELL
GPPB/GPPC/GPPH
GPPA PRIMARY WELL
MIPI PLL
PCIE2/SATA2/PCIE3
ANALOG PLL USB3/
AUDIO PLL
MOD PHY PRIMARY
VCCPRIM_3P3
VCCPRIM_3P3
VCCPRIM_3P3
VCCDSW_3P3
VCCDSW_3P3
VCCDSW_3P3
VCCMPHY_1P0
VCCMPHY_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCHDA
VCCCLK5
VCCCLK5
VCCCLK3
VCCCLK4
VCCCLK2
VCCCLK2
VCCCLK1
VCCATS
VCCAPLLEBB_1P0
DCPDSW_1P0
VCCAPLLEBB_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCDSW_3P3
VCCMPHY_1P0
VCCMPHY_1P0
VCCHDAPLL_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCMPHY_1P0
VCCPGPPD
VCCPGPPD
VCCPGPPD
VCCPGPPBCH
VCCPGPPA
VCCPGPPBCH
VCCPGPPBCH
VCCMIPIPLL_1P0
VCCSPI
VCCSPI
VCCRTC
VCCRTCPRIM_3P3
DCPRTC
VCCPGPPG
VCCPGPPEF
VCCPGPPEF
VCCUSB2PLL_1P0
VCCUSB2PLL_1P0
1000PF CAPS ARE INTEL PLACEHOLDERS & ALL PLACENEAR NEED TO BE UPDATED
RAIL SIDE
Current data from LPT EDS (doc #486708, Rev 1.0).
PCH SIDE
17 OF 121
17 OF 145
10.0.0
051-00647
dvt-fab10
VOLTAGE=1V
VOLTAGE=1V
VOLTAGE=1V
VOLTAGE=1V
VOLTAGE=3.3V
PP1V8_S016 109 
PP3V3_SUS
15 16 110 
PP3V3_SUS16 110 
PP1V0_SUS110 
PP3V3_SUS
13 16 110 
PP3V0_G3H12 16 109 
PP3V3_SUS16 110 
PP1V0_SUS16 110 
PP3V3_SUS12 14 16 110 
PP1V8_SUS
15 16 109 
PP1V_SUSSW_PCH_VCCAMPHYPLL_F 16 
PP1V_SUS_PCH_VCCUSB2HDAPLL_F 16 
PP1V_SUS_PCH_VCCUSB2HDAPLL_F 16 
PP1V_SUSSW_PCH_VCCAMPHYPLL_F 16 
PP1V0_SUS
110 
PP3V3_S512 16 110 
PP1V_SUS_PCH_VCCCLK5_F 16 
PP3V3_S016 110 
PP3V3_SUS12 15 16 110 
PP1V0_SUS
16 110 
PP1V0_SUS16 110 
PP3V3_SUS16 110 
PP1V0_SUS110 
PP1V_SUS_PCH_VCCUSB2HDAPLL_F
MAKE_BASE=TRUE
PP1V_SUSSW_PCH_VCCAMPHYPLL_FMAKE_BASE=TRUE
MAKE_BASE=TRUE
PP1V_SUS_PCH_VCCCLK5_F
PP1V_S5_PCH_DCPDSW
PPDCPRTC_PCH
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=CPU & CHIPSET
PCH DECOUPLING
L1700,L1701,L1702RES,MF,1A MAX,0OHM,5%,0603113S0022 3
PLACE_NEAR=U1100.P23:1MM
16V
X5R-CERM
10%
0.1UF
0201
C17141
2
PLACE_NEAR=U1100.U23:1MM
0.1UF
10%
0201
16V
X5R-CERM
C17131
2
6.3V
0805
20%
47UF
POLY-TANT
PLACE_NEAR=U1100.AC10:2.1MM
C17111
2 X6S-CERM
6.3V
0201
20%
PLACE_NEAR=U1100.AC11:1MM
1UF
C17121
2
0603
OMIT_TABLE
2.2UH-240MA-0.221OHM
PLACE_NEAR=U1100.AC10:3.6MM
L1702
1 2
PLACE_NEAR=U1100.AA23:1MM
16V
X5R-CERM
0201
10%
0.1UF
C17101
2
1UF
20%
6.3V
0201
PLACE_NEAR=U1100.J11:1MM
X6S-CERM
C17071
2
6.3V
1UF
PLACE_NEAR=U1100.K21:1MM
0201
20%
X6S-CERM
C17051
2
PLACE_NEAR=U1100.U17:1MM
6.3V
22UF
20%
603
X5R-CERM-1
C1700 1
2
PLACE_NEAR=U1100.V17:1MM
6.3V
402
10%
1UF
CERM
C17011
2
47UF
6.3V
0805
20%
POLY-TANT
PLACE_NEAR=U1100.K24:1MM
C17041
2
2.2UH-240MA-0.221OHM
PLACE_NEAR=U1100.K24:3MM
OMIT_TABLE
0603
L1700
1 2
6.3V
PLACE_NEAR=U1100.J12:1MM
20%
POLY-TANT
47UF
0805
C17061
2
OMIT_TABLE
PLACE_NEAR=U1100.J12:3MM
2.2UH-240MA-0.221OHM
0603
L1701
1 2
PLACE_NEAR=U1100.AB12:1MM
16V
X5R-CERM
0201
10%
0.1UF
C17201
2
PLACE_NEAR=U1100.AD14:1MM
6.3V
X6S-CERM
0201
20%
1UF
C17191
2
PLACE_NEAR=U1100.L17:1MM
6.3V
X6S-CERM
0201
20%
1UF
C17021
2
PLACE_NEAR=U1100.AC17:1MM
16V
X5R-CERM
0.1UF
0201
10%
C17221
2
PLACE_NEAR=U1100.AC17:1MM
6.3V
20%
X6S-CERM
0201
1UF
C17211
2
6.3V
X6S-CERM
1UF
0201
PLACE_NEAR=U1100.K22:1MM
20%
C17031
2
PLACE_NEAR=U1100.T12:1MM
20%
6.3V
1UF
X6S-CERM
0201
C17181
2
PLACE_NEAR=U1100.AD19:1MM
20%
6.3V
X6S-CERM
1UF
0201
C17081
2
PLACE_NEAR=U1100.AD18:1MM
16V
0201
X5R-CERM
10%
0.1UF
C17091
2
PLACE_NEAR=U1100.P10:1MM
10V
20%
CERM
0.1UF
402
C17241
2
PLACE_NEAR=U1100.AC22:1MM
16V
0.1UF
X5R-CERM
0201
10%
C17571
2
16V
0201
X5R-CERM
10%
0.1UF
PLACE_NEAR=U1100.AD13:1.2MM
C17491
2 6.3VX5R-CERM-1
603
20%
22UF
C17481
2
PLACE_NEAR=U1100.P23:1MM
6.3V
X5R-CERM-1
22UF
20%
603
C1747 1
2
PLACE_NEAR=U1100.AC19:1MM
16V
X5R-CERM
0.1UF
10%
0201
C17461
2
PLACE_NEAR=U1100.AD16:1MM
X6S-CERM
6.3V
1UF
0201
20%
C17451
2
6.3V
20%
POLY-TANT
0805
47UF
C17441
2
6.3V
CERM
1UF
10%
402
PLACE_NEAR=U1100.N12:1MM
C17431
2
PLACE_NEAR=U1100.AB10:1MM
0.1UF
X5R-CERM
16V
0201
10%
C17421
2
16V
PLACE_NEAR=U1100.J11:1MM
0.1UF
X5R-CERM
0201
10%
C17411
2
16V
0.1UF
10%
X5R-CERM
PLACE_NEAR=U1100.L24:1MM
0201
C17401
2
PLACE_NEAR=U1100.K22:1MM
16V
0.1UF
X5R-CERM
0201
10%
C17391
2
20%
6.3V
X6S-CERM
0201
1UF
PLACE_NEAR=U1100.L17:1.4MM
C17371
2
PLACE_NEAR=U1100.L17:2.1MM
6.3V
X6S-CERM
0201
20%
1UF
C17381
26.3VPOLY-TANT
47UF
0805
20%
C17361
2 16V
0.1UF
X5R-CERM
0201
10%
C17341
2
0.1UF
X5R-CERM
0201
16V
10%
C17351
2
10%
16V
0201
X5R-CERM
0.1UF
C17301
2 16V
0201
10%
X5R-CERM
0.1UF
C17311
2 16V
0201
X5R-CERM
10%
0.1UF
C17321
2 16V
10%
0.1UF
0201
X5R-CERM
C17331
2
25V
5%
12PF
0201
NP0-C0G
C1754 1
2
25V
0201
NP0-C0G
5%
12PF
C1755 1
2
3.0PF
0201
NP0-C0G
25V
+/-0.1PF
C1756 1
2
25V
NP0-C0G
12PF
5%
0201
C1753 1
2
25V
0201
NP0-C0G
5%
12PF
C17521
2
25V
12PF
0201
NP0-C0G
5%
C1751 1
2
0201
25V
NP0-C0G
12PF
5%
C1750 1
2
PLACE_NEAR=U1100.AC20:1MM
402
10V
0.1UF
CERM
20%
C1723 1
2
PLACE_NEAR=U1100.AD13:1MM
6.3V
1UF
20%
X6S-CERM
0201
C17171
2
PLACE_NEAR=U1100.W22:1MM
16V
10%
X5R-CERM
0.1UF
0201
C17161
2
PLACE_NEAR=U1100.AD16:1MM
16V
0201
X5R-CERM
10%
0.1UF
C17151
2
16 
16 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NEED TO CONNECT TO VCCST, *STG POWER LOGIC
(OD)
VCC_OBS_AB
HOOK2
TDO
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
HOOK1
RESET#/HOOK6
SDA
ITPCLK#/HOOK5
VCC_OBS_CD
ITPCLK/HOOK4
OBSDATA_D3
OBSDATA_B2
518S0847
TCK1
DBR#/HOOK7
TRSTn
TCK0
OBSFN_A1
OBSFN_A0
OBSDATA_A1
TMS
 support chipset debug.
OBSFN_C1
 Use with 921-0133 Adapter Flex to
NOTE: This is not the standard XDP pinout.
The PDG puts them on a secondary XDP connector that is only needed in some PCH debugging situation.
These signals do not connect to the Primary (Merged) XDP connector in this architecture.
OBSDATA_A0
OBSDATA_B3
OBSDATA_D0
OBSFN_B0
OBSDATA_B0
OBSFN_B1
SCL
OBSDATA_D2
Unused GPIOs have TPs.
Non-XDP Signals
TDI
OBSDATA_D1
LAST CHANGE: Mon Jun 15 22:04:28 2015
DESIGN: X502/MLB
PCH/XDP Signals
PCH XDP Signals
OBSFN_C0
OBSDATA_B1
OBSFN_D1
HOOK0
OBSDATA_C3
OBSDATA_C2
OBSDATA_C1
OBSDATA_C0
Extra BPM Testpoints
ROUTE IN STAR TOPOLOGY FROM XDP CONNECTOR.
PROPER WAY TO TERMINATE?
OBSFN_D0
OBSDATA_A3
HOOK3
XDP_PIN_1
OBSDATA_A2
(STRAP TO PCH)
They are listed here to show their secondary XDP functions and to provide test points for signals that are not used elsewhere.
XDP_PRESENT#
Primary / Merged (CPU/PCH) Micro2-XDP
PULL CFG<3> LOW
WHEN XDP PRESENT
PLACE_NEAR=U0500.BN28:2.54MM
PLACE_NEAR=U0500.E8:2.54MM
18 OF 121
NC_ITPXDP_CLK100MP
NC_ITPXDP_CLK100MN
PP1V0_S0SW6 8 11 110 
PP3V3_SUS18 73 110 
PP3V3_SUS18 73 110 
PP3V3_SUS18 73 110 
PP1V0_SUS110 
18 OF 145
10.0.0
051-00647
dvt-fab10
CPU_CFG<13>
CPU_CFG<12>
CPU_CFG<15>
CPU_CFG<14>
XDP_PCH_TCK
PM_SYSRST_L
CPU_CFG<0>
PCH_JTAGX
CPU_CFG<1>
XDP_PCH_TCK
CPU_CFG<8>
XDP_CPU_TRST_L
XDP_CPU_TDO
XDP_PCH_TRST_L
XDP_PCH_OBSDATA_D3
XDP_PCH_TMS
XDP_CPU_TDO
XDP_PCH_OBSDATA_C2
XDP_PCH_OBSDATA_A3
XDP_PCH_OBSDATA_D2
XDP_PCH_OBSDATA_A2
XDP_PCH_OBSDATA_C0
XDP_PCH_TDO
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<3>
XDP_BPM_L<2>
XDP_CPU_TDI
XDP_PCH_OBSFN_C1
XDP_PCH_OBSDATA_D0
XDP_PCH_OBSDATA_C1
XDP_PCH_TDI
XDP_PCH_OBSDATA_C3
CPU_CFG<11>
XDP_CPU_TMS
CPU_CFG<9>
CPU_CFG<10>
XDP_CPU_TCK
CPU_CFG<4>
CPU_CFG<6>
XDP_DBRESET_L
CPU_CFG<2>
CPU_CFG<3>
XDP_CPU_PWRBTN_L
XDP_PM_RSMRST_L
XDP_CPU_TCK
CPU_CFG<7>
XDP_CPU_PRDY_L
XDP_PCH_OBSDATA_B0
XDP_PCH_OBSDATA_D1
ITP_PMODE
CPU_CFG<19>
CPU_CFG<18>
SPI_IO<2>
SPI_MOSI_R_CONN
XDP_PCH_TDO
SPI_IO2_STRAP_L
XDP_PCH_TDI
CPU_CFG<5>
CPU_CFG<16>
CPU_CFG<17>
XDP_PRESENT_L
XDP_PCH_TRST_L
XDP_PCH_TMS
SPI_MOSI_R
PM_PWRBTN_L
PM_RSMRST_L
XDP_CPU_PREQ_L
XDP_PRESENT_CPU
CPU/PCH Merged XDP
BOM_COST_GROUP=DEBUG
SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/25/2016
6 
6 
6 
6 
115 18 6 
6 
NOSTUFF
NO_XNET_CONNECTION
PLACE_NEAR=U1830.4:2.54MM
49.9
1%
201MF
1/20W
R1832
1 2
XDP:YES
10%
0201
X5R-CERM
10V
0.1UF
C18301
2
XDP:YES
SOT891
74AUP1G07GF
U1830
2
3
1 5
6
4
115 113 12 
115 113 12 
MF
1/20W
5%
1K
201
XDP:YES
PLACE_NEAR=J1800.48:2.54MM
R18041
2
57 13 
PLACE_NEAR=U1100.AM23:2.54MM
XDP:YES
5% 1/20W
1K
MF 201
R1803 1 2
NOSTUFF
51
MF 2015% 1/20W
R1898 2 1
TP-P6 TP1801
1
TP-P6 TP1800
16 
6 
57 13 
13 
0
MF
5%
1/20W
XDP:YES
0201
R1806
1 2 115 46 12 
14 
14 
14 
14 
14 
14 
14 
14 
14 
TP-P6 TP1880
1
TP-P6 TP1879
1
TP-P6 TP1878
1
TP-P6 TP1877
1
TP-P6 TP1881
1
TP-P6 TP1876
1
TP-P6 TP1875
1
TP-P6 TP1874
1
TP-P6 TP1873
1
TP-P6 TP1872
1
TP-P6 TP1871
1
TP-P6 TP1870
1
73 
XDP:YES
MF
5%
1/20W
100K
201
R18501
2
PLACE_NEAR=U1100.AM10:3MM
XDP:YES
MF5%
10
1/20W 201
R1802 1 2 MF201
1/20W
1K
5%
R18301
2
115 13 6 
PLACE_NEAR=U1830.4:7.54MM
NO_XNET_CONNECTION
1.5K
MF XDP:YES 5% 1/20W201
R1831
1 2
PLACE_NEAR=J1800.57:2.54MM
XDP:YES
0
MF 02015% 1/20W
R1824 1 2
XDP:YESPLACE_NEAR=J1800.55:2.54MM 1/20W
0
MF 02015%
R1823 1 2
XDP:YES
0
MF 0201PLACE_NEAR=J1800.53:2.54MM5% 1/20W
R1822 1 2
XDP:YES
0
MF5% 1/20W 0201PLACE_NEAR=J1800.51:2.54MM
R1821 1 2
115 73 46 12 
201
5%
1/20W
MF
NO_XNET_CONNECTION
1K
XDP:YES
R18011
2
6 
M-ST-SM1
DF40RC-60DP-0.4V
XDP_CONN
J1800
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
4142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
1/20W5% 201MF
51
NOSTUFF
PLACE_NEAR=U1100.AG6:28MM
R1897 2 1
CERM-X5R
PLACE_NEAR=J1800.47:28MM
10%
0201
6.3V
0.1UF
XDP:YES
C18061
2
XDP:YES
0201
CERM-X5R
PLACE_NEAR=J1800.42:28MM
6.3V
10%
0.1UF
C1804 1
2
115 13 6 
115 13 6 
PLACE_NEAR=J1800.44:28MM
XDP:YES
10%
6.3V
0.1UF
0201
CERM-X5R
C1800 1
2
14 
6 
13 
14 
XDP:YES
0.1UF
CERM-X5R
10%
6.3V
0201
PLACE_NEAR=J1800.43:28MM
C18011
2
115 18 6 
115 6 
115 6 
20 0
XDP:YES
5% MF1/20W 0201
PLACE_NEAR=J1800.58:28MM
R1835 1 2
XDP:YES
PLACE_NEAR=U1100.AF6:28MM
51
MF 2015% 1/20W
R1890 2 1
PLACE_NEAR=U1100.AF5:28MM
51
XDP:YES
MF5% 1/20W 201
R1891 2 1
PLACE_NEAR=U1100.AG5:28MM 1/20W
XDP:YES
51
MF 2015%
R1892 2 1
PLACE_NEAR=U0500.BT28:28MM
XDP:YES
51
1/20W MF 2015%
R1810 2 1
115 18 13 
TP-P6 TP1802
1
TP-P6 TP1803
1
6 
6 
6 
6 
6 
6 
6 
PLACE_NEAR=U1100.AF12:3.8MM 201
1K
5%
XDP:YES
1/20W MF
R1800 1 2
51
PLACE_NEAR=U0500.BR28:28MM
XDP:YES
MF 2015% 1/20W
R1813 2 1
115 18 13 
115 18 13 
6 
115 18 13 
48 46 
6 
6 
6 
6 
115 6 
6 
6 
115 18 13 
18 
115 18 13 
115 18 6 
115 18 13 
115 18 13 
115 18 6 
18 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
OUT
IN
NCNC
GND
VCC
NCNC
YA
IN
IN
IN
NC
NC
TP
TPIN
IN
NC
NC
NC
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
OUT
OUT
IN
IN
IN
BI
BI
IN
BI
BI
IN
OUT
OUT
OUT
OUT
TP
TP
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
PCIe Wake Muxing
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
SEL OUTPUT
H AP_S0IX_WAKE_L (B1)
***** Circuit does not support HDA voltage >3.3V.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
PCH ME Disable Strap 
SMC controls strap enable to allow in-field control of strap setting.
PCH IPD = 9-50k
L PCIE_WAKE_L (B0)
NOTE: 30 PPM or better required for SKL PCH
System 32kHz / 12MHz / 24MHz Clock Generator
19 OF 121
MIN_LINE_WIDTH=0.2000
VOLTAGE=2.9V
MIN_NECK_WIDTH=0.1200
PP1V8_S0
NC_PPVIOE_SSDCLK
NC_SYSCLK_CLK24M_SSD 20 
PP3V3_S5110 
NC_PPVIOE_CAMCLK
NC_SYSCLK_CLK24M_CAMERA 20 
19 OF 145
10.0.0
051-00647
dvt-fab10
PP2V9_SYSCLK
SYSCLK_CLK32K_PCH
SYSCLK_CLK24M_X1
SPI_DESCRIPTOR_OVERRIDE_L
HDA_SDOUT_R
AP_PCIE_WAKE_L PCIE_WAKE_L
AP_S0IX_WAKE_L
SPI_DESCRIPTOR_OVERRIDE
SYSCLK_CLK24M_X2
PPVDD_U1900_RC
SMC_CLK12M_EN SYSCLK_CLK24M_PCH
SYSCLK_CLK32K_CAMERA_BT_AP
AP_S0IX_WAKE_SEL
SYSCLK_CLK24M_X2_R
PPVRTC_U1900_RC
PPVIO_32K_B_RC
PPVIO_VIOE_A_RC
SYSCLK_CLK12M_SMC
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=X363_SAKKOC SYNC_DATE=04/29/2016
Chipset Support 1
CRITICAL
SC70
PI5A3157BC6E
U1910
4 3
1
2
6
5
24MHZ-10PPM-8PF-40OHM
CRITICAL
2.5X2.0MM-SM
Y1900
2
4
1
3
0201
CRITICAL
50V
CER-C0G
9.5PF
+/-0.1PF
C1908
1 2
CRITICAL
9.5PF
CER-C0G
+/-0.1PF
50V
0201
C1907
1 2
STQFN
SLG3AP3444
U1900
7
3
6
16
10
13
4 9 14 18
8
1
12
2
5
15
17
11
20
19
20 
20 
12 
12 
12 
0201
6.3V
0.1UF
CERM-X5R
10%
C1910 1
25%
1/20W
201
MF
100K
R19101
2
35 
SOT23
DMP31D0U
Q1930
3
1
2
109 
BYPASS=U1900.17:18:5MM
0201
20%
6.3V
X5R-CERM
2.2UF
C19001
2
46 
5%
1/20W
NO STUFF
1M
201
MF
R19011
2
0201
MF
5%
0
1/20W
R1900
1 2
46 
13 
1/20W
201
5%
MF
1K
R19301
2
20 
113 
113 
20 
20 
20 
113 
20 
20 
20 
46 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
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SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
SEL
B0
GND
B1
0
1
A
VCC
VER 1
VIO_32K_B
VIOE_24M_A
VIOE_24M_B
X2
X1
VD
D
VIOE_24M_C
VR
TC
12M
VOUT
GND
OE_12M
32.768K_A
24M_A
24M_B
24M_C
32.768K_BIN
IN
IN
OUT
OUTIN
DS
G
IN
IN
IN
OUT
J80 & J80G Display Port DDPB, DDPC,DDPD
GreenCLK VIOEs
NC ALIASES
Unbuffered
Power State Debug LEDs (For development only)
Buffered
Platform Reset Connections
DPMUX Connections
NC ALIASES 3
Scrub for Layout Optimization
UNUSED NETS in J80
LDO
F = 1.7MHz
PCIE CLKREQS
SIGNAL ALIASES
F = 1.7MHz
RC Filter -3dB @ 240KHz
F = 500kHz
LDO
NC ALIASES 2
GREENCLK CLOCK OUT ALIASES
INTEL SKL DEBUG
20 OF 121
NC_TCON_RESET_L15 
TBT_T_PCI_RESET_L 101 
NC_PCH_DDPD_CTRLCLK15 
TBT_X_PCI_RESET_L 27 29 
SOC_SWD_CLK15 42 
PP3V3_S0110 
SOC_UART_R2D 42 
NC_PCH_CLK32K_RTCX2
PP1V8_S4
LPC_CLK24M_DPMUX_UC_R12 20 
PCH_JTAGX13 
PP3V3_G3H
PP3V3_G3H
MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
SSD_CLKREQ_L_R12 
TBT_T_CLKREQ_L_R12 
NC_PCH_STRP_TLSCONF15 
NC_PCH_STRP_ESPI15 
NC_PPVIOE_CAMCLK 19 
NC_PPVIOE_SSDCLK 19 
NC_PCH_CLK24M_XTALOUT
SYSCLK_CLK24M_PCH
PP3V3_S012 14 20 73 110 
SOC_UART_D2R 42 
NC_TBT_W_PLUG_EVENT_L15 
NC_BKLT_FAULT_INT_L15 
NC_SDCONN_STATE_CHANGE15 
NC_ENET_MEDIA_SENSE15 
NC_AUD_I2C_INT_L15 
NC_AUD_IPHS_SWITCH_EN15 
NC_AUD_IP_PERIPHERAL_DET15 
TBT_X_CLKREQ_L_R12 
NC_PCH_SLP_LAN_L12 
NC_PCH_BSSB_CLK15 
PP3V3_S5110 
BKLT_PWM_MLB2TCON89 
DPMUX_UC_IRQ15 
NC_PCH_GPD712 
NC_PCH_DDPB_CTRLCLK15 
NC_PCH_SLP_A_L12 
NC_PCH_TP1_AG913 
NC_ISOLATE_CPU_MEM_L15 
NC_CAMERA_RESET_L15 
LPC_CLK24M_DPMUX_UC_R12 20 
NC_ENET_LOW_PWR15 
NC_PCH_STRP_BSSB_SEL_GPIO13 
NC_PCH_BSSB_DATA15 
NC_PCH_CAM_EXT_BOOT_L14 
NC_PCH_CAM_RESET14 
NC_SYSCLK_CLK24M_SSD19 
NC_I2C_UPC_SCL15 
NC_SYSCLK_CLK24M_CAMERA19 
NC_I2C_UPC_SDA15 
NC_PCH_TP1_AH913 
NC_PCH_DDPC_CTRLCLK15 
AP_CLKREQ_L_R12 
SYSCLK_CLK32K_PCH
NC_WOL_EN14 
LPC_CLK24M_DPMUX_UC_R
PCH_DISPA_SDI 5 
PP3V3_S0 12 14 20 73 110 
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1750
PP1V8_S4
MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
PP1V0_SUS
ALS_SOC_UART_R2D15 
ALS_SOC_UART_D2R15 
NC_HDD_PWR_EN14 
PCH_DISPA_BCLK 5 
NC_PCH_LANPHYPC12 
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1750
PCH_SOC_DBELL_L15 37 
SOC_PCH_DBELL_L15 38 
NC_SDCONN_OC_L15 
MIN_NECK_WIDTH=0.1750
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.0V
NC_PCH_PME_L12 
PCH_DISPA_SDO 5 
NC_SPKR_ID115 
20 OF 145
10.0.0
051-00647
dvt-fab10
MAKE_BASE=TRUE
NC_SPKR_ID1
MAKE_BASE=TRUE
TP_PCH_DMIC_CLK1
TP_PCH_DMIC_DATA1
TP_PCH_DMIC_CLK0
TP_PCH_DMIC_DATA0
TBT_X_CLKREQ_L
LPC_CLK24M_DPMUX_UC_R
MAKE_BASE=TRUE
TBT_X_PCI_RESET_L
MAKE_BASE=TRUE
SSD_CLKREQ_L
SMC_LRESET_L
AP_RESET_L
PCH_DISPA_SDI
MAKE_BASE=TRUE
PPVRTC_U1900_RC
MAKE_BASE=TRUE
TBT_X_CLKREQ_L_R
PM_SLP_S0_L
MAKE_BASE=TRUE
NC_PCH_CLK24M_XTALOUT
PCH_DDPC_CTRLDATA
PCH_DDPD_CTRLDATA
PCH_DDPB_CTRLDATA
TBT_W_USB_PWR_EN
TBT_W_CIO_PWR_EN
TBT_W_CLKREQ_L
CAMERA_CLKREQ_L
ENETSD_CLKREQ_L
SSD_RESET_L
MAKE_BASE=TRUE
NC_TBT_W_PLUG_EVENT_L
MAKE_BASE=TRUE
NC_SDCONN_OC_L
MAKE_BASE=TRUE
NC_BKLT_FAULT_INT_L
NC_SDCONN_STATE_CHANGE
MAKE_BASE=TRUE
NC_ENET_MEDIA_SENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_AUD_I2C_INT_L
NC_AUD_IPHS_SWITCH_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_AUD_IP_PERIPHERAL_DET
NC_PCH_SLP_A_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_GPD7
NC_PCH_DDPD_CTRLCLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_CLKOUT_PCIE_13_N
PLT_RST_L_BUF
PLT_RST_L
DBGLED_S5BKLT_PWM_MLB2TCON
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ALS_SOC_UART_D2R
AP_CLKREQ_L
PLT_RST_L
DPMUX_UC_IRQ
MAKE_BASE=TRUE
PLT_RST_L
LPC_CLK24M_DPMUX_UC
DPMUX_LRESET_L
MAKE_BASE=TRUE
NC_PCH_LANPHYPC
MAKE_BASE=TRUE
NC_ISOLATE_CPU_MEM_L
NC_PCH_SLP_LAN_L
MAKE_BASE=TRUE
NC_CAMERA_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SYSCLK_CLK24M_CAMERA
NC_WOL_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_ENET_LOW_PWR
MAKE_BASE=TRUE
NC_PCH_CAM_RESET
MAKE_BASE=TRUE
SSD_CLKREQ_L_R
DBGLED_S0DBGLED_S0I3
DBGLED_S0I3_D
PM_SLP_S3_L
DBGLED_S3DBGLED_S4
DBGLED_S3_D
PM_SLP_S4_L
DBGLED_S4_D
PM_SLP_S5_L
MAKE_BASE=TRUE
NC_I2C_UPC_SDA
NC_I2C_UPC_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_CAM_EXT_BOOT_L
MAKE_BASE=TRUE
NC_TCON_RESET_L
NC_PCH_DRAM_RESET_L
MAKE_BASE=TRUE
NC_PCH_TP1_AH9
MAKE_BASE=TRUE
NC_PCH_DDPB_CTRLCLK
MAKE_BASE=TRUE
NC_CLKOUT_PCIE_13_N
NC_CLKOUT_PCIE_13_P
MAKE_BASE=TRUE
NC_PCH_TP1_AG9
MAKE_BASE=TRUE
NC_PCH_BSSB_DATA
MAKE_BASE=TRUE
ALS_SOC_UART_R2D
MAKE_BASE=TRUE
PCH_JTAGX
MAKE_BASE=TRUE
TBT_T_CLKREQ_L
NC_HDD_PWR_EN
NC_PCH_DDPC_CTRLCLK
MAKE_BASE=TRUE
AP_CLKREQ_L_R
MAKE_BASE=TRUE
TBT_T_CLKREQ_L_R
MAKE_BASE=TRUE
NC_PCH_CLK32K_RTCX2
MAKE_BASE=TRUE
NC_PCH_STRP_TLSCONF
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SYSCLK_CLK24M_SSD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCH_STRP_BSSB_SEL_GPIO
NC_PCH_STRP_ESPI
MAKE_BASE=TRUE
SYSCLK_CLK32K_OSC_SOCSYSCLK_CLK32K_OSC_Y1901
DBGLED_S0_D
PCH_DISPA_SDO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYSCLK_CLK24M_PCH
TBT_T_PCI_RESET_L
MAKE_BASE=TRUE
PPVIO_32K_B_RC
PPVDD_U1900_RC
SOC_PMU_CLK_32K
SYSCLK_CLK32K_WIFIBT
PCH_DISPA_BCLK
MAKE_BASE=TRUE
SYSCLK_CLK32K_CAMERA_BT_AP
MAKE_BASE=TRUE
NC_CLKOUT_PCIE_13_P
MAKE_BASE=TRUE
NC_PCH_PME_L
NC_PPVIOE_CAMCLK
MAKE_BASE=TRUE
SOC_CLK_32K
PPVCC_RTC_OSC
MAKE_BASE=TRUE
NC_PPVIOE_SSDCLK
TBT_W_PCI_RESET_L
SOC_SWD_CLK
MAKE_BASE=TRUE
SOC_PCH_DBELL_L
MAKE_BASE=TRUE
SOC_UART_R2D
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SOC_UART_D2R
PPVIO_VIOE_A_RC
MAKE_BASE=TRUE
PCH_SOC_DBELL_L
NC_PCH_DRAM_RESET_L
NC_PCH_BSSB_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYSCLK_CLK32K_PCH
BOM_COST_GROUP=CPU & CHIPSET
Chipset Support 2
SYNC_MASTER=X363_SAKKOC SYNC_DATE=01/14/2016
SM
P2MM
PP2003
1
SM
P2MM
PP2002
1
P2MM
SM
PP2001
1
SM
P2MM
PP2000
1
6.3V
0201
X5R
10%
0.1UF
C20051
2CERM-X5R
0201
6.3V
10%
0.1UF
C20111
2
3.3
MF
201
1/20W
5%
R2014
1 2
201
1/20W
5%
3.3
MF
R2015
1 2
6.3V
20%
1.0UF
X5R
0201-1
C2009 1
2
0.1UF
6.3V
0201
X5R
10%
C20081
2
10%
6.3V
0201
CERM-X5R
0.1UF
C20071
2
1.0UF
0201-1
20%
X5R
6.3V
C2010 1
2
109 20 
109 20 
6.3V
CERM-X5R
0201
0.1UF
BYPASS=U1900.12:18:5MM
10%
C20011
2
0.1UF
0201
10%
CERM-X5R
6.3V
C20021
2
MF
5%
3.3
1/20W
201
R2012
1 2
MF
201
5%
3.3
1/20W
R2013
1 2
0201-1
6.3V
20%
1.0UF
X5R
C2003 1
2
0.1UF
0201
6.3V
10%
CERM-X5R
BYPASS=U1900.02:18:5MM
C20001
2
0.1UF
6.3V
0201
CERM-X5R
10%
C20041
2
1.0UF
6.3V
0201-1
20%
X5R
C2006 1
2
109 20 
110 
37 
35 
PLACE_NEAR=U3900.AA22:3mm
NOSTUFF
1/20W
MF
5%
0
0201
R2026
1 2
5%
MF
1/20W
0
0201
R2017
1 2
1/20W
NOSTUFF
MF
5%
0201
0
R2018
1 2
32.768KHZ-25PPM-15PF-5.5V
2.50X2.00-SM-COMBO
Y2001
1
2
3
4
0201
X5R-CERM
10V
10%
0.01UF
C20151
2
5%
MF
201
3.3
1/20W
R2016
1 2
0.1UF
CERM-X5R
0201
10%
6.3V
C20141
20201-1
X5R
6.3V
1.0UF
20%
C2013 1
2
109 20 
113 12 
89 
201
1/20W
MF
5%
100K
R20891
2
89 
201
22
MF
1/20W
5%
R2007
1 2
114 35 20 12 
100K
1/20W 201MF5%
R200612
12 
12 
12 
12 
12 
201MF1/20W5%
100K R200512
2.2K
201 MF1/20W5%
R2052 1 2
19 
1/20W
1K
5% MF 201
R2087 1 2
1K
2015% MF1/20W
R2086 1 2
1/20W 201MF5%
1KR2085 1 2
1/20W
1K
201MF5%
R2084 1 2
1/20W5% 201
47K
MF
R2080 1 2
1/20W 201
47K
5% MF
R2081 1 2
5% 201MF1/20W
47KR2083 1 2
5%
47K
1/20W MF 201
R2082 1 2
1/20W
100K
5% 201MF
R200412
MF1/20W5%NOSTUFF
10K
201
R200312
2011/20W5% MF
100K R200212
MF1/20W5% 201
100K R200112
2.2K
201 MF1/20W5%
R2051 1 2
2.2K
201 MF1/20W5%
R2050 1 2
0
0201
MF
1/20W
5%
R2043
1 2 41 37 
12 
12 19 
19 
DBGLED
SILK_PART=S0I3_ON
PLACE_SIDE=BOTTOM
0402
GRN-90MCD-5MA-2.85V
D2093A
K
DMN5L06VK-7
SOT563
DBGLED
Q2091
6
2 1
DBGLED
MF
1/20W
5%
20K
201
R20951
2
DMN5L06VK-7
SOT563
DBGLED
Q2091
3
5 4
1/20W
5%
201
20K
MF
DBGLED
R20931
2
DBGLED
1/20W
5%
201
MF
20K
R20921
2
DBGLED
MF
1/20W
20K
201
5%
R20911
2
PLACE_SIDE=BOTTOM
SILK_PART=S0_ON
DBGLED
0402
GRN-90MCD-5MA-2.85V
D2095A
K
DBGLED
DMN5L06VK-7
SOT563
Q2090
3
5 4
SILK_PART=S3_ON
PLACE_SIDE=BOTTOM
DBGLED
0402
GRN-90MCD-5MA-2.85V
D2092A
K
SOT563
DMN5L06VK-7
DBGLED
Q2090
6
2 1
SILK_PART=STBY_ON
PLACE_SIDE=BOTTOM
DBGLED
0402
GRN-90MCD-5MA-2.85V
D2091A
K
MF
1/20W
5%
20K
201
DBGLED
R20901
2
73 46 12 
73 70 46 43 12 
114 101 89 76 73 70 46 27 12 
70 46 12 
PLACE_SIDE=BOTTOM
0402
SILK_PART=S5_ON
GRN-90MCD-5MA-2.85V
DBGLED
D2090A
K
12 
2015% 1/20W
100K
MF
R200012114 35 20 12 
PLACE_NEAR=R2001:5MM
NOSTUFF
1/20W
0201
0
MF
5%
R20731
2
114 
35 20 12 
1/20W
1%
MF
4.99K
PLACE_NEAR=U2071:5MM
201
R20721
2
1/20W
5%
100K
MF
201
R20701
2
CRITICAL
SC70-HF
MC74VHC1G08
U2071
3
2
1
4
5
0201
X5R-CERM
10%
16V
0.1UF
C2071 1
2
13 
13 
13 
13 
27 
14 
115 87 
46 
114 36 35 15 
13 
19 
15 
15 
15 
115 114 87 14 
20 12 
114 76 
42 
35 
89 
20 12 
20 12 
20 12 
42 
18 
101 
115 
13 
14 
19 
19 
13 
20 12 
15 
15 
15 
19 
20 12 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
PP
PP
PP
PP
IN
IN
IN
IN
OUT
OUT
GND
EN/DIS OUT
VCC
IN
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUTIN
IN
G S
D
VER 3
G S
D
VER 3
G S
D
VER 3
G S
D
VER 3
IN
IN
IN
IN
OUT
IN
IN
CPU-Based Margining
 DDR3L (1.35V) 6.99mV per step VRef Dividers
NOTE: CPU DAC output step sizes:
 DDR3 (1.5V) 7.70mV per step
 LPDDR3 (1.2V) ?.??mV per step
051-00647
dvt-fab10
10.0.0
21 OF 121
22 OF 145
PP0V6_S3_MEM_VREFDQ_A 109 
MIN_NECK_WIDTH=0.1450
MIN_LINE_WIDTH=0.3000
PP0V6_S3_MEM_VREFCA_A 109 
MIN_NECK_WIDTH=0.1450
MIN_LINE_WIDTH=0.3000
PP0V6_S3_MEM_VREFDQ_B 109 
MIN_LINE_WIDTH=0.3000
MIN_NECK_WIDTH=0.2000
PP1V2_S3 109 
MEM_VREFDQ_A_RC
MEM_VREFDQ_B_RC
MEM_VREFCA_A_RC
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
CPU_DIMM_VREFCA
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
LPDDR3 VREF MARGINING
BOM_COST_GROUP=DRAM
0.022UF
6.3V
10%
0201
X5R-CERM
C22201
2
24.9
201
MF
1/20W
1%
R2220
1 2
PLACE_NEAR=R2221.2:1mm
1/20W
MF
201
1%
8.2K
R22221
2
201
1/20W
MF
10
1%
R2223
1 2
1/20W
8.2K
MF
201
1%
R22411
2
6.3V
X5R-CERM
0201
0.022UF
10%
C22401
2
201
MF
1%
1/20W
10
R2243
1 2
201
MF
1/20W
1%
24.9
R2240
1 2
PLACE_NEAR=R2241.2:1mm
201
1%
8.2K
1/20W
MF
R22421
2
201
1%
8.2K
1/20W
MF
R22611
2
10%
0.022UF
0201
X5R-CERM
6.3V
C22601
2
0201
5.1
1%
1/20W
MF
R2263
1 2
201
MF
1/20W
1%
24.9
R2260
1 2
201
1%
8.2K
1/20W
MF
PLACE_NEAR=R2261.2:1mm
R22621
2
201
MF
1%
8.2K
1/20W
R22211
2
7 
7 
7 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
10uF caps are shared between DRAM.
Distribute evenly.
LPDDR3 CHANNEL A (0-31)
PLACEMENT_NOTE:
22 OF 121
dvt-fab10
10.0.0
051-00647
23 OF 145
PP1V2_S322 23 24 25 109 116 
PP1V8_S3_MEM22 23 24 25 109 116 
MEM_A_DQ<9>
MEM_A_DQ<0>MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<16>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<21>
MEM_A_DQ<17>
MEM_A_DQ<24>
MEM_A_DQ<22>
PP1V2_S322 23 24 25 109 116 
MEM_A_DQ<26>
MEM_A_DQS_P<1>
MEM_A_DQ<8>
MEM_A_DQS_N<0>
MEM_A_DQ<23>
MEM_A_DQS_P<3>
MEM_A_DQS_P<0>
MEM_A_DQS_P<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<2>
MEM_A_DQS_N<1>
MEM_A_DQ<27>
MEM_A_DQ<30>
MEM_A_DQ<25>
MEM_A_DQ<28>
MEM_A_DQ<31>
MEM_A_DQ<20>
MEM_A_DQ<2>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<1>
MEM_A_DQ<3>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<13>
MEM_A_DQ<12>
PP1V2_S322 23 24 25 109 
MEM_A_DQ<29>
PP1V2_S322 23 24 25 109 
PP1V8_S3_MEM22 23 24 25 109 116 
PP1V2_S322 23 24 25 109 116 
PP1V2_S322 23 24 25 109 116 
MEM_A_ZQ<0>
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
MEM_A_CLK_N<0>
MEM_A_CS_L<0>
MEM_A_CAA<7>
MEM_A_CLK_P<0>
MEM_A_CKE<1>
MEM_A_CAA<8>
MEM_A_CAA<9>
MEM_A_CAA<6>
MEM_A_CAA<2>
MEM_A_CS_L<1>
MEM_A_ODT<0>
MEM_A_CKE<0>
MEM_A_CAA<1>
MEM_A_ZQ<1>
MEM_A_CAA<0>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_CAA<5>
LPDDR3 DRAM Channel A (0-31)
BOM_COST_GROUP=DRAM
SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015
112 
ED
FA
23
2A
1M
A-
GD
-F
OMIT_TABLE
CRITICAL
LPDDR3-16GB
FBGA
U2300
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
OMIT_TABLE
CRITICAL
ED
FA
23
2A
1M
A-
GD
-F
LPDDR3-16GB
FBGA
U2300
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J2
J3
K3
K4
L3
L4
L8
G8
P8
D8
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
L11
L10
G11
G10
P11
P10
D11
D10
C4
K9
R3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
J8
H4
J11
B3
B4
201
MF
1/20W
243
1%
R23011
2
243
1%
1/20W
MF
201
R23001
2
112 
26 23 7 
26 23 7 
26 23 7 
113 26 7 
113 26 7 
26 7 
26 7 
113 26 7 
113 26 7 
112 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
10%
6.3V
0.047UF
201
X5R
C2340 1
2 6.3V
10%
201
0.047UF
X5R
C23411
2
112 
10V
X5R-CERM
0201-1
1.0UF
20%
C23301
2 10VX5R-CERM
0201-1
1.0UF
20%
C23311
2 X6S-CERM
0402-2
4V
10UF
20%
C23321
2
10UF
4V
X6S-CERM
0402-2
20%
C23331
2
0402-2
4V
10UF
20%
X6S-CERM
C23231
2 4VX6S-CERM
0402-2
10UF
20%
C23241
2
112 
10V
X5R-CERM
0201-1
1.0UF
20%
C23221
210VX5R-CERM
1.0UF
20%
0201-1
C23211
2
1.0UF
20%
X5R-CERM
0201-1
10V
C23201
2
X6S-CERM
0402-2
4V
10UF
20%
C23121
210V
0201-1
X5R-CERM
1.0UF
20%
C23111
210VX5R-CERM
0201-1
20%
1.0UF
C23101
2
112 
10V
0201-1
1.0UF
20%
X5R-CERM
C23051
2
10%
16V
0.1UF
X5R-CERM
0201
C23011
2 10VX5R-CERM
0201-1
1.0UF
20%
C23041
210VX5R-CERM
0201-1
1.0UF
20%
C23031
2
0.1UF
16V
10%
X5R-CERM
0201
C23001
2
112 
10V
0201-1
1.0UF
X5R-CERM
20%
C23021
2
10UF
4V
20%
0402-2
X6S-CERM
C23071
2X6S-CERM
4V
20%
0402-2
10UF
C23061
2
112 
112 
109 23 
109 23 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
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2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
(2 OF 2)
VDD1
VDD2
VSSQ
VSSCA
VSS
VDDQ
VDDCA
(1 OF 2)
NU
CS1*
CS0*
ZQ1
ZQ0
VREFDQ
VREFCA
ODT
NC
DQS3_T
DQS3_C
DQS2_T
DQS2_C
DQS1_T
DQS1_C
DQS0_T
DQS0_C
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DM3
DM2
DM0
CKE0
CA9
CA8
CA7
CA6
CA4
CA3
CA2
CA1
CA0
DM1
CK_C
CKE1
CK_T
CA5
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
LPDDR3 CHANNEL A (32-63)
PLACEMENT_NOTE:
10uF caps are shared between DRAM.
PLACEMENT_NOTE:
Distribute evenly.Distribute evenly.
10uF caps are shared between DRAM.
dvt-fab10
10.0.0
051-00647
23 OF 121
24 OF 145
PP1V2_S322 23 24 25 109 
PP1V8_S3_MEM22 23 24 25 109 116 
PP1V2_S322 23 24 25 109 
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<41>
MEM_A_DQ<47>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<40>
MEM_A_DQ<49>
MEM_A_DQ<53>
MEM_A_DQ<51>
MEM_A_DQ<55>
MEM_A_DQ<52>
MEM_A_DQ<48>
MEM_A_DQ<50>
MEM_A_DQ<34>
MEM_A_DQ<37>
MEM_A_DQ<39>
MEM_A_DQ<62>
MEM_A_DQ<59>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<56>
MEM_A_DQ<63>
MEM_A_DQ<60>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_DQS_P<4>
MEM_A_DQ<54>
MEM_A_DQ<32>
MEM_A_DQ<38>
MEM_A_DQ<35>
MEM_A_DQ<61>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
PP1V8_S3_MEM22 23 24 25 109 116 
MEM_A_DQ<36>
MEM_A_DQS_P<7>
PP1V2_S322 23 24 25 109 116 
MEM_A_DQS_P<6>
PP1V2_S322 23 24 25 109 116 
MEM_A_DQ<33>
MEM_A_DQS_P<5>
PP1V2_S322 23 24 25 109 116 
PP1V2_S322 23 24 25 109 116 
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
MEM_A_ZQ<2>
MEM_A_ODT<0>
MEM_A_CS_L<0>
MEM_A_CKE<2>
MEM_A_CAB<5>
MEM_A_CAB<3>
MEM_A_CAB<2>
MEM_A_CAB<1>
MEM_A_CAB<0>
MEM_A_CAB<4>
MEM_A_CS_L<1>
MEM_A_CLK_N<1>
MEM_A_CAB<7>
MEM_A_CAB<8>
MEM_A_CAB<9>
MEM_A_CLK_P<1>
MEM_A_ZQ<3>
MEM_A_CKE<3>
MEM_A_CAB<6>
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=DRAM
LPDDR3 DRAM Channel A (32-63)
X5R-CERM
0201-1
1.0UF
20%
10V
C24021
2
10V
X5R-CERM
20%
1.0UF
0201-1
C24221
2
0.1UF
16V
X5R-CERM
10%
0201
C24011
2
10V
0201-1
20%
X5R-CERM
1.0UF
C24211
2
X5R-CERM
10%
0.1UF
16V
0201
C24001
2
10V
X5R-CERM
0201-1
20%
1.0UF
C24201
2
0402-2
X6S-CERM
4V
10UF
20%
C24121
2
10UF
0402-2
X6S-CERM
4V
20%
C24321
2
112 
10V
X5R-CERM
0201-1
1.0UF
20%
C24111
210VX5R-CERM
0201-1
1.0UF
20%
C24101
2
10V
X5R-CERM
0201-1
1.0UF
20%
C24311
210VX5R-CERM
0201-1
1.0UF
20%
C24301
2
FBGA
ED
FA
23
2A
1M
A-
GD
-F
LPDDR3-16GB
CRITICAL
OMIT_TABLE
U2400
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
OMIT_TABLE
CRITICAL
ED
FA
23
2A
1M
A-
GD
-F
LPDDR3-16GB
FBGA
U2400
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J2
J3
K3
K4
L3
L4
L8
G8
P8
D8
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
L11
L10
G11
G10
P11
P10
D11
D10
C4
K9
R3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
J8
H4
J11
B3
B4
112 
26 22 7 
26 22 7 
113 26 7 
113 26 7 
26 7 
26 7 
113 26 7 
113 26 7 
112 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
0402-2
X6S-CERM
4V
10UF
20%
C24241
2
10UF
0402-2
X6S-CERM
4V
20%
C24071
2
0402-2
4V
20%
X6S-CERM
10UF
C24331
2
6.3V
10%
0.047UF
201
X5R
C24411
2
112 
6.3V
0.047UF
201
10%
X5R
C2440 1
2
201
MF
1/20W
243
1%
R24011
2
243
1%
1/20W
MF
201
R24001
2
26 22 7 
112 
10UF
0402-2
X6S-CERM
4V
20%
C24061
210V
0201-1
1.0UF
20%
X5R-CERM
C24051
2
0201-1
X5R-CERM
20%
1.0UF
10V
C24041
2X5R-CERM
0201-1
1.0UF
20%
10V
C24031
2
X6S-CERM
10UF
0402-2
4V
20%
C24231
2
112 
109 22 
109 22 
 II NOT TO REPRODUCEOR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
(2 OF 2)
VDD1
VDD2
VSSQ
VSSCA
VSS
VDDQ
VDDCA
(1 OF 2)
NU
CS1*
CS0*
ZQ1
ZQ0
VREFDQ
VREFCA
ODT
NC
DQS3_T
DQS3_C
DQS2_T
DQS2_C
DQS1_T
DQS1_C
DQS0_T
DQS0_C
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DM3
DM2
DM0
CKE0
CA9
CA8
CA7
CA6
CA4
CA3
CA2
CA1
CA0
DM1
CK_C
CKE1
CK_T
CA5
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
LPDDR3 CHANNEL B (0-31)
10uF caps are shared between DRAM.
PLACEMENT_NOTE:
Distribute evenly.
10uF caps are shared between DRAM.
Distribute evenly.
PLACEMENT_NOTE:
24 OF 121
25 OF 145
dvt-fab10
10.0.0
051-00647
PP0V6_S3_MEM_VREFCA_A25 109 
MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DQS_N<3>
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQ<24>
MEM_B_DQ<28>
MEM_B_DQ<25>
MEM_B_DQ<31>
MEM_B_DQ<27>
MEM_B_DQ<30>
MEM_B_DQ<26>
MEM_B_DQ<4>
MEM_B_DQ<6>
MEM_B_DQ<2>
MEM_B_DQ<5>
MEM_B_DQ<7>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<19>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<20>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<12>
MEM_B_DQ<9>
MEM_B_DQ<15>
MEM_B_DQ<8>
PP1V2_S322 23 24 25 109 
PP1V2_S322 23 24 25 109 116 
MEM_B_DQS_P<3>
MEM_B_DQS_N<2>
MEM_B_DQ<23>
PP1V2_S322 23 24 25 109 
MEM_B_DQ<3>
PP1V8_S3_MEM22 23 24 25 109 116 
MEM_B_DQ<16>
MEM_B_DQS_P<1> PP1V2_S322 23 24 25 109 116 
MEM_B_DQ<29>
PP1V2_S322 23 24 25 109 116 
PP1V8_S3_MEM22 23 24 25 109 116 
PP1V2_S322 23 24 25 109 116 
PP0V6_S3_MEM_VREFDQ_B
MEM_B_ZQ<0>
MEM_B_ODT<0>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_CLK_N<0>
MEM_B_CLK_P<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<9>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_B_CAA<4>
MEM_B_CAA<3>
MEM_B_CAA<2>
MEM_B_CAA<1>
MEM_B_CAA<0>
MEM_B_ZQ<1>
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=DRAM
LPDDR3 DRAM Channel B (0-31)
X5R-CERM
0201-1
20%
1.0UF
10V
C25021
2
10V
X5R-CERM
0201-1
1.0UF
20%
C25221
2
0.1UF
16V
X5R-CERM
10%
0201
C25011
2
10V
X5R-CERM
0201-1
1.0UF
20%
C25211
2
0.1UF
16V
X5R-CERM
10%
0201
C25001
2
10V
X5R-CERM
0201-1
1.0UF
20%
C25201
2
0402-2
X6S-CERM
4V
20%
10UF
C25121
2
10UF
4V
X6S-CERM
20%
0402-2
C25321
2
112 
10V
X5R-CERM
0201-1
1.0UF
20%
C25111
210VX5R-CERM
0201-1
1.0UF
20%
C25101
2
10V
X5R-CERM
0201-1
1.0UF
20%
C25311
210VX5R-CERM
0201-1
1.0UF
20%
C25301
2
ED
FA
23
2A
1M
A-
GD
-F
LPDDR3-16GB
FBGA
CRITICAL
OMIT_TABLE
U2500
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
FBGA
LPDDR3-16GB
ED
FA
23
2A
1M
A-
GD
-F
CRITICAL
OMIT_TABLE
U2500
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J2
J3
K3
K4
L3
L4
L8
G8
P8
D8
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
L11
L10
G11
G10
P11
P10
D11
D10
C4
K9
R3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
J8
H4
J11
B3
B4
112 
26 25 7 
26 25 7 
113 26 7 
113 26 7 
26 7 
26 7 
113 26 7 
113 26 7 
112 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
0402-2
4V
10UF
20%
X6S-CERM
C25241
2
0402-2
10UF
X6S-CERM
4V
20%
C25071
2
4V
0402-2
X6S-CERM
20%
10UF
C25331
2
112 
201
0.047UF
10%
6.3V
X5R
C25411
2
201
0.047UF
6.3V
10%
X5R
C2540 1
2
1%
243
1/20W
MF
201
R25011
2201
MF
1/20W
1%
243
R25001
2
26 25 7 
112 
10UF
0402-2
X6S-CERM
4V
20%
C25061
2
0201-1
X5R-CERM
10V
20%
1.0UF
C25051
210V
0201-1
1.0UF
20%
X5R-CERM
C25041
210VX5R-CERM
0201-1
1.0UF
20%
C25031
2
10UF
0402-2
X6S-CERM
20%
4V
C25231
2
112 
109 25 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
(2 OF 2)
VDD1
VDD2
VSSQ
VSSCA
VSS
VDDQ
VDDCA
(1 OF 2)
NU
CS1*
CS0*
ZQ1
ZQ0
VREFDQ
VREFCA
ODT
NC
DQS3_T
DQS3_C
DQS2_T
DQS2_C
DQS1_T
DQS1_C
DQS0_T
DQS0_C
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DM3
DM2
DM0
CKE0
CA9
CA8
CA7
CA6
CA4
CA3
CA2
CA1
CA0
DM1
CK_C
CKE1
CK_T
CA5
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
10uF caps are shared between DRAM.
Distribute evenly.
10uF caps are shared between DRAM.
PLACEMENT_NOTE:
Distribute evenly.
PLACEMENT_NOTE:
LPDDR3 CHANNEL B (32-63)
25 OF 121
dvt-fab10
10.0.0
051-00647
26 OF 145
MEM_B_DQ<33>
PP0V6_S3_MEM_VREFCA_A24 109 
MEM_B_DQS_P<7>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQ<60>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<63>
MEM_B_DQ<56>
MEM_B_DQ<59>
MEM_B_DQ<62>
MEM_B_DQ<35>
MEM_B_DQ<32>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<34>
MEM_B_DQ<38>
MEM_B_DQ<49>
MEM_B_DQ<55>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<48>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<44>
MEM_B_DQ<46>
MEM_B_DQ<41>
MEM_B_DQ<45>
MEM_B_DQ<40>
MEM_B_DQ<47>
PP1V2_S322 23 24 25 109 116 
PP1V2_S322 23 24 25 109 
PP1V2_S322 23 24 25 109 116 
PP1V8_S3_MEM22 23 24 25 109 116 
MEM_B_DQ<54>
MEM_B_DQ<61>
PP1V2_S322 23 24 25 109 116 
PP1V2_S322 23 24 25 109 116 
MEM_B_DQS_N<7>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
PP1V2_S322 23 24 25 109 
PP1V8_S3_MEM22 23 24 25 109 116 
MEM_B_DQ<39>
PP0V6_S3_MEM_VREFDQ_B
MEM_B_ZQ<2>
MEM_B_ZQ<3>
MEM_B_CAB<0>
MEM_B_CAB<1>
MEM_B_CAB<2>
MEM_B_CAB<3>
MEM_B_CAB<4>
MEM_B_CAB<5>
MEM_B_CAB<6>
MEM_B_CAB<7>
MEM_B_CAB<8>
MEM_B_CAB<9>
MEM_B_CKE<2>
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_CKE<3>
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=DRAM
LPDDR3 DRAM Channel B (32-63)
10V
X5R-CERM
1.0UF
20%
0201-1
C26021
2
10V
X5R-CERM
0201-1
1.0UF
20%
C26221
2
10%
0.1UF
X5R-CERM
16V
0201
C26011
2
10V
X5R-CERM
1.0UF
20%
0201-1
C26211
2
16V
0.1UF
10%
0201
X5R-CERM
C26001
2
10V
X5R-CERM
0201-1
1.0UF
20%
C26201
2
10UF
0402-2
X6S-CERM
4V
20%
C26321
2
112 
10V
X5R-CERM
0201-1
1.0UF
20%
C26111
210VX5R-CERM
0201-1
1.0UF
20%
C26101
2
10V
0201-1
20%
1.0UF
X5R-CERM
C26311
210VX5R-CERM
0201-1
1.0UF
20%
C26301
2
OMIT_TABLE
CRITICAL
FBGA
LPDDR3-16GB
ED
FA
23
2A
1M
A-
GD
-F
U2600
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
FBGA
LPDDR3-16GB
ED
FA
23
2A
1M
A-
GD
-F
CRITICAL
OMIT_TABLE
U2600
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J2
J3
K3
K4
L3
L4
L8
G8
P8
D8
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
L11
L10
G11
G10
P11
P10
D11
D10
C4
K9
R3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
J8
H4
J11
B3
B4
112 
26 24 7 
26 24 7 
113 26 7 
113 26 7 
26 7 
26 7 
113 26 7 
113 26 7 
112 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
113 26 7 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
112 
0402-2
X6S-CERM
4V
10UF
20%
C26121
2
10UF
4V
0402-2
20%
X6S-CERM
C26241
2
10UF
0402-2
X6S-CERM
4V
20%
C26071
2
10UF
4V
20%
X6S-CERM
0402-2
C26331
2
112 
201
0.047UF
10%
6.3V
X5R
C26411
2
201
0.047UF
6.3V
10%
X5R
C2640 1
2
243
1/20W
1%
MF
201
R26011
2201
MF
1/20W
1%
243
R26001
2
112 
26 24 7 
10UF
0402-2
X6S-CERM
4V
20%
C26061
210VX5R-CERM
0201-1
1.0UF
20%
C26051
210VX5R-CERM
0201-1
1.0UF
20%
C26041
2X5R-CERM
0201-1
1.0UF
20%
10V
C26031
2
4V
0402-2
X6S-CERM
20%
10UF
C26231
2
112 
109 24 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
(2 OF 2)
VDD1
VDD2
VSSQ
VSSCA
VSS
VDDQ
VDDCA
(1 OF 2)
NU
CS1*
CS0*
ZQ1
ZQ0
VREFDQ
VREFCA
ODT
NC
DQS3_T
DQS3_C
DQS2_T
DQS2_C
DQS1_T
DQS1_C
DQS0_T
DQS0_C
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DM3
DM2
DM0
CKE0
CA9
CA8
CA7
CA6
CA4
CA3
CA2
CA1
CA0
DM1
CK_C
CKE1
CK_T
CA5
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
Intel recommends 68 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK
26 OF 121
PP0V6_S0_DDRVTT109 116 PP0V6_S0_DDRVTT109 116 
27 OF 145
10.0.0
051-00647
dvt-fab10
MEM_B_CAA<9>
MEM_A_CAB<7>
MEM_A_CAB<1>
MEM_A_CAA<6>
MEM_B_CAA<6>
MEM_B_CAA<5>
MEM_A_CKE<0>
MEM_B_ODT<0>
MEM_B_CS_L<1>
MEM_A_CLK_P<1>
MEM_B_CKE<2>
MEM_B_CAB<5>
MEM_B_CAA<2>
MEM_A_CS_L<0>
MEM_A_CS_L<1>
MEM_A_CAB<4>
MEM_B_CLK_N<1>
MEM_A_CAA<0>
MEM_A_CKE<3>
MEM_A_CLK_P<0>
MEM_A_CAB<0>
MEM_A_CKE<1>
MEM_A_CAA<5>
MEM_A_CAA<3>
MEM_A_CAA<4>
MEM_A_ODT<0>
MEM_B_CS_L<0>
MEM_A_CAA<9>
MEM_A_CAA<7>
MEM_A_CLK_N<0>
MEM_A_CAA<2>
MEM_A_CAA<1>
MEM_A_CAB<9>
MEM_A_CAB<8>
MEM_A_CAB<6>
MEM_A_CAB<5>
MEM_A_CLK_N<1>
MEM_A_CKE<2>
MEM_B_CAA<8>
MEM_B_CAA<7>
MEM_B_CLK_N<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_B_CAA<1>
MEM_B_CAB<4>
MEM_B_CAB<3>
MEM_B_CKE<3>
MEM_B_CLK_P<1>
MEM_B_CAA<0>
MEM_B_CAA<3>
MEM_B_CAA<4>
MEM_A_CAB<2>
MEM_A_CAA<8>
MEM_A_CAB<3>
MEM_B_CLK_P<0>
MEM_B_CAB<9>
MEM_B_CAB<8>
MEM_B_CAB<7>
MEM_B_CAB<6>
MEM_B_CAB<2>
MEM_B_CAB<1>
MEM_B_CAB<0>
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=DRAM
LPDDR3 DRAM Termination
0201
12PF
5%
NP0-C0G
25V
C27411
2
0201
12PF
5%
NP0-C0G
25V
C27211
2
1% MF1/20W
68
201
R2767 1 2 1% 201 MF1/20W
68R2766 1 2 2011/20W MF1%
68R2765 1 2 1% 2011/20W MF
68R2764 1 2
68
201 MF1% 1/20W
R2758 1 2
68
201 MF1% 1/20W
R2757 1 2
68
201 MF1% 1/20W
R2756 1 2
68
201 MF1/20W1%
R2755 1 2
68
1% 201 MF1/20W
R2753 1 2
68
2011/20W MF1%
R2752 1 2 2011/20W MF1%
68R2751 1 2
68
1/20W1% MF201
R2743 1 2
68
1/20W1% MF201
R2742 1 2
68
1% MF1/20W 201
R2741 1 2 1% MF1/20W 201
68R2740 1 2
1%
68
201 MF1/20W
R2727 1 2 1% MF
68
1/20W 201
R2726 1 2 1%
68
MF2011/20W
R2725 1 2 1%
68
1/20W 201 MF
R2724 1 2
1%
68
MF1/20W 201
R2715 1 2
1%
68
2011/20W MF
R2716 1 2
1% 2011/20W MF
68R2717 1 2
1%
68
1/20W MF201
R2718 1 2
68
MF2011/20W1%
R2711 1 2
68
2011/20W MF1%
R2713 1 2
68
MF2011/20W1%
R2712 1 2
68
1% MF2011/20W
R2703 1 2
68
1/20W1% 201 MF
R2702 1 2
68
1% 1/20W 201 MF
R2701 1 2
68
MF2011% 1/20W
R2700 1 2
20%
CRITICAL
X5R-CERM-1
603
22UF
6.3V
C27401
2
20%
6.3V
603
CRITICAL
22UF
X5R-CERM-1
C27201
2
68
201 MF1/20W1%
R2754 1 2
1%
68
2011/20W MF
R2714 1 2
1/20W MF
82
2011%
R2770 1 2
82
MF1/20W 2011%
R2769 1 2 MF
82
1/20W 2011%
R2768 1 2
1% MF1/20W 201
68R2763 1 2 1% 201 MF
82
1/20W
R2762 1 2 1% 2011/20W MF
82R2761 1 2 1%
39
1/20W 201 MF
R2760 1 2 1% 201 MF
39
1/20W
R2759 1 2
68
1/20W MF2011%
R2750 1 2 1/20W1% MF201
68R2749 1 2 1%
82
MF1/20W 201
R2748 1 2 MF201
82
1% 1/20W
R2747 1 2
39
MF2011% 1/20W
R2746 1 2
39
1/20W MF2011%
R2745 1 2
68
1% 201 MF1/20W
R2744 1 2
1/20W MF2011%
82R2730 1 2 1/20W
82
MF1% 201
R2729 1 2 1% 1/20W MF
82
201
R2728 1 2
68
201 MF1/20W1%
R2723 1 2 1% 1/20W 201
82
MF
R2722 1 2 1%
82
MF1/20W 201
R2721 1 2 1%
39
2011/20W MF
R2720 1 2 1% MF201
39
1/20W
R2719 1 2
68
201 MF1% 1/20W
R2710 1 2
68
201 MF1% 1/20W
R2709 1 2 MF2011%
82
1/20W
R2708 1 2
82
2011/20W1% MF
R2707 1 2
39
MF2011% 1/20W
R2706 1 2
39
201 MF1% 1/20W
R2705 1 2
68
201 MF1% 1/20W
R2704 1 2
23 22 7 
23 22 7 
23 22 7 
113 22 7 
25 24 7 
25 24 7 
25 24 7 
113 25 7 
23 7 
113 23 7 
113 23 7 
113 25 7 
113 25 7 
113 25 7 
113 25 7 
25 7 
25 7 
113 25 7 
113 25 7 
113 25 7 
113 25 7 
113 25 7 
113 25 7 
113 25 7 
113 24 7 
113 24 7 
113 24 7 
113 24 7 
113 24 7 
24 7 
24 7 
113 24 7 
113 24 7 
113 24 7 
113 24 7 
113 24 7 
113 24 7 
4V
20%
0.47UF
201
CERM-X5R-1
C27101
2
20%
4V
0.47UF
CERM-X5R-1
201
C27111
2
0.47UF
4V
20%
201
CERM-X5R-1
C27131
2
4V
20%
0.47UF
CERM-X5R-1
201
C27151
2
201
0.47UF
4V
20%
CERM-X5R-1
C27171
2
CERM-X5R-1
201
4V
20%
0.47UF
C27191
2
20%
0.47UF
4V
CERM-X5R-1
201
C27181
2
4V
20%
201
CERM-X5R-1
0.47UF
C27161
2
4V
20%
201
CERM-X5R-1
0.47UF
C27141
2
0.47UF
201
4V
20%
CERM-X5R-1
C27121
2
113 24 7 
20%
4V
201
CERM-X5R-1
0.47UF
C27081
2
113 23 7 
113 23 7 
113 22 7 
113 22 7 
113 23 7 
113 23 7 
113 23 7 
113 23 7 
113 22 7 
113 23 7 
113 22 7 
113 22 7 
22 7 
113 22 7 
113 23 7 
113 23 7 
113 23 7 
23 7 
113 22 7 
22 7 
113 22 7 
113 22 7 
113 22 7 
113 22 7 
201
20%
4V
0.47UF
CERM-X5R-1
C27091
2
CERM-X5R-1
20%
4V
0.47UF
201
C27071
2
4V
201
CERM-X5R-1
20%
0.47UF
C27051
2
201
0.47UF
4V
20%
CERM-X5R-1
C27061
2
0.47UF
4V
20%
CERM-X5R-1
201
C27031
2
201
0.47UF
20%
CERM-X5R-1
4V
C27011
2
20%
CERM-X5R-1
4V
201
0.47UF
C27001
2
201
CERM-X5R-1
20%
4V
0.47UF
C27041
2
4V
201
20%
CERM-X5R-1
0.47UF
C27021
2
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
PLACE_NEAR=
PU at PCH
PU at PCH
To SPI Flash
USE NEAREST GND BALL
(AC22) FOR THERM_D_N
SNK0 AC Coupling
SNK1 AC Coupling
not used
10K PU ON CLOCKS PAGE
27 OF 121
PP3V3_UPC_XB_LDO 29 
TBT_X_TMU_CLK_IN
NC_DP_X_SRC_ML_P<0>
NC_DP_X_SRC_ML_P<3>
NC_DP_X_SRC_ML_P<1>
NC_DP_X_SRC_ML_N<0>NC_DP_X_SRC_ML_P<2>
NC_DP_X_SRC_AUX_P
NC_DP_X_SRC_ML_N<3>
NC_DP_X_SRC_AUX_N
DP_X_SNK0_DDC_DATA
DP_X_SNK0_DDC_CLK
SMC_PME_S4_DARK_L
TBT_X_USB_PWR_EN
PM_BATLOW_L
UPC_X_SPI_MOSI 29 
DP_X_SNK1_DDC_CLK
DP_X_SNK1_DDC_DATA
JTAG_ISP_TDO
TBTTHMSNS_X_D1_P
NC_DP_X_SRC_ML_N<2>
NC_DP_X_SRC_ML_N<1>
TBT_X_PCI_RESET_L
PP3V3_S5_TBT_X_SW 27 33 
TBT_X_TMU_CLK_OUT
PP3V3_S5_TBT_X_SW 27 33 
TBT_X_CIO_PWR_EN
UPC_X_SPI_CLK 29 
UPC_X_SPI_CS_L 29 
UPC_X_SPI_MISO 29 
28 OF 145
10.0.0
051-00647
dvt-fab10
LAST_MODIFIED=Wed Aug 24 09:57:49 2016
TBT_X_SPI_CS_L
TBT_X_ROM_HOLD_L
DP_XA_HPD
TBT_XB_LSRX
DP_XA_AUXCH_P
TBT_XA_LSRX
DP_XB_HPD
DP_XB_AUXCH_P
DP_XB_AUXCH_N
DP_XA_AUXCH_N
TBT_XA_LSTX
TBT_XB_LSTX
TBT_X_SPI_MOSITBT_X_SPI_CLK
DP_X_SNK1_AUXCH_C_N
DP_X_SNK1_AUXCH_C_P
DP_X_SNK0_ML_C_P<1>
DP_X_SNK0_ML_C_P<2>
DP_X_SNK1_ML_C_P<0>
DP_X_SNK1_ML_C_N<3>
DP_X_SNK1_ML_C_P<2>
DP_X_SNK1_ML_C_P<1>
DP_X_SNK1_ML_C_N<1>
DP_X_SNK1_ML_C_N<0>
DP_X_SNK0_AUXCH_C_N
DP_X_SNK0_AUXCH_C_P
DP_X_SNK0_ML_C_N<3>
DP_X_SNK1_ML_C_P<3>
DP_X_SNK1_ML_C_N<2>
DP_X_SNK1_ML_N<3>
DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_P<2>
DP_X_SNK1_ML_N<0>
DP_X_SNK1_ML_N<1>
DP_X_SNK0_AUXCH_N
DP_X_SNK0_ML_N<0>
DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_N<1>
DP_X_SNK0_ML_P<0>
DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<2>
DP_X_SNK1_AUXCH_P
DP_X_SNK1_ML_P<3>
DP_X_SNK0_ML_N<3>
DP_X_SNK0_AUXCH_P
DP_X_SNK0_ML_P<2>
DP_X_SNK0_ML_C_N<1>
DP_X_SNK0_ML_C_N<0>
DP_X_SNK1_AUXCH_N
DP_X_SNK1_ML_P<0>
DP_X_SNK0_ML_C_P<0>
DP_X_SNK0_ML_C_P<3>
DP_X_SNK0_ML_C_N<2>
USB_UPC_XA_N
TBT_X_RSENSE
USBC_XA_D2R_P<2>
PCIE_TBT_X_R2D_P<2>
PCIE_CLK100M_TBT_X_N
TBT_X_PCIE_BIAS
PCIE_TBT_X_D2R_C_N<3>
DP_X_SNK1_ML_N<1>
DP_X_SNK0_AUXCH_P
DP_X_SNK0_HPD
PCIE_TBT_X_R2D_P<3>
PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_P<0>
PCIE_TBT_X_D2R_C_P<3>
PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_R2D_N<3>
DP_X_SRC_HPD
DP_X_SRC_RBIAS
TBT_X_ROM_WP_L
DP_X_SNK0_ML_P<1>
DP_X_SNK0_ML_P<3>
DP_X_SNK0_ML_N<3>
DP_X_SNK0_AUXCH_N
DP_X_SNK1_ML_P<0>
DP_X_SNK1_ML_N<0>
TBT_X_HDMI_DDC_DATA
TBT_X_HDMI_DDC_CLK
I2C_TBT_XB_INT_L
I2C_TBT_XA_INT_L
TBT_X_FORCE_PWR
PM_SLP_S3_L
TBT_X_TEST_PWR_GOOD
TBT_X_TEST_EN
TBT_X_XTAL25M_IN
TBT_X_XTAL25M_OUT
USBC_XB_R2D_C_P<1>
USBC_XB_R2D_C_N<2>
USBC_XB_R2D_C_N<1>
USBC_XB_D2R_P<1>
DP_XB_AUXCH_C_P
USBC_XB_D2R_N<1>
USB_UPC_XB_P
DP_XB_AUXCH_C_N
TBT_XB_LSTX
USB_UPC_XB_N
DP_X_SNK1_ML_P<1>
DP_X_SNK1_ML_N<2>
DP_X_SNK1_ML_P<3>
DP_X_SNK1_ML_N<3>
DP_X_SNK1_AUXCH_P
DP_X_SNK1_AUXCH_N
DP_X_SNK1_HPD
DP_X_SNK_RBIAS
JTAG_TBT_TDI
JTAG_TBT_X_TMS
JTAG_TBT_TCK
TBT_X_RBIAS
USBC_XA_R2D_C_P<2>
USBC_XA_D2R_N<2>
USBC_XA_R2D_C_P<1>
USBC_XA_R2D_C_N<2>
USBC_XA_D2R_P<1>
USBC_XA_R2D_C_N<1>
DP_XA_AUXCH_C_P
USBC_XA_D2R_N<1>
USB_UPC_XA_P
DP_XA_AUXCH_C_N
TBT_XA_LSTX
DP_XB_HPD
TBT_XB_USB2_RBIAS
TBT_XA_LSRX
DP_XA_HPD
TBT_XA_USB2_RBIAS
PCIE_TBT_X_R2D_P<1>
PCIE_TBT_X_R2D_N<1>
DP_X_SNK0_ML_P<2>
PCIE_CLK100M_TBT_X_P
PCIE_TBT_X_R2D_N<2>
TBT_X_CLKREQ_L
USBC_X_RESET_L
PCIE_TBT_X_D2R_C_N<2>
DP_X_SNK0_ML_N<2>
DP_X_SNK0_ML_N<0>
TBT_X_SPI_MISO
I2C_TBT_X_SDA
DP_X_SNK1_ML_P<2>
TBT_X_ROM_WP_L
DP_X_SNK0_ML_P<0>
TBT_X_CIO_PLUG_EVENT_L
I2C_TBT_X_SCL
DP_X_SNK0_ML_N<1>
USBC_XB_D2R_N<2>
USBC_XB_D2R_P<2>
USBC_XB_R2D_C_P<2>
TBT_XB_LSRX
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=TBT
USB-C HIGH SPEED 1
113 32 
113 32 
113 32 
113 32 
X5R-CERM
020116V10%0.1UF
GND_VOID=TRUE
C2835 1 2
020110% 16V
X5R-CERM0.1UF
GND_VOID=TRUE
C2820 1 2
0.1UF X5R-CERM 020116V10%
GND_VOID=TRUE
C2821 1 2
0.1UF X5R-CERM10% 16V 0201
GND_VOID=TRUE
C2822 1 2
0.1UF 10% 16V
GND_VOID=TRUE
X5R-CERM
0201
C2823 1 2
0.1UF 020116V10%X5R-CERM
GND_VOID=TRUE
C2825 1 2
X5R-CERM
10% 16V 02010.1UF
GND_VOID=TRUE
C2824 1 2
0201
X5R-CERM
10% 16V0.1UF
GND_VOID=TRUE
C2826 1 2
0.1UF X5R-CERM16V 020110%
GND_VOID=TRUE
C2827 1 2
GND_VOID=TRUE
0.1UF 020116V10%X5R-CERM
C2829 1 2
0.1UF 16V10%X5R-CERM 0201
GND_VOID=TRUE
C2828 1 2
X5R-CERM
020116V10%0.1UF
GND_VOID=TRUE
C2831 1 2
020116V10%
X5R-CERM0.1UF
GND_VOID=TRUE
C2830 1 2
X5R-CERM
020116V0.1UF 10%
GND_VOID=TRUE
C2832 1 2
0.1UF 020116V10%X5R-CERM
GND_VOID=TRUE
C2833 1 2
10%
X5R-CERM0.1UF 020116V
GND_VOID=TRUE
C2834 1 2
020116V10%0.1UF X5R-CERM
GND_VOID=TRUE
C2836 1 2
020116V10%
X5R-CERM0.1UF
GND_VOID=TRUE
C2838 1 2
16V10%
X5R-CERM0.1UF 0201
GND_VOID=TRUE
C2837 1 2
GND_VOID=TRUE
X5R-CERM
16V10% 02010.1UF
C2839 1 2
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
113 99 
1/20W
201
5%
MF
2.2K
R28371
2
201
5%
MF
1/20W
2.2K
R28361
2
201
5%
MF
1/20W
2.2K
R28351
2201
5%
MF
1/20W
2.2K
R28341
2
TBT-AR-4C-CNTRL
CRITICAL
OMIT_TABLE
FCBGA
U2800
B23
A23
W11
Y11
Y5
R4
AA2
AC7
AB7
AC9
AB9
AC11
AB11
AC13
AB13
W12
Y12
Y8
N4
Y6
AC15
AB15
AC17
AB17
AC19
AB19
AC21
AB21
Y18
Y19
W19
G1
R1
R2
N1
N2
L1
L2
J1
J2
N6
AB4
AC3
AB3
AC4
L15
N15
U1
U2
V1
V2
W1
W2
Y1
Y2
AA1
C23
C22
W13
W18
AB2
D6
W15
Y15
M4
A4
A5
A21
B21
B15
A15
B19
A19
B17
A17
D20
E20
H19
W16
Y16
G2
B5
B4
B13
A13
A7
B7
B11
A11
B9
A9
D19
E19
F19
V18
AC5 N16
T19
V19
Y22
Y23
T22
T23
M22
M23
H22
H23
V22
V23
P22
P23
K22
K23
F22
F23
L4
J4
E2
D4
H4
F2
D2
F1
H6
F4
J6
T4
Y4
W4
AC1
E1
AB5
AC23
AB23
V4
E18
D22
D23
113 29 
113 29 
113 29 
113 29 
113 29 
113 29 
113 29 
113 29 
103 
113 31 
113 31 
GND_VOID=TRUE
0.1UF 020110% 16VX5R-CERM
C28131 2
GND_VOID=TRUE
020110% 16V
X5R-CERM0.1UF
C28121 2
113 30 
113 30 
GND_VOID=TRUEX5R-CERM
16V0201 10% 0.1UF
C281112
GND_VOID=TRUE
16V 0.1UF0201 10%X5R-CERM
C281012
5%
201
3.3K
1/20W
MF
R28901
2
1/20W
201
5%
MF
3.3K
R28921
2
MF
201
3.3K
5%
1/20W
R28931
2
3.3K
201
5%
1/20W
MF
R28911
2
113 29 
113 29 
113 29 
113 29 
30 29 27 
MF
201
1/20W
5%
100
R28291
2
1/20W
100
5%
MF
201
R28251
2
PLACE_NEAR=U2800.H6:2MM
4.75K1/20W
0201
TF
0.5%
PLACE_NEAR=U2800.J6:2MM
R2855
1 2
33 29 
113 29 
29 
29 
29 
29 
29 
29 
29 
29 
29 
29 
29 
29 
1/20W 201
100K
5% MF
R28721 2
2015% 1/20W MF
100K R28621 2
CERM
1UF
6.3V
10%
402
C28901
2
USON
W25Q80DVUXIE
8MBIT-3.0V
CRITICAL
OMIT_TABLE
U2890
6
1
5
2
4
7
9
8
3
89 29 
89 29 
113 29 
113 29 
113 29 
113 29 
29 
29 
31 30 29 
114 101 89 76 73 70 46 20 12 
31 30 
29 
91 
91 
29 
103 101 29 
113 29 
20 
12 
12 
103 101 29 
101 29 
29 15 
101 29 
30 27 
29 
29 
29 
29 
30 27 
5%
201
MF
1/20W
100K
R28311
2
113 32 
29 
29 
29 
29 
499
MF
201
1/20W
1%
PLACE_NEAR=U2800.H19:6MM
R2854
1
2
499
1/20W
MF
201
1%
PLACE_NEAR=U2800.F19:5MM
R28531
2
113 32 
113 32 
14K
U2800.N6:2MM
201MF
1%
1/20W
R2852
1 2
MF
1%
1/20W
201
3.01K
PLACE_NEAR=U2800.N16:2MM
R2851
1 2
29 
29 
113 32 
1/20W
PLACE_NEAR=U2800.Y18:2MM1% MF14K 201
R2850
12
113 32 
MF5%
1M
2011/20W
R28611 2
5%
1M
MF 2011/20W
R28601 2
1/20W5% 201MF
1M R28701 2
1M
5% MF1/20W 201
R28711 2
113 32 
54 
113 32 
113 32 
1/20W
MF
5%
201
100K
R28271
2
113 32 
31 27 
113 32 
100K
201
1/20W
MF
5%
R28301
2
29 20 
113 32 
31 27 
31 27 
113 32 
29 
30 29 27 
31 27 
30 27 
31 27 
30 27 
31 27 
29 29 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
29 
27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 
113 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 
113 
113 27 
113 27 
113 27 
29 
113 27 
27 
113 27 
113 27 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARYPROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
DRAWING
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
S
O
U
R
C
E
 P
O
R
T
 0
P
C
IE
 G
E
N
3
DEBUG
P
O
R
T
 A
T
B
T
 P
O
R
T
S
MISC
S
IN
K
 P
O
R
T
 1
P
O
R
T
 B
P
O
C
 G
P
IO
LC
 G
P
IO
S
IN
K
 P
O
R
T
 0
SYM 1 OF 2
PA_USB2_D_N
RSENSE
PA_RX1_P
PCIE_RX2_P
GPIO_8
PCIE_REFCLK_100_IN_N
PCIE_RBIAS
DPSRC_ML0_P
DPSRC_ML3_P
PCIE_TX3_N
DPSNK1_ML1_N
DPSNK1_ML2_P
USB2_ATEST
DPSNK0_AUX_P
DPSNK0_HPD
PCIE_RX3_P
PCIE_RX0_N
PCIE_RX0_P
PCIE_TX3_P
PCIE_TX2_N
PCIE_TX2_P
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX0_N
PCIE_TX0_P
PCIE_RX3_N
DPSNK0_ML0_P
DPSRC_ML1_P
DPSRC_ML0_N
DPSRC_ML2_P
DPSRC_AUX_P
DPSRC_ML3_N
DPSRC_HPD
DPSRC_AUX_N
DPSRC_RBIAS
GPIO_0
GPIO_1
GPIO_2
DPSNK0_ML0_N
DPSNK0_ML1_P
DPSNK0_ML1_N
DPSNK0_ML3_P
DPSNK0_ML3_N
DPSNK0_AUX_N
DPSNK0_DDC_DATA
DPSNK0_DDC_CLK
DPSNK1_ML0_P
DPSNK1_ML0_N
GPIO_5
GPIO_3
GPIO_4
GPIO_6
GPIO_7
POC_GPIO_1
POC_GPIO_0
POC_GPIO_2
POC_GPIO_3
POC_GPIO_4
POC_GPIO_5
POC_GPIO_6
TEST_PWR_GOOD
TEST_EN
XTAL_25_IN
XTAL_25_OUT
EE_DI
EE_DO
PB_RX1_P
EE_CLK
PB_TX1_P
PB_RX1_N
PB_TX0_P
PB_TX1_N
PB_TX0_N
PB_RX0_P
PB_DPSRC_AUX_P
PB_RX0_N
PB_USB2_D_P
PB_DPSRC_AUX_N
PB_LSTX
PB_USB2_D_N
DPSNK1_ML1_P
DPSNK1_ML2_N
DPSNK1_ML3_P
DPSNK1_ML3_N
DPSNK1_AUX_P
DPSNK1_AUX_N
DPSNK1_HPD
DPSNK1_DDC_CLK
DPSNK1_DDC_DATA
DPSNK_RBIAS
TDI
TMS
TCK
RBIAS
TDO
PA_TX1_P
PA_RX1_N
PA_TX0_P
PA_TX1_N
PA_RX0_P
PA_TX0_N
PA_DPSRC_AUX_P
PA_RX0_N
PA_USB2_D_P
PA_DPSRC_AUX_N
PA_LSTX
PB_LSRX
PB_DPSRC_HPD
MONDC_SVR
PB_USB2_RBIAS
ATEST_P
ATEST_N
MONDC_DPSNK_0
MONDC_DPSNK_1
MONDC_DPSRC
PA_LSRX
PA_DPSRC_HPD
PA_USB2_RBIAS
THERMDA
THERMDA
PCIE_ATEST
FUSE_VQPS_64
TEST_EDM
MONDC_CIO_0
FUSE_VQPS_128
MONDC_CIO_1
PCIE_RX1_P
PCIE_RX1_N
DPSNK0_ML2_P
DPSNK0_ML2_N
PCIE_REFCLK_100_IN_P
DPSRC_ML2_N
DPSRC_ML1_N
PCIE_RX2_N
PERST*
PCIE_CLKREQ*
RESET*
EE_CS*
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
VCC
DI(IO0)
DO(IO1)
CS*
HOLD*(IO3)
WP*(IO2)
CLK
GND EPAD
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
NC
NC
BI
BI
IN
IN
OUT
NC
NC
IN
BI
BI
BI
BI
IN
IN
BI
BI
OUT
OUT
IN
OUT
IN
OUT
IN
IN
OUT
IN
OUT
IN
OUT
OUT
FROM USB-C PORT
CONTROLLER (UPC)
SOURCED BY INTERNAL SWITCH
INTERNAL SWITCH
SOURCED BY
SOURCED BY INTERNAL SWITCH
INTERNAL SWITCH
SOURCED BY
SOURCED BY INTERNAL SWITCH
SOURCED BY INTERNAL SWITCH
(SEE INTEL LAYOUT GUIDELINES)
AND GND OF VCC3P3_SVR CAPS
FROM SYSTEM GND IN LAYOUT
SOURCED BY INTERNAL SWITCH
INTERNAL SWITCHING VR OUTPUT
SOURCED BY
support page
INTERNAL SWITCH
2x 10uF outside BGA area
ISOLATE GND OF SVR_IND CAPSAdd XW or alias on 
XW
28 OF 121
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.1200
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
TBTTHMSNS_X_D1_N
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=0.9V
PP3V3_TBT_X_S0 29 110 116 
PP3V3_S5_TBT_X_SW
29 33 
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.2000
VOLTAGE=0V
MIN_LINE_WIDTH=0.2000
29 OF 145
10.0.0
051-00647
dvt-fab10
PP0V9_TBT_X_USB
PP0V9_TBT_X_LVR
PP0V9_TBT_X_CIO
PP3V3_TBT_X_ANA_USB2
PP3V3_TBT_X_ANA_PCIE
PP0V9_TBT_X_PCIE
VR0V9_IND_TBT_X
PP0V9_TBT_X_DP
PP0V9_TBT_X_SVR
PP3V3_TBT_X_LC
PP3V3_TBT_X_F
P0V9_TBT_X_SVR_AGND
BOM_COST_GROUP=TBT
USB-C HIGH SPEED 2
SYNC_MASTER=J80_MLB SYNC_DATE=11/06/2015
6.3V
X5R
0201-1
1.0UF
20%
C29361
26.3VX5R
0201-1
1.0UF
20%
C29351
26.3VX5R
0201-1
1.0UF
20%
C29341
2
6.3V
X5R
0201-1
1.0UF
20%
C2947 1
2
6.3V
X5R
0201-1
1.0UF
20%
C29331
26.3VX5R
0201-1
1.0UF
20%
C29321
26.3VX5R
0201-1
1.0UF
20%
C29311
2
54 
PLACE_NEAR=U2800.AC22:2MM
NO_XNET_CONNECTION=1
SM
XW2900
1 2
6.3V
X5R
0201-1
1.0UF
20%
C29211
2
10UF
CERM-X5R
0402-4
6.3V
20%
C29781
2
0402-4
CERM-X5R
10UF
6.3V
20%
C29771
2CERM-X5R
0402-4
6.3V
20%
10UF
C29761
2
0402-4
BYPASS=U2800.A2:A1:3MM
10UF
CERM-X5R
6.3V
20%
C29751
2
6.3V
X5R
0201-1
1.0UF
20%
C29911
2
6.3V
X5R
0201-1
1.0UF
20%
C2990 1
2
6.3V
X5R
0201-1
1.0UF
20%
C29201
2
OMIT_TABLE
CRITICAL
FCBGA
TBT-AR-4C-CNTRL
U2800
C1
C2
D1
A1
B1
B2
V11
V12
V13
L6
M6
L19
N19
L18
M18
N18
R8
R9
R11
R12
L8
L11
L12
M8
T11
T12
F18
H18
J11
H11
M13
M15
M16
L9
M9
E12
E13
F11
F12
F13
F15
J9
R15
R16
L16
J16
R6
R13
A2
A3
B3
F8
H9
D5
E4
E5
E6
F5
F6
H5
H8
J8
J12
J13
J15
L13
M12
N8
N9
N11
N12
N13
T6
T8
T9
T13
T15
T16
T18
AB1
AC2
M11
A6
A8
A10
A12
A14
A16
A18
A20
A22
B6
B8
B10
B12
B14
B16
B18
B20
B22
D8
D9
D11
D12
D13
D15
D16
D18
E8
E9
E11
E15
E16
E22
E23
F9
F20
F16
G22
G23
H1
H2
H12
H13
H15
H16
H20
J5
J19
J20
J18
J22
J23
K1
K2
L5
L20
L22
L23
M1
M2
M5
M19
M20
N5
N20
N22
N23
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U23
U22
V5
V6
V8
V9
V15
V16
V20
W5
W6
W8
W9
W20
W22
W23
Y9
Y13
Y20
AA22
AA23
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
6.3V
X5R
0201-1
1.0UF
20%
C29141
2
6.3V
X5R
0201-1
1.0UF
20%
C29811
2
6.3V
X5R
0201-1
1.0UF
20%
C29301
2
6.3V
X5R
0201-1
1.0UF
20%
C29101
2 6.3VX5R
0201-1
1.0UF
20%
C29111
2 6.3VX5R
0201-1
1.0UF
20%
C29121
2 6.3VX5R
0201-1
1.0UF
20%
C29131
2
CRITICAL
1.0UH-20%-2.1A-0.128OHM
0603
L2990
1 2
CRITICAL
1210
0.68UH-20%-6.1A-0.020OHM
L2950
1 2
12PF
5%
25V
NP0-C0G
0201
C29171
2
0603
47UF
CER-X5R
6.3V
20%
C2995 1
2
47UF
0603
CER-X5R
6.3V
20%
C2994 1
2
0603
CER-X5R
47UF
6.3V
20%
C29521
2
0603
CER-X5R
47UF
6.3V
20%
C29511
2
0603
CER-X5R
47UF
6.3V
20%
C29501
2
0.1UF
X5R-CERM
10%
16V
0201
C29801
2
6.3V
X5R
0201-1
1.0UF
20%
C29161
26.3VX5R
0201-1
1.0UF
20%
C29151
2
CERM-X5R
10UF
0402-4
6.3V
20%
C2954 1
2
0402-4
10UF
CERM-X5R
6.3V
20%
C2955 1
26.3VX5R
0201-1
1.0UF
20%
C2992 1
2
6.3V
X5R
0201-1
1.0UF
20%
C2945 1
2
6.3V
X5R
0201-1
1.0UF
20%
C2993 1
2
6.3V
X5R
0201-1
1.0UF
20%
C29841
2 6.3VX5R
0201-1
1.0UF
20%
C29851
2
6.3V
X5R
0201-1
1.0UF
20%
C29671
26.3VX5R
0201-1
1.0UF
20%
C29641
2 6.3VX5R
0201-1
1.0UF
20%
C29651
2 6.3VX5R
0201-1
1.0UF
20%
C29661
2
6.3V
X5R
0201-1
1.0UF
20%
C2946 1
2
29 
29 
29 
116 
29 
29 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
G
N
D
V
C
C
SYM 2 OF 2VCC0P9_DP
VCC0P9_DP
VCC0P9_DP
VCC3P3_SX
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSRC
VCC0P9_ANA_DPSNK
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC0P9_SVR
VCC0P9_SVR
VCC3P3_SVR
VSS_ANAVSS_ANA
VCC0P9_DP
VCC0P9_ANA_DPSNK
VCC3P3_LC
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_USB
VCC0P9_USB
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_2
VCC0P9_ANA_PCIE_1
VCC0P9_PCIE
VCC0P9_PCIE
VCC0P9_ANA_DPSNK
VCC0P9_LVR
VCC0P9_LVR
VCC3P3_SVR
VCC0P9_SVR_ANA
VCC3P3A
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC3P3_S0
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANAVSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
SVR_VSS
SVR_VSS
SVR_VSS
VSS_ANA
VSS_ANA
VSS_ANA
SVR_IND
SVR_IND
VCC0P9_SVR_SENSE
VCC0P9_SVR_ANA
VCC0P9_SVR_ANA
VCC3P3_ANA_PCIE
VCC3P3_ANA_USB2
VCC0P9_ANA_PCIE_1
VCC0P9_PCIE
VCC0P9_DP
VCC0P9_DP
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
SVR_IND
VCC3P3_SVR
VCC0P9_LVR
VCC0P9_LVR_SENSE
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
Ridge PDs
ROM
DCI
 USBC DEBUG CONN
PCH USB3
TMU CLKs ACE A RPD STRAPPING
Place on bottom
 AR/ACE SPI BUS SERIES R'S
RIDGE 0.9V SVR XW
Place on bottom
 ACE B RPD STRAPPING
TBT to ACE
FUSES FOR UPC
USBC 5V EN PD
(Write: 0x70 Read: 0x71)
U3100
to/from Ridge
740S0135
Pri ACE
U3200
Sec ACE
TBT
 AR
 
I2C SERIES R'S
(Write: 0x7E Read: 0x7F)
(MASTER)
SMC MOJO
ACE PDs
ACE DEBUG CONN
 Ace
Ridge PCIE Caps
Alpine Ridge U2800
POWER ALIASES
SIGNAL ALIASES
 
RIDGE JTAG ISOLATION
DP SRC OPTIONS
IF DP SRC NOT USED
ACE/SMC I2C PU 
25MHz xtal
RIDGE DEBUG CONN
NC ALIASES / NO TEST
GND ALIASES
ACE Debug Support
29 OF 121
PP5V_S4_X_USBC34 116 
PP3V3_UPC_XA_LDO30 
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
PP3V3_TBT_X_S028 110 116 
PP5V_S4_X_USBC31 
PP5V_S4_X_USBC30 
PP20V_USBC_XA_VBUS29 30 
PP20V_USBC_XB_VBUS29 31 
PPDCIN_G3H30 31 103 104 105 VOLTAGE=20V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
PP3V3_UPC_XB_LDO31 
PP3V3_UPC_XB_LDO31 
PP3V3_UPC_XA_LDO30 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
VOLTAGE=5V
SMC_USBC_INT_L
USB3_EXTA_R2D_N
USB3_EXTA_D2R_P
JTAG_TBT_X_TMS
PP3V3_S430 
PP3V3_S431 
SMC_DEBUGPRT_RX_L
31 
USB3_EXTA_R2D_P
UPC_T_SPI_CS_L101 103 
USB2_UPC_XA_N30 
SMC_PME_S4_DARK_L30 31 103 104 
105 
UPC_X_SPI_CLK27 29 
UPC_T_SPI_MOSI101 103 
TBT_X_CIO_PWR_EN27 30 31 
UPC_X_5V_EN29 30 
PM_BATLOW_L27 
TBT_X_PCI_RESET_L 20 27 
TBT_T_TMU_CLK_IN 101 
PP3V3_S5_TBT_X_SW 28 33 
XDP_PCH_OBSDATA_C1 14 
XDP_PCH_OBSDATA_C0 14 
TBT_X_CIO_PLUG_EVENT_L
15 
TBT_X_USB_PWR_EN27 30 31 
JTAG_ISP_TDO27 101 103 
I2C_UPC_X_SDA231 
I2C_TBT_X_SDA 30 
UPC_X_SPI_MOSI
I2C_UPC_X_SDA230 
I2C_TBT_XA_INT_L 30 
I2C_TBT_X_SCL 31 
I2C_TBT_XB_INT_L 31 
NC_DP_X_SRC_ML_P<3..0>27 
I2C_UPC_X_SCL230 
USBC_XB_CC131 
USBC_XB_CC231 
DP_X_SNK0_DDC_CLK27 
UPC_X_SPI_CLK
UPC_X_SPI_CS_L
NC_DP_X_SRC_ML_P<3..0>
NC_DP_X_SRC_ML_N<3..0>
DP_X_SNK0_DDC_DATA27 
UPC_X_5V_EN29 30 
I2C_TBT_X_SDA 31 
TBT_X_TMU_CLK_OUT27 
SMBUS_SMC_4_G3H_SCL 49 
I2C_UPC_X_SCL231 
I2C_TBT_X_SCL 30 
NC_DP_X_SRC_AUX_P27 
PP20V_USBC_XA_VBUS29 30 
SMBUS_SMC_4_G3H_SCL 49 
SMBUS_SMC_4_G3H_SDA 49 
SMBUS_SMC_4_G3H_SDA 49 
NC_DP_X_SRC_AUX_N27 
PP20V_USBC_XB_VBUS29 31 
NC_DP_X_SRC_ML_N<3..0>27 
TBT_POC_RESET29 30 31 
DP_X_SNK1_DDC_CLK27 
SMC_DEBUGPRT_TX_L
31 
UPC_X_5V_EN31 
UPC_X_SPI_MOSI27 29 
UPC_T_SPI_MISO101 103 
TBT_POC_RESET
TP_USBC_XA_RESET_L30 
UPC_X_SPI_MISO
USB2_UPC_XA_P30 
UPC_X_SPI_CS_L27 29 
USB3_EXTA_D2R_N
SMC_USBC_INT_L
JTAG_TBT_T_TMS103 
PP3V3_UPC_XB_LDO27 
USB2_UPC_XB_P31 
USB2_UPC_XB_N31 
SMC_PME_S4_DARK_L27 101 103 
UPC_X_SPI_MISO27 29 
UPC_T_SPI_CLK101 103 
PP3V3_G3H 109 
DP_X_SNK1_DDC_DATA27 
USBC_XA_CC230 
USBC_XA_CC130 
GND30 31 103 104 
105 
GND31 
GND30 
GND30 
GND30 
GND30 
GND30 
GND30 
GND31 
GND30 
30 OF 145
10.0.0
051-00647
dvt-fab10
MAKE_BASE=TRUE
PP3V3_TBT_X_S0
MAKE_BASE=TRUE
PP20V_USBC_XA_VBUS
PP20V_USBC_XB_VBUS
MAKE_BASE=TRUE
PPDCIN_G3H
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP5V_S4_X_USBC
PP3V3_UPC_XB_LDO
MAKE_BASE=TRUE
PP3V3_UPC_XA_LDO
MAKE_BASE=TRUE
TBT_X_SPI_MOSI
UPC_XA_FAULT_L
SMC_DEBUGPRT_TX_L
MAKE_BASE=TRUE
USB2_UPC_XB_P
MAKE_BASE=TRUE
USB2_UPC_XB_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB2_UPC_XA_N
PCIE_TBT_X_R2D_C_P<1>
MAKE_BASE=TRUE
UPC_T_SPI_CLK
MAKE_BASE=TRUE
SMC_PME_S4_DARK_L
MAKE_BASE=TRUE
PM_BATLOW_L
PP0V9_TBT_X_PCIE
PP0V9_TBT_X_USB
USB3_EXTA_R2D_C_N
USBC_XA_CC1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USBC_XA_CC2
TBT_X_SPI_CLK_DBG
SMC_USBC_INT_L
MAKE_BASE=TRUE
TBT_T_TMU_CLK_IN
MAKE_BASE=TRUE
DP_X_SNK1_DDC_DATA
DP_X_SNK1_DDC_CLK
MAKE_BASE=TRUE
DP_X_SNK0_HPD
PP0V9_TBT_X_CIO
PCIE_TBT_X_R2D_C_P<2>
TP_UPC_XB_SWD_DATA
MAKE_BASE=TRUE
TBT_X_CIO_PLUG_EVENT_L
TBT_POC_RESET
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UPC_T_SPI_MISO
JTAG_ISP_TDO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UPC_T_SPI_MOSI
UPC_T_SPI_CS_L
MAKE_BASE=TRUE
UPC_X_SPI_MOSI
MAKE_BASE=TRUE
UPC_X_SPI_MISO
MAKE_BASE=TRUE
UPC_X_SPI_CS_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UPC_X_SPI_CLK
SMC_USBC_INT_L
MAKE_BASE=TRUE
JTAG_TBT_X_TMS
MAKE_BASE=TRUE
JTAG_TBT_T_TMS
MAKE_BASE=TRUE
TP_UPC_XA_SWD_DATA
PCIE_TBT_X_R2D_P<1>
I2C_TBT_XB_INT_L
TBT_X_XTAL25M_IN
UPC_XA_HPD_RX
PCIE_TBT_X_R2D_P<0>
TP_UPC_XB_SWD_CLK
?
TP_UPC_XA_SWD_CLK
TBT_X_XTAL25M_OUT_R
MAKE_BASE=TRUE I2C_TBT_XB_INT_L
TBT_X_SPI_CS_L
TBT_X_SPI_CLK
MAKE_BASE=TRUE
USBC_XB_CC1
MAKE_BASE=TRUE
USBC_XB_CC2
UPC_XB_SPI_CS_L
MAKE_BASE=TRUENC_DP_X_SRC_AUX_P
JTAG_ISP_TDI
MAKE_BASE=TRUE I2C_TBT_X_SCL
I2C_UPC_X_SDA2
MAKE_BASE=TRUE
DP_X_SRC_HPD
PCIE_TBT_X_R2D_C_N<1>
MAKE_BASE=TRUE I2C_TBT_X_SDA
PCIE_TBT_X_D2R_C_N<3>
JTAG_TBT_TDI
I2C_TBT_X_SDA
USBC_X_RESET_L
MAKE_BASE=TRUE
I2C_UPC_X_SCL2
P0V9_TBT_X_SVR_AGND
I2C_UPC_X_SDA2
I2C_UPC_X_SCL2
UPC_XB_SPI_MOSI
UPC_XB_SPI_CLK
DP_X_SNK0_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_X_SNK0_DDC_DATA
UPC_XB_SPI_MISO
PP20V_USBC_XB_VBUS_F
JTAG_ISP_TCK
PCIE_TBT_X_D2R_P<3>PCIE_TBT_X_D2R_C_P<3>
MAKE_BASE=TRUE I2C_TBT_XA_INT_L
NO_TEST=1
MAKE_BASE=TRUE
NO_TEST=1
MAKE_BASE=TRUE
NC_DP_X_SRC_AUX_N MAKE_BASE=TRUE
PCIE_TBT_X_D2R_C_N<2>
PCIE_TBT_X_R2D_C_P<3>
PCIE_TBT_X_R2D_C_P<0>
PCIE_TBT_X_D2R_C_N<0>
PCIE_TBT_X_R2D_C_N<3>
PCIE_TBT_X_D2R_P<1>PCIE_TBT_X_D2R_C_P<1>
PCIE_TBT_X_D2R_N<3>
PP20V_USBC_XA_VBUS_F
TBT_X_TMU_CLK_OUT
MAKE_BASE=TRUE
PCIE_TBT_X_R2D_N<0>
PCIE_TBT_X_R2D_N<1>
PCIE_TBT_X_R2D_P<3>
PCIE_TBT_X_R2D_P<2>
PCIE_TBT_X_D2R_N<2>
PCIE_TBT_X_D2R_P<2>
PCIE_TBT_X_D2R_N<1>
PCIE_TBT_X_R2D_C_N<2>
PCIE_TBT_X_D2R_P<0>
PCIE_TBT_X_R2D_N<2>
PCIE_TBT_X_D2R_N<0>
PCIE_TBT_X_D2R_C_P<0>
PCIE_TBT_X_D2R_C_P<2>
PCIE_TBT_X_D2R_C_N<1>
PCIE_TBT_X_R2D_N<3>
TBT_X_CIO_PLUG_EVENT_L
DP_X_SNK1_HPD
TBT_X_SPI_MISO
USB_UPC_PCH_XB_N
UPC_XB_HPD_RX
USB_UPC_XB_P
USB_UPC_XA_N
JTAG_TBT_TCK
MAKE_BASE=TRUE
USB3_EXTA_R2D_P
USB_UPC_PCH_XA_P
USB_UPC_PCH_XA_N
USB2_UPC_XA_P
MAKE_BASE=TRUE
USB_UPC_XA_P
UPC_XB_FAULT_L
PCIE_TBT_X_R2D_C_N<0>
USB3_EXTA_R2D_C_P
MAKE_BASE=TRUE
USB3_EXTA_D2R_N
MAKE_BASE=TRUE
USB3_EXTA_D2R_P
MAKE_BASE=TRUE
TP_USBC_XA_RESET_L
MAKE_BASE=TRUE
SMC_DEBUGPRT_RX_L
MAKE_BASE=TRUE
USB3_EXTA_R2D_N
PP3V3_S4
MAKE_BASE=TRUE
TBT_X_USB_PWR_EN
MAKE_BASE=TRUE
TBT_X_CIO_PWR_EN
MAKE_BASE=TRUE
UPC_XA_HPD_RX
SMC_USBC_INT_L
I2C_TBT_XA_INT_L
UPC_XA_UART_TX UPC_XA_UART_RX
I2C_UPC_XA_DBG_CTL_SCLTBT_X_SPI_CLK_DBG
I2C_TBT_X_SCL
SMC_RESET_L
TBT_X_XTAL25M_OUT
I2C_UPC_XA_DBG_CTL_SDA
USB_UPC_PCH_XB_P
USB_UPC_XB_N
MAKE_BASE=TRUE
UPC_X_5V_EN
NC_UPC_XB_I2C_ADDR
PP3V3_TBT_X_LC
DP_XA_HPD
UPC_XB_HPD_RX
MAKE_BASE=TRUE
UPC_XA_DBG_UART_TX
UPC_XA_DBG_UART_RX
TP_UPC_XB_DBG_UART_RX
TP_UPC_XB_DBG_UART_TX
BOM_COST_GROUP=TBT
USB-C Support
SYNC_MASTER=X363_AGOTETI SYNC_DATE=08/08/2016
C30200.1UF
X5R-CERM
21
16V 10% 0201
21
R3077 0
0201
5% 1/20W
MF
R3076
1/20W
21
MF 0201
0
5%
30 
30 
30 
30 
21
R3026
201MF
1/20W5%
100K
21
R3085
5% 1/20W MF 0201
0
NOSTUFF
0201
21
R3084
MF1/20W5%
0
NOSTUFF
R30812 1
NOSTUFF
0
5% 1/20W MF 0201
2 1R3082
0201
0
1/20W MF5%NOSTUFF
21
R3079
MF
5%
0
0201
1/20W
021
R3078
5% 1/20W
MF 0201
21
R3087
MF
1/20W5%0201
0
21
R3086
1/20W
0201MF
5%
0
21R3036
1/20W MF 2015%
0
R3035 0 21
5% 1/20W 201MF
10
505070-1220
7
J3001
1615
1413
1211
9
8
65
43
21
M-ST-SM
USBC_DBG
21
XW3000
SM
NO_XNET_CONNECTION=1
114 47 46 
114 47 46 
1 TP3001TP-P5
1 TP3002TP-P5
1 TP3004TP-P5
1 TP3003TP-P5
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 27 
113 
111 
113 
111 
113 
111 
113 
111 
113 
111 
113 
111 
113 
111 
113 
111 
2 1 C3050
0.22UF6.3VX5R0201 20%
GND_VOID=TRUE
2 1 C3051
GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3052
6.3V 0.22UF
GND_VOID=TRUE
X5R0201 20%
2 1 C3053
GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3054
GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3055
0.22UF
GND_VOID=TRUE
6.3VX5R0201 20%
2 1 C3056 GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3057
0.22UF
GND_VOID=TRUE
6.3VX5R0201 20%
2 1 C3040
0.22UF
GND_VOID=TRUE
6.3VX5R0201 20%
2 1 C3041
0.22UF6.3VX5R0201 20%
GND_VOID=TRUE
2 1 C3042
0.22UF
GND_VOID=TRUE
6.3VX5R0201 20%
2 1 C3044
0.22UF6.3VX5R0201 20%
GND_VOID=TRUE
2 1 C3043GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3046
0.22UF6.3V
GND_VOID=TRUE
X5R0201 20%
2 1 C3045GND_VOID=TRUE
0.22UF6.3VX5R0201 20%
2 1 C3047
0.22UF
GND_VOID=TRUE
6.3VX5R0201 20%
113 111 
113 111 
113 111 
113 111 
113 111 
113 111 
113 111 
113 111 
5%
21R3032 100K
1/20W 201MF
21R3033
NO_STUFF
1/20W
100K
201MF5%
31 
21R3093
5%
15
201MF1/20W
OMIT
402
2 1
R3088
NONENONE
NOSTUFF
NONE
505070-1220
1615
1413
1211
109
87
65
43
21
J3000USBC_DBG
M-ST-SM
21R3042
PLACE_NEAR=U5000:5mm
1/20W 201
33
5% MF
21R3041
5% 201
33
PLACE_NEAR=U5000:5mm
MF1/20W
402NONE
2 1
R3089
NONE
NOSTUFF
NONE
OMIT
15 21R3025
1/20W MF5% 201
PLACE_NEAR=U2800.V2:5mm
21R3044
5% MF1/20W 0201
0
PLACE_NEAR=U1100.AK28:10mm
21R3043
PLACE_NEAR=U1100.AJ29:10mm
0201
0
MF1/20W5%
21R3094
1/20W 2015% MF
100
21R3092
1/20W MF5% 201
15
21R3091
1/20W MF5% 201
15 5%
21R3090
MF 201
15
1/20W
1/20W
15 21R3098
201MF5%
15 21R3097
201MF5% 1/20W
5%
21R3096
MF1/20W 201
15
21R3095
MF
15
5% 2011/20W
29 27 
29 27 
29 27 
29 27 
31 
31 
31 
31 
MF5% 1/20W 201
21R3034 100K
NO_STUFF
R3070
100K 21
1/20W
MF
5%
201
R3069
21
201
MF
5%
100K
1/20W
R3067
100K 21
5%
201
MF
1/20W
21
F3001
6AMP-32V-0.0095OHM
PLACE_NEAR=Q3200:5MM
CRITICAL
0603
6AMP-32V-0.0095OHM
21
F3000
PLACE_NEAR=Q3100:5MM
CRITICAL
0603
21
R3038
201
1/20W
MF
5%
10K
21
R3040
1M
201
MF
1/20W
5%
30 
31 
103 15 14 31 30 29 
103 46 29 30 
31 
14 
14 
0.1UF
21
10%
C3021
0201X5R-CERM 16V
14 
14 
3
1
4
2 Y3000
CRITICAL
2.00X1.60-SM
25MHZ-25PPM-20PF-50OHM
100K 21
R3068
1/20W
5%
201
MF
21
C3002
20PF
5%
C0G
0201
25V
21
2015%
MF1/20W
0
R3007
2
1R3006
MF
1/20W
5%
201
1M
NOSTUFF
21
C3003
5%
20PF
25V
C0G
0201
32 
32 
116 114 64 50 
31 
30 
27 
103 48 47 46 
103 46 12 
28 
28 
32 30 
32 30 
29 
103 
46 29 
89 27 
28 
31 
29 27 
103 15 
27 15 
103 101 15 
30 
29 27 
30 29 
31 
30 
113 
29 
27 
27 
27 
32 31 
32 31 
15 
29 
27 
29 
27 
29 
27 
101 27 
29 27 
33 27 
29 
28 
29 
29 
31 
15 
29 
27 
30 
29 27 
89 27 
27 
14 
31 29 
27 
27 
101 27 
14 
14 
27 
114 110 103 
12 
12 
30 29 
103 46 29 
29 27 
31 30 31 30 
30 29 
29 27 
114 76 64 57 48 
30 
14 
27 
34 
28 
30 27 
31 29 
114 30 
114 30 
114 31 
114 31 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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REVISION
DRAWING NUMBER SIZE
D
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 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
IN
IN
OUT
IN
TP
TP
TP
TP
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
IN
IN
OUTIN
OUTIN
IN
OUT
OUT
IN
IN
Otherwise PU to PP3V3_UPC_XA_LDO
NC or GND to dissipate heat
PU to PP3V3_S4 if convenient
GND I2C_ADDR
ON BANSURI DESIGNS
USE GPIO3 FOR POWER_GATE_EN
ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR
USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
PRIMARY ONLY
(EVEN IN PRODUCTION)
TESTPOINTS MUST BE
REAR PORT:
for layout.
PRIMARY ONLY
PRIMARY ONLY
PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION
TO SMC
PULL R3109 AND R3108 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
FRONT PORT:
Add on 
PULL R3109 AND R3108 DOWN TO GND FOR 2ND RIDGE'S ACES
PRIMARY ACE USB-C PORT CONTROLLER (UPC)
MAX 100uF TOTAL ON RAIL
support page
FUSE
CAP FOR PP_5V0 ON VR PAGE
GROUND UPC SPI
CONNECT UPC SPI TO ROM
PRESENT FOR GPIO0, GPIO1
051-00647
10.0.0
31 OF 145
30 OF 121
dvt-fab10
PP3V3_UPC_XA_LDO 29 
PP3V3_S429 
TBT_X_USB_PWR_EN
TP_USBC_XA_RESET_L
I2C_TBT_X_SDA
I2C_TBT_XA_INT_L
I2C_UPC_X_SDA2
USBC_XA_CC2
PPDCIN_G3H 105 104 103 31 29 
GND
GND
GND
I2C_UPC_X_SCL2
SMC_USBC_INT_L
I2C_TBT_X_SCL
GND
GND
GND 29 
TBT_X_CIO_PWR_EN
UPC_X_5V_EN
TBT_POC_RESET
PP20V_USBC_XA_VBUS29 
GND105 104 103 31 29 
P3V3_TBT_X_SX_EN_R 33 
PP5V_S4_X_USBC29 
PP3V3_G3H109 
PP3V3_UPC_XA_LDO29 
GND
SMC_PME_S4_DARK_L
USBC_XA_CC1
USB3_EXTA_D2R_N
USB3_EXTA_R2D_N
USB3_EXTA_R2D_P
USB3_EXTA_D2R_P
USB2_UPC_XA_P
USB2_UPC_XA_N
VOLTAGE=20V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900 VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.0900
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.2000
27 113 
27 113 
5 84 13 2
Q3100
FDPC4044
PWR-CLIP-33
CRITICAL
29 31 
29 
27 29 
29 
29 31 103 104 105 
29 
29 
29 
29 
29 
29 
29 
29 
29 
29 31 
29 
29 
32 115 
32 115 
29 
29 
29 32 
2
1 C3105
0201-1
X5R
6.3V
20%
1.0UF
29 
29 
29 
2
1 C3100
0402-1
6.3V
20%
10UF
CERM-X5R
21 R3105
5% MF1/20W
1M
201
2
1R3110
1/20W
201
5%
MF
NO_XNET_CONNECTION=1
100K
2
1R3111
MF
NO_XNET_CONNECTION=1
100K
5%
1/20W
201
H2H1 B1K1
1
J1
1
J1
0
H1
1
L5
K5
E2
F2
F4
G4
H7
B3
B4
A4
A3
B10
A10
K10
K9
F11
G2
B7A8A7A6 H1
0
D1
1
C1
1
B1
1
A1
1
L11
E11
L4
K4
E1G
1
A2K1
A5
D1
B5
D2
B6
C1
F1
A9
B9
H6
D7
G10
E10
C10
G11
D10
C2
B2
G
7
G
6F8F7F6E8D8B8L1H8G
8H5H4G
5F5E7E6E5D6A1
D5
E4
K3
L3
K2
L2
K6
L6
K7
L7
L8
K8
L10
L9
F10
J1
J2
U3100
CD3215A
CRITICAL
OMIT_TABLE
BGA
GROUND
2
1 C3114
16V
220PF
CER-X7R
0201
10%
2
1 C3113
220PF
16V
0201
CER-X7R
10%
2
1 C3109
0201
0.47UF
10%
6.3V
CERM-X5R
2
1R3103
TF-LF
0201
0.1%
15K
1/20W
CRITICAL
2
1 C3106
CERM-X5R
0201
6.3V
0.47UF
10%
29 
29 
21 R31091M
5% 201MF1/20W
21 R3108
1/20W
1M
5% 201MF
27 29 31 
27 29 31 
29 30 31 
27 
27 
4
32
1
PLACE_NEAR=U3100:5mm
29 
29 
32 
32 
32 
32 
2
1 C3101
35V
X5R
0402
1UF
10%
2
1 C3104
20%
X5R-CERM
0201
4V
2.2UF
2
1 C3108
0402-1
CERM-X5R
6.3V
10UF
20%
SYNC_DATE=08/08/2016SYNC_MASTER=X362_GKOO
BOM_COST_GROUP=USB-C
USB-C PORT CONTROLLER A
TP_Q3100_DRAIN
UPC_XA_UART_RX
I2C_UPC_XA_DBG_CTL_SCL
I2C_UPC_XA_DBG_CTL_SDA
UPC_XA_GATE2
I2C_UPC_XA_DBG_CTL_SCL
TBT_XA_LSTX
USBC_XA_SBU2
USBC_XA_SBU1
TP_UPC_XA_SWD_CLK
TP_UPC_XA_SWD_DATA
I2C_UPC_XA_DBG_CTL_SDA
UPC_XA_SS
UPC_XA_DBG_UART_RX
UPC_XA_HPD_RX
DP_XA_HPD
UPC_XA_GATE1
UPC_XA_R_OSC
UPC_XA_DBG_UART_TX
UPC_XA_FAULT_L
USBC_XA_USB_DBG_TOP_P
USBC_XA_USB_DBG_TOP_N
USBC_XA_USB_DBG_BOT_P
USBC_XA_USB_DBG_BOT_N
DP_XA_AUXCH_P
USB_UPC_XA_F_N
DP_XA_AUXCH_N
TBT_XA_LSRX
UPC_XA_UART_RX
UPC_XA_UART_TX
USB_UPC_XA_F_P
PP20V_USBC_XA_VBUS_F
PP1V1_UPC_XA_LDO_BMC
PP1V8_UPC_XA_LDOD
PP1V8_UPC_XA_LDOA
PP3V3_UPC_XA_LDO
USBC_XA_CC1
USBC_XA_CC2
EXCX4CE
90-OHM-0.1A
L3000
29 30 31 
29 30 
29 3029 30 
29 
29 
29 30 
29 
114 
29 
29 
114 
29 
29 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
BI
BI
BI
BI
BI
BI
SYM_VER-1
IN
OUT
IN
IN
IN
BI
BI
H
V
 F
E
T
/S
E
N
S
E
P
O
R
T
 M
U
X
D
IG
IT
A
L 
C
O
R
E
 I/
O
 A
N
D
 C
O
N
T
R
O
L
T
Y
P
E
-C
HV_GATE2
PP
_5
V0
C_USB_BP
GPIO3
RESET*
DEBUG_CTL1
I2C_SDA1
I2C_IRQ1*
I2C_SDA2
LSX_R2P
LSX_P2R
C_SBU2
C_SBU1
C_USB_BN
C_USB_TN
C_USB_TP
RPD_G2
RPD_G1
UART_TX
USB_RP_P
SENSEP
SENSEN
UART_RX
SWD_CLK
SWD_DATA
SPI_SSZ
SPI_CLK
SPI_MOSI
I2C_SCL2
I2C_IRQ2*
I2C_SCL1
DEBUG_CTL2
BUSPOWERZ
C_CC2
C_CC1
SPI_MISO
NC
AUX_P
AUX_N
USB_RP_N
SS
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
DEBUG1
DEBUG3
DEBUG2
DEBUG4
GPIO1
GPIO2
GPIO5
GPIO4
GPIO6
MRESET
VB
US
VB
US
VB
US
VB
US
PP
_H
V
PP
_H
V
PP
_H
V
PP
_5
V0
PP
_5
V0
PP
_H
V
PP
_5
V0
LD
O
_B
M
C
LD
O
_1
V8
D
LD
O
_1
V8
A
VO
UT
_3
V3
PP
_C
AB
LE
LD
O
_3
V3
VI
N_
3V
3
VD
DI
O
HV_GATE1
I2C_ADDR
R_OSC
GPIO0
GPIO8
GPIO7
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
OUT
OUT
BI
BI
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
G
1
G
2
S2 S1
BI
BI
SECONDARY ACE USB-C PORT CONTROLLER (UPC)
PRESENT FOR GPIO0, GPIO1
support page
FUSE
TESTPOINTS MUST BE
PU to PP3V3_S4 if convenient
MAX 100uF TOTAL ON RAIL
NC or GND to dissipate heat
NEED 0.1%
CAN GROUND PIN D6 IN PRODUCTION
PIN D6 IS UNDOCUMENTED RESET
for layout.
REAR PORT:
CAP FOR PP_5V0 ON VR PAGE
TO SMC
VOUT_3V3 FOR RIDGE,
OR FLOAT IF UNUSED
Otherwise PU to PP3V3_UPC_XA_LDO
FRONT PORT:
Add on 
PULL R3209 AND R3208 UP TO ACEs LDOs FOR 1ST RIDGE'S ACES
PULL R3209 AND R3208 DOWN TO GND FOR 2ND RIDGE'S ACES
(EVEN IN PRODUCTION)
GROUND UPC SPI
CONNECT UPC SPI TO ROM
32 OF 145
31 OF 121
10.0.0
051-00647
dvt-fab10
USBC_X_RESET_L_R
TBT_POC_RESET
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
SMC_DEBUGPRT_TX_L
SOC_SWDIO_DBG
SOC_SWCLK_DBG
PP3V3_UPC_XB_LDO 29 
SMC_DEBUGPRT_RX_L
I2C_TBT_XB_INT_L
USB2_UPC_XB_N
SMC_USBC_INT_L
USB2_UPC_XB_P
PP5V_S4_X_USBC29 
GND
PP3V3_S429 
GND 29 
I2C_TBT_X_SDA
I2C_TBT_X_SCL
I2C_UPC_X_SDA2
USBC_XB_CC1
USBC_XB_CC2
SMC_PME_S4_DARK_L
P3V3_TBT_X_SX_EN_R 33 
I2C_UPC_X_SCL2
GND
MIN_NECK_WIDTH=0.1200
VOLTAGE=20V
MIN_LINE_WIDTH=0.2000
PP3V3_G3H109 
PP3V3_UPC_XB_LDO29 
PP20V_USBC_XB_VBUS29 
TBT_X_CIO_PWR_EN
TBT_X_USB_PWR_EN
UPC_X_5V_EN
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
PPDCIN_G3H 29 30 103 104 105 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
TP_UPC_XB_SWD_CLK
UPC_XA_UART_RX
UPC_XB_GATE2
USBC_XB_CC2
PP3V3_UPC_XB_LDO
PP1V1_UPC_XB_LDO_BMC
DP_XB_AUXCH_N
DP_XB_AUXCH_P
I2C_UPC_XB_DBG_CTL_SCL
NC_UPC_XB_I2C_ADDR
UPC_XB_R_OSC
UPC_XA_UART_TX
UPC_XB_SPI_MOSI
UPC_XB_SPI_CS_L
UPC_XB_SPI_MISO
UPC_XB_SPI_CLK
USBC_XB_USB_TOP_P
USB_UPC_XB_F_N
UPC_XB_FAULT_L
TBT_XB_LSRX
I2C_UPC_XB_DBG_CTL_SDA
UPC_XB_SS
USBC_XB_SBU2
USBC_XB_SBU1
USBC_XB_USB_BOT_N
USBC_XB_USB_BOT_P
USBC_XB_USB_TOP_N
UPC_XA_UART_TX
I2C_UPC_XB_DBG_CTL_SCL
UPC_XB_HPD_RX
TBT_XB_LSTX
USB_UPC_XB_F_P
I2C_UPC_XB_DBG_CTL_SDA
TP_UPC_XB_SWD_DATA
PP20V_USBC_XB_VBUS_F
UPC_XB_GATE1
TP_Q3200_DRAIN
TP_UPC_XB_DBG_UART_TX
DP_XB_HPD
TP_UPC_XB_DBG_UART_RX
PP1V8_UPC_XB_LDOA
PP1V8_UPC_XB_LDOD
USBC_XB_CC1
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
USB-C PORT CONTROLLER B
BOM_COST_GROUP=USB-C
29 
29 
32 
32 
32 
32 
115 32 
115 32 
30 29 
27 
29 
29 
29 
29 
29 
105 104 103 30 29 
29 
27 
PWR-CLIP-33
FDPC4044
CRITICAL
Q3200
23 14 85
113 27 
0402-1
10UF
CERM-X5R
6.3V
20%
C32081
2
4V
X5R-CERM
2.2UF
0201
20%
C32041
2
113 27 
30 29 27 
30 29 27 
33 
30 29 
1M
1/20W5% MF 201
R32081 2
2011/20W MF
1M
5%
R32091 2
29 
29 
29 
29 
29 
29 
EXCX4CE
90-OHM-0.1A
PLACE_NEAR=U3200.K5:5mm
PLACE_NEAR=U3200.L5:5mm
L3200
1
2 3
4
29 
29 
42 
42 
0.47UF
CERM-X5R
10%
6.3V
0201
C32061
2
35V
10%
0402
X5R
1UF
C32011
2
6.3V
CERM-X5R
0.47UF
10%
0201
C32091
2
TF-LF
CRITICAL
15K
0.1%
1/20W
0201
R32031
2
CER-X7R
16V
220PF
10%
0201
C32131
2
220PF
16V
CER-X7R
10%
0201
C32141
2
CD3215A
OMIT_TABLE
BGA
CRITICAL
GROUND
U3200
J2
J1
F10
L9
L10
K8
L8
L7
K7
L6
K6
L2
K2
L3
K3
E4
D5
A1 D6 E5 E6 E7 F5 G
5 H4 H5 G
8 H8 L1 B8 D8 E8 F6 F7 F8 G
6
G
7
B2
C2
D10
G11
C10
E10
G10
D7
H6
B9
A9
F1
C1
B6
D2
B5
D1
A5
K1 A2G
1
E1
K4
L4
E11
L11
A1
1
B1
1
C1
1
D1
1
H1
0
A6 A7 A8 B7
G2
F11
K9
K10
A10
B10
A3
A4
B4
B3
H7
G4
F4
F2
E2
K5
L5
H1
1
J1
0
J1
1
K1
1
B1H1 H2
MF
5%
1/20W
100K
201
NO_XNET_CONNECTION=1
R32111
2
100K
5%
MF
1/20W
201
NO_XNET_CONNECTION=1
R32101
2
5%
1M
201MF1/20W
R32051 2
10UF
0402-1
CERM-X5R
6.3V
20%
C32001
2
29 
29 
29 
32 29 
32 29 
6.3V
X5R
0201-1
1.0UF
20%
C32051
2
27 
29 
29 
31 
29 
31 30 29 
31 
31 30 29 
31 
29 
31 
29 
29 
114 29 
114 29 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
BI
IN
OUT
OUT
OUT
OUT
NC
G
1
G
2
S2 S1
BI
BI
BI
BI
OUT
IN
OUT
IN
OUT
OUT
BI
BI
SYM_VER-1
BI
BI
BI
BI
H
V
 F
E
T
/S
E
N
S
E
P
O
R
T
 M
U
X
D
IG
IT
A
L 
C
O
R
E
 I/
O
 A
N
D
 C
O
N
T
R
O
L
T
Y
P
E
-C
HV_GATE2
PP
_5
V0
C_USB_BP
GPIO3
RESET*
DEBUG_CTL1
I2C_SDA1
I2C_IRQ1*
I2C_SDA2
LSX_R2P
LSX_P2R
C_SBU2
C_SBU1
C_USB_BN
C_USB_TN
C_USB_TP
RPD_G2
RPD_G1
UART_TX
USB_RP_P
SENSEP
SENSEN
UART_RX
SWD_CLK
SWD_DATA
SPI_SSZ
SPI_CLK
SPI_MOSI
I2C_SCL2
I2C_IRQ2*
I2C_SCL1
DEBUG_CTL2
BUSPOWERZ
C_CC2
C_CC1
SPI_MISO
NC
AUX_P
AUX_N
USB_RP_N
SS
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
DEBUG1
DEBUG3
DEBUG2
DEBUG4
GPIO1
GPIO2
GPIO5
GPIO4
GPIO6
MRESET
VB
US
VB
US
VB
US
VB
US
PP
_H
V
PP
_H
V
PP
_H
V
PP
_5
V0
PP
_5
V0
PP
_H
V
PP
_5
V0
LD
O
_B
M
C
LD
O
_1
V8
D
LD
O
_1
V8
A
VO
UT
_3
V3
PP
_C
AB
LE
LD
O
_3
V3
VI
N_
3V
3
VD
DI
O
HV_GATE1
I2C_ADDR
R_OSC
GPIO0
GPIO8
GPIO7
OUT
BI
BI
BI
BI
OUT
TBT_D2R0
CC2
TBT_R2D1
SBU2 
CC1 
USB2 BOT
PLACE VBUS CAP NEAR EACH VBUS PIN
SBU1 
TBT_D2R1
SBU2
CC1
TBT_R2D0
CC2
TBT_R2D1
SBU1
USB2 TOP
LAST CHANGE: Wed Apr 1 22:57:37 2015
PLACE VBUS CAP NEAR EACH VBUS PIN
TBT_D2R0
TBT_D2R1
USB2 BOT
USB2 BOT
TBT_R2D0
32 OF 121
VOLTAGE=20V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=20V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000
VOLTAGE=20V
MIN_NECK_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
VOLTAGE=20V
33 OF 145
10.0.0
051-00647
dvt-fab10
USBC_XA_R2D_P<1>
USBC_XB_R2D_N<1>
USBC_XB_USB_TOP_P
USBC_XA_D2R_P<1>
USBC_XB_R2D_C_N<2>
USBC_XA_SBU1
USBC_XB_D2R_N<2>
USBC_XB_USB_TOP_N
USBC_XB_R2D_C_P<2>
USBC_XA_R2D_C_N<1>
USBC_XA_R2D_C_N<2>
USBC_XB_R2D_C_P<1>
USBC_XA_R2D_C_P<1>
USBC_XA_R2D_C_P<2>
USBC_XB_R2D_C_N<1>
USBC_XB_D2R_P<2>
USBC_XA_USB_DBG_TOP_N
USBC_XA_D2R_N<1>
USBC_XA_R2D_N<1>
USBC_XA_USB_DBG_TOP_P
USBC_XB_R2D_P<2>
PP20V_USBC_XA_VBUS_CONNUSBC_XB_CC1
USBC_XA_CC2
USBC_XB_SBU2
USBC_XB_D2R_N<1>
USBC_XA_R2D_N<2>
USBC_XA_R2D_P<2>
USBC_XB_D2R_P<1>
USBC_XB_R2D_P<1>
USBC_XB_USB_BOT_P
USBC_XB_R2D_N<2>
USBC_XA_SBU2
PP20V_USBC_XA_VBUS PP20V_USBC_XA_VBUS_CONN
PP20V_USBC_XB_VBUS PP20V_USBC_XB_VBUS_CONN
USBC_XA_CC1
TP_J3300_P56
USBC_XA_D2R_P<2>
USBC_XA_D2R_N<2>
TP_J3300_P2
USBC_XB_CC2
USBC_XB_USB_BOT_N
USBC_XA_USB_DBG_BOT_N
USBC_XA_USB_DBG_BOT_P
USBC_XB_SBU1
NOSTUFF138S0683 CAP,CER,X5R,1UF,10%,25V,04022 C3304, C3354 CRITICAL
BOM_COST_GROUP=USB-C
SYNC_DATE=03/30/2016SYNC_MASTER=X362_MLB
USB-C CONNECTOR A
SM
XW3300
12
SM
XW3350
12
114 
114 
F-ST-SM
20759-056E-02
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
J3300
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
NSR20F40NX_G
CRITICAL
DSN2
D3370
A
K
DSN2
CRITICAL
NSR20F40NX_G
D3300
A
K
ESDA25P35-1U1M
1610
D3302
A
K
ESDA25P35-1U1M
1610
D3301
A
K
02
01
-T
HI
CK
ST
NC
L
5.
5V
-6
.2
PF
DZ
33
50
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
36
0
1
2
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
D3
35
7
1
2
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
D3
35
9
1
2
GND_VOID=TRUE
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
35
8
1
2
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
GND_VOID=TRUE
D3
35
6
1
2
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
GND_VOID=TRUE
D3
35
5
1
2
5.
5V
-6
.2
PF
02
01
-T
HI
CK
ST
NC
L
DZ
33
02
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
32
9
1
2
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
GND_VOID=TRUE
D3
32
2
1
2
GND_VOID=TRUE
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
32
3
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
30
4
1
2
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
GND_VOID=TRUE
D3
32
0
1
2
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
D3
32
1
1
2
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
D3
32
8
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
31
2
1
2
GND_VOID=TRUE
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
32
4
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
32
5
1
2
X3
DF
N2
-T
HI
CK
ST
NC
L
ES
D8
01
1
GND_VOID=TRUE
D3
32
6
1
2
X3
DF
N2
-T
HI
CK
ST
NC
L
GND_VOID=TRUE
ES
D8
01
1
D3
32
7
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
35
0
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
35
1
1
2
X3
DF
N2
-T
HI
CK
ST
NC
LGND_VOID=TRUE
ES
D8
01
1
D3
35
2
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
35
4
1
2
ES
D8
01
1
X3
DF
N2
-T
HI
CK
ST
NC
L
GND_VOID=TRUE
D3
34
9
1
2
ES
D8
01
1
GND_VOID=TRUE
X3
DF
N2
-T
HI
CK
ST
NC
L
D3
35
3
1
2
GND_VOID=TRUE
0.22UF
6.3V10% X5R-CERM 0201
GND_VOID=TRUE
C3391 1 2
6.3V
0.22UF
10%
GND_VOID=TRUE
0201
GND_VOID=TRUE
X5R-CERM
C3390 1 2
0.22UF
0201X5R-CERM6.3V
GND_VOID=TRUE
10%
GND_VOID=TRUE
C3373 1 2
GND_VOID=TRUE
02016.3V
0.22UF
X5R-CERM
GND_VOID=TRUE
10%
C3372 1 2
X5R-CERM10%
GND_VOID=TRUE
0201
GND_VOID=TRUE
0.22UF
6.3V
C3371 1 2
GND_VOID=TRUE
0.22UF
6.3V10% 0201
GND_VOID=TRUE
X5R-CERM
C3370 1 2
0201
GND_VOID=TRUE
0.22UF
10% 6.3V
GND_VOID=TRUE
X5R-CERM
C3393 1 2
GND_VOID=TRUE
0.22UF
GND_VOID=TRUE
0201X5R-CERM6.3V10%
C3392 1 2
31 29 
113 27 
113 27 
31 
31 
113 27 
113 27 
115 31 
115 30 
113 27 
113 27 
30 
30 
113 27 
113 27 
30 29 
25V
0201
0.01UF
10%
X5R-CERM
CRITICAL
BYPASS=J3300.58::2MM
C33551
2
CRITICAL
0.01UF
0201
X5R-CERM
BYPASS=J3300.58::2MM
25V
10%
C33621
2
BYPASS=J3300.58::2MM
10%
X5R-CERM
0201
CRITICAL
25V
0.01UF
C33531
2
BYPASS=J3300.58::2MM
0.01UF
10%
X5R-CERM
25V
CRITICAL
0201
C33591
2
0201
X5R-CERM
0.01UF
BYPASS=J3300.58::2MM
10%
25V
CRITICAL
C33521
2
0201
BYPASS=J3300.58::2MM
X5R-CERM
0.01UF
25V
10%
CRITICAL
C33581
2
25V
10%
0.01UF
X5R-CERM
BYPASS=J3300.58::2MM
CRITICAL
0201
C33511
2
0.01UF
CRITICAL
X5R-CERM
10%
25V
0201
BYPASS=J3300.58::2MM
C33501
2
X5R-CERM
BYPASS=J3300.58::2MM
25V
0.01UF
10%
CRITICAL
0201
C33571
2
BYPASS=J3300.58::2MM
25V
CRITICAL
0.01UF
X5R-CERM
10%
0201
C33561
2
02
01
-T
HI
CK
ST
NC
L
5.
5V
-6
.2
PF
DZ
33
53
1
2
5.
5V
-6
.2
PF
02
01
-T
HI
CK
ST
NC
L
DZ
33
51
1
2
5.
5V
-6
.2
PF
02
01
-T
HI
CK
ST
NC
L
DZ
33
00
1
2
CRITICAL
0201
25V
0.01UF
10%
X5R-CERM
BYPASS=J3300.59::2MM
C33051
2
BYPASS=J3300.59::2MM
X5R-CERM
0.01UF
10%
CRITICAL
0201
25V
C33121
2
402
X5R
OMIT_TABLE
10%
25V
1UF
C3354 1
2
113 27 
113 27 
113 27 
31 
115 31 
31 
31 29 
02
01
-T
HI
CK
ST
NC
L
5.
5V
-6
.2
PF
DZ
33
01
1
2
5.
5V
-6
.2
PF
02
01
-T
HI
CK
ST
NC
L
DZ
33
52
1
2
5.
5V
-6
.2
PF
02
01
-T
HI
CK
ST
NC
L
DZ
33
03
1
2
0.01UF
CRITICAL
X5R-CERM
0201
25V
BYPASS=J3300.59::2MM
10%
C33031
2
BYPASS=J3300.59::2MM
CRITICAL
10%
0.01UF
25V
0201
X5R-CERM
C33091
2
0.01UF
X5R-CERM
0201
25V
10%
CRITICAL
BYPASS=J3300.59::2MM
C33021
2
10%
X5R-CERM
0201
BYPASS=J3300.59::2MM
CRITICAL
25V
0.01UF
C33081
2
25V
CRITICAL
BYPASS=J3300.59::2MM
X5R-CERM
0.01UF
10%
0201
C33011
2
X5R-CERM
CRITICAL
BYPASS=J3300.59::2MM
0201
0.01UF
25V
10%
C33071
2
BYPASS=J3300.59::2MM
X5R-CERM
CRITICAL
25V
0.01UF
0201
10%
C33001
2
0201
CRITICAL
0.01UF
X5R-CERM
10%
25V
BYPASS=J3300.59::2MM
C33061
2
30 
30 29 
30 
115 30 
113 27 
113 27 
113 27 
1UF
25V
X5R
10%
402
OMIT_TABLE
C3304 1
2
116 115 114 32 
29 
29 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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PAGE TITLE
C
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
OUT
OUT
PWR
PWR
SIGNAL
GND
BI
IN
IN
BI
BI
OUT
OUT
BI
BI
IN
IN
BI
BI
OUT
OUT
BI
OUT
OUT
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
IN
. 
DESIGN: X502/DEV_MLB_U
LAST CHANGE: Wed Feb 18 17:12:24 2015
Push-pull
440us +/- 20us
2.508V nominal
U3401
Vth 
Delay
Output
TBT X "POC" Power-up Reset
33 OF 121
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200P3V3_TBT_X_SX_EN_R
P3V3_TBT_X_SX_EN_R
USBC_X_RESET_L_R
PP3V3_S5 110 116 
PP3V3_S5_TBT_X_SW 28 29 
PP3V3_S5_TBT_X_SW 27 
34 OF 145
10.0.0
051-00647
dvt-fab10
PP3V3_S5_TBT_X_SW
MAKE_BASE=TRUE
P3V3_TBT_X_SX_EN
TBTXPOCRST_SNS TBTXPOCRST_CT
MAKE_BASE=TRUE
P3V3_TBT_X_SX_EN_R
USBC_X_RESET_L_R
MAKE_BASE=TRUE
USBC_X_RESET_L
USB-C CONNECTOR B
BOM_COST_GROUP=USB-C
SYNC_MASTER=X362_MLB SYNC_DATE=03/29/2016
100K
201
MF
1/20W
1%
R34021
2
MF
5%
100K
1/20W
201
R34041
2
C0G
25V
5%
100PF
0201
C3400 1
2
201
MF
0
5%
1/20W
R3401
1 231 
30 
1.0UF
20%
X5R
NOSTUFF
0201-1
6.3V
C34311
2
31 
MF
1/20W
NOSTUFF
5%
10K
201
R3431
1 2
DSF01S30SCAP
SC2
NOSTUFF
D3400
AK
4020
MF-LF 1/16W5%
NOSTUFF
R3400
1 2
CRITICAL
USON
TPS3895ADRY
U3401
5
1
2
3
4
6
201
24.9K
1%
1/20W
MF
R34031
2
29 27 
CRITICAL
STDFN
SLG5AP1449V
U3400
2
4
1
3
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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SHEET
PAGE TITLE
C
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NOTICE OF PROPRIETARYPROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
VCC
CT
SENSE_OUTENABLE
SENSE
GND
OUT
ON
S
D
GND
Vout = 5.23V
Freq = 500 kHz
Max OCP = 13.9A
Nom OCP = 11.6A
Min OCP = 9.37A
34 OF 121
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
GATE_NODE=TRUE
PP5V_S4_X_USBC29 34 116 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=5V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
PP5V_S4108 110 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
GATE_NODE=TRUE
DIDT=TRUE
PP5V_S4_X_USBC 29 34 116 
PPBUS_G3H
108 109 116 
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
35 OF 145
10.0.0
051-00647
dvt-fab10
P5VUSBCX_SET_R
P5VUSBCX_VO
P5VUSBCX_SET0
P5VUSBCX_SREF P5VUSBCX_LL
P5VUSBCX_P
P5VUSBCX_DRVH_R
P5VUSBCX_DRVH
P5VUSBCX_RTN_DIV_R P5VUSBCX_SENSE_DIV_R
PP5V_USBCX_VCC
P5VUSBCX_BOOT_RC
P5VUSBCX_FSEL
UPC_X_5V_EN
P5VUSBCX_R
P5VUSBCX_VBST
P5VUSBCX_SET1
P5VUSBCX_OCSET
P5VUSBCX_DRVL
P5VUSBCX_SENSE_DIV
P5VUSBCX_RTN_DIV
P5VUSBCX_AGND
P5VUSBCX_N
BOM_COST_GROUP=USB-C
TBT 5V REGULATOR
SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN SYNC_DATE=12/04/2015
0402-1
10UF
X5R-CERM
10V
20%
C35211
2
2.2
1/20W
MF
201
5%
R3501 1
2
1%
0.002
1/2W
MF
0306
CRITICAL
NO_XNET_CONNECTION=1
R3530
1 2
3 4
CER-X7R
10%
0201
25V
2200PF
NO_XNET_CONNECTION=1
C3570
12
MF
201
2.74K
1%
1/20W
R35721
2
2.74K
201
MF
1/20W
1%
R35211
2
SM
PLACE_NEAR=U3500.2:1mm
XW3500
1 2
29 
ISL95870AH
CRITICAL
UTQFN
U3500
1815
10
13
3
1
11
2
14
16
20
4
8
9
7
17
19
6
5
12
5%
MF
NOSTUFF
201
1/20W
0
R3513 1
2
10%
10V
0402
X6S-CERM
2.2UF
C35221
2
1/20W
MF
0201
191K
0.1%
R35171
2
10%
0.1UF
16V
X5R-CERM
0201
C3523 1
2
95.3K
MF
1/20W
0201
0.1%
R35181
2
1%
1/20W
MF
11K
201
R3500
1 2
5%
50V
C0G
0201
10PF
C35151
2
1/20W
0.1%
10K
0201-1
MF
R35021
2
0.1%
27.4K
1/20W
MF
0201
NO_XNET_CONNECTION=1
R35311
2
0.1%
27.4K
0201
1/20W
MF
NO_XNET_CONNECTION=1
R35031
2
1/20W
0.1%
10K
0201-1
MF
R35041
2
10PF
5%
50V
0201
C0G
C35261
2
50V
22PF
C0G
5%
0201
C35171
2
SM
XW3502
1
2
SM
XW3501
1
2
25V
20%
X5R-CERM
0402-1
2.2UF
C3506 1
2
2.2UF
X5R-CERM
0402-1
20%
25V
C35011
2
0402-1
2.2UF
25V
20%
X5R-CERM
C3505 1
2
25V
X5R-CERM
2.2UF
0402-1
20%
C35001
2
LLP
FDPC1012S
CRITICAL
Q3501
5 6 10
1
7
2
3
4
8
9
150UF
20%
6.3V
TANT-POLY
CASE-B1S-1
C35071
26.3V
20%
TANT-POLY
150UF
CASE-B1S-1
C35081
2
20%
TANT-POLY
6.3V
150UF
CASE-B1S-1
C35091
2
CRITICAL
PIMB062D-SM
1.5UH-20%-12.5A-0.017OHM
L3500
1 2
CRITICAL
CASE-B3
33UF
TANT-POLY
16V
20%
C3502 1
2
CRITICAL
TANT-POLY
20%
16V
CASE-B3
33UF
C3503 1
2
CRITICAL
TANT-POLY
16V
CASE-B3
33UF
20%
C3504 1
2
10%
X7R-CERM
0.1UF
16V
0402
C35161
2
1/20W
5%
0
MF
0201
R3539
12
201
MF
5%
2.2
1/20W
R35091
2
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
C
A
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
SREF
VID0
RTN
FSEL
SET0
PVCCVCC
BOOT
UGATE
LGATE
PHASE
PGNDGND
EN
VO
FB
OCSET
PGOOD
SET1
VID1
NC
SW
LSG
V+
V+
HSG
G
ND
G
ND
G
ND
PLACE ON THE TOP SIDE CLOSE TO U3730
SROM_STRAPS
DEBUG CONNECTOR
STRAP_1 LO:16kb SROM
BLUETOOTH SERIAL FLASH
WLAN SERIAL EEPROM
BT UART RX & CTS ISOLATION CIRCUIT
FOR JTAG MODE REMOVE R3735
FEM SUPPLY SHUNT CAPACITORS
BT UART TX & RTS ISOLATION CIRCUIT
STRAP_0 HI:SROM (Default)
051-00647
dvt-fab10
35 OF 121
10.0.0
37 OF 145
PP3V3_S4_WLAN_SW 35 
BT_LOW_PWR_L 35 
SMC_PME_S4_DARK_L 35 48 
PP3V3_S4_BT35 
PP3V3_S4_WLAN_SW35 
PP3V3_S4_WLAN_SW 35 
PP3V3_S4_WLAN_SW 35 
PP3V3_S4_WLAN_SW35 
PP3V3_S435 110 
PP3V3_S4_BT35 
PP3V3_S4_WLAN_SW 35 
VOLTAGE=3.3V
PP3V3_S4_BT 35 
PP3V3_S4_BT 35 
PP3V3_S4_BT 35 
PP3V3_S4_WLAN_SW35 PP3V3_S4_BT 35 PP3V3_S4_WLAN_SW 35 
BT_LOW_PWR_L35 
PP3V3_S4_WLAN_SW 35 
PP3V3_S435 110 
SMC_PME_S4_DARK_L
PP3V3_S4_WLAN_SW35 
PP3V3_S4_BT 35 
BT_ROM_BOOT_L
PP3V3_S4_BT
PP3V3_S4_BT 35 
BT_TIMESTAMP BT_TIMESTAMP
MAKE_BASE=TRUE
BT_UART_D2R
BT_SPI2_MISO
WLAN_JTAG_TCK
BT_SPI2_MOSI
BT_SWDIO
SMC_BT_PWR_EN
CORE2_5G_CTL2_WLAN_JTAG_TDO
WLAN_JTAG_SEL
AP_CLKREQ_L
AP_PCIE_WAKE_L
BT_UART_R2D
BT_UART_CTS_R2D_L
BT_UART_D2R
BT_UART_CTS_R2D_LPCH_BT_UART_RTS_L
PCIE_AP_R2D_C_P
WLAN_STRAP_1
WLAN_JTAG_TMS
WLAN_JTAG_TDI
AP_RESET_L
WLAN_UART_RX
WLAN_STRAP_0
BT_SFLASH_CS_L
BT_SPI2_CLK
BT_SFLASH_HOLD_L
BT_SFLASH_WP_L
PLT_RST_L
BT_UART_R2D
PLT_RST_L
PCH_BT_UART_R2D
BT_SPI2_CSN
BT_UART_CTS_R2D_L
BT_UART_R2D
WLAN_UART_TX
BT_UART_RTS_D2R_L
SMC_WIFI_PWR_EN
BT_SPI2_CSN
BT_SPI2_MOSI
BT_SPI2_CLK
BT_ROM_BOOT_L
MAKE_BASE=TRUE
BT_SPI2_MISO
MAKE_BASE=TRUE
PP3V3_S4_WLAN_SW
PCH_BT_UART_D2R
PCH_BT_UART_CTS_L
PP3V3_S4_BT
MAKE_BASE=TRUE
PCIE_AP_R2D_C_N
PCH_BT_ROM_BOOT
BT_LOW_PWR_L
MAKE_BASE=TRUE
50_G_1_MATCH
50_A_0_MATCH
BT_UART_R2D
WLAN_1P2V_EN
50_G_0_MATCH
50_G_2_MATCH
50_A_2_MATCH
WLAN_UART_RX
WLAN_UART_TX
WLAN_JTAG_TDI
SMC_BT_PWR_EN
BT_ROM_BOOT_L
BT_TIMESTAMP
50_A_1_MATCH
WLAN_JTAG_TCK
WLAN_JTAG_TMS
CORE2_5G_CTL2_WLAN_JTAG_TDO
WLAN_EXT_POR_L
WLAN_JTAG_TRST_L
PCIE_AP_D2R_P
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_P
SPROM_CLK
SPROM_CS
BT_SPI2_CLK
SPROM_DIN
WLAN_STRAP_0
SPROM_DOUT
BT_SPI2_MISO
BT_SPI2_MOSI
BT_I2S_CLK
BT_I2S_D2R
WLAN_JTAG_SEL
WLAN_JTAG_TRST_L
BT_SWDIO
BT_SWDCLK
BT_UART_RTS_D2R_L
BT_UART_CTS_R2D_L
BT_UART_RTS_D2R_L
WLAN_STRAP_1
BT_UART_RTS_D2R_L
BT_UART_D2R
BT_UART_D2R
SPROM_CS
SPROM_CLK
WIFI_SROM_ORG
SPROM_DINSPROM_DOUT
AP_RESET_CONN_L
BT_RX_ACTIVE
AP_CLKREQ_L
AP_PCIE_WAKE_L
PCIE_CLK100M_AP_N
WL_CLK32K
PP3V3_S4_WLAN_SW
BT_I2S_SYNC
BT_I2S_R2D
BT_SWDCLK
SYSCLK_CLK32K_WIFIBT
SYSCLK_CLK32K_WIFIBT
BT_SPI2_CSN
BOM_COST_GROUP=WIRELESS
SYNC_DATE=04/29/2016SYNC_MASTER=X363_SAKKOC
WIFI/BT: MODULE 1
OMIT_TABLE
2MBIT
USON
MX25L2006EZUI-12G
U3750
1
4
7
6 5
2
9
8
3
113 36 
113 36 
113 36 
113 36 
113 36 
113 36 
DMN32D2LFB4
DFN1006H4-3
Q3702
3
1
2
48 35 
2011/20W
MF
5%
100K
R3777
12
201
100K
MF
5%
1/20W
R3776
12
5%
201
100K
1/20W
MF
R3767
12
201
100K
1/20W
MF
5%
R3766
12
15 
15 
NO STUFF
201
5%
0
MF
1/20W
R3775
1 2
NO STUFF
1/20W
201
MF
0
5%
R3774
1 2
NO STUFF
MF
0
5%
201
1/20W
R3765
1 2
1/20W
NO STUFF
201
MF
0
5%
R3764
1 2
CER-X5R
0.1UF
0201
10%
35V
C37741
2
74LVC2G126
CRITICAL
X2-DFN2010
U3770
2
5
4
1
7
8
6
3
114 35 20 12 
UDFN8
CAS93C86B
OMIT_TABLE
U3710
1
3 4
5
6
7
2
9
8
74LVC2G126
CRITICAL
X2-DFN2010
U3760
2
5
4
1
7
8
6
3
15 DMN32D2LFB4
DFN1006H4-3
Q3701
3
1
2
35V
CER-X5R
0201
0.1UF
10%
C37641
2
114 35 20 12 
35 20 
201
MF
5%
1/20W
270K
R37591
2
NOSTUFF
MF
1K
5%
1/20W
201
R37011
2
3.0PF
+/-0.1PF
NP0-C0G
0201
25V
C37631
2
+/-0.1PF
25V
3.0PF
0201
NP0-C0G
C37621
2
+/-0.1PF
0201
25V
NP0-C0G
3.0PF
C37611
2
NP0-C0G
12PF
5%
25V
0201
C37571
225VNP0-C0G
5%
0201
12PF
C37581
2
12PF
0201
NP0-C0G
5%
25V
C37421
2 NP0-C0G
0201
12PF
5%
25V
C37411
2
12PF
0201
NP0-C0G
5%
25V
C37401
2
12 
5%
MF
201
10K
R3762
12
10%
0.1UF
0201
X7R
6.3V
GND_VOID=TRUE GND_VOID=TRUE
C3760
12
6.3V
X7R
0201
0.1UF
GND_VOID=TRUE GND_VOID=TRUE
10%
C3759
12
0
5%
MF
1/20W
201
NO_XNET_CONNECTION=1
R3735
12
5%
MF
201
100K
1/20W
R37531
2
1/20W
100K
5%
MF
201
R37521
2
100K
1/20W
5%
201
MF
R37511
2
35 13 
10%
35V
CER-X5R
0.1UF
0201
C37021
2
WIFI_DBGAA25D-S038VA1
F-ST-SM
J3701
39 40
41 42
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
CERM-X5R
10UF
20%
0402-4
6.3V
C3739 1
2
5%
1K
1/20W
MF
201
R3754
1 2
MF
201
5%
10K
R3712
12
5%
10K
1/20W
201
MF
R37341
2
NOSTUFF
201
5%
10K
MF
1/20W
R37311
2
0201
0.1UF
10%
35V
CER-X5R
C37561
2
CER-X5R
35V
10%
0.1UF
0201
C37111
2
CER-X5R
35V
0.1UF
10%
0201
C37051
2
20%
10UF
CERM-X5R
6.3V
0402-4
C37041
2
0.1UF
CER-X5R
0201
35V
10%
C37011
2
0201
CER-X5R
10%
35V
0.1UF
C37031
2
0402-4
10UF
6.3V
20%
CERM-X5R
C37381
2
10UF
0402-4
20%
6.3V
CERM-X5R
C37371
2
10UF
0402-4
6.3V
20%
CERM-X5R
C37361
2
15 
LBEE5UQ1HG-844
LGA
U3730
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
LGA
LBEE5UQ1HG-844
U3730
95
47
63
78
61
74
85
35
29
28
27
33
34
30
53
50
52
49
45
31
43
66
59
65
58
56
57
41
42
36
37
32
25
91
90
1 3 5 8 11 14 18 20 26 38 39 40 44 46 48 51 54 60 62 64 67 69 73 75 76 77 79 80 82 83 84 86 87
16
17
7
6
12
13
9
10
15
97
99
100
98
2 5568 8189 96 88 24
22
23
94
71
93
72
70
19
4
21
92
113 14 
113 14 
113 14 
113 14 
113 12 
113 12 
35 19 
36 
15 
35 13 
35 
35 
35 
35 
35 
46 35 
35 
35 
35 20 
35 19 
35 
35 
35 
35 
35 
35 
35 
114 36 20 15 
48 35 
35 
35 
35 
35 
35 
35 
48 35 
35 
48 46 36 
35 
35 
35 
35 
35 
36 35 110 
35 
48 35 
48 35 
35 
46 35 
35 
35 
35 
35 
35 
113 
113 
35 
35 
35 
35 
35 
35 
35 
35 
13 
13 
35 
35 
35 
35 
35 
35 
35 
35 
35 
35 
35 
35 
35 
35 35 
36 35 
13 
13 
35 
35 20 
35 20 
35 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
R
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SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
PAD
VCC
CS*
HOLD*
WP*
SCLK
GND THRM
SO/SIO1
SI/SIO0
BI
BI
BI
BI
BI
BI
G
S
SYM_VER_3
D
OUT
IN
IN
GND
VCC
2OE
A2
1OE
Y2
Y1A1
IN
PE
CS
EPADGND
SK
VCC
ORG
DODI
GND
VCC
2OE
A2
1OE
Y2
Y1A1
IN
G
S
SYM_VER_3
D
IN
BI
IN
NC
NCIN
NC
OUT
NC
SYM 2 OF 2
THRM_PADTHRM_PAD
SYM 1 OF 2
2G_ANT_CORE1
5G_ANT_CORE0
VD
D3
P3
_F
EM
_C
O
RE
1
VD
D3
P3
_R
EG
1P
2
BT_UART_CTS*/BT_JTAG_TMS
BT_UART_RTS*/BT_JTAG_TCK
BT_UART_RXD/BT_JTAG_TDI
BT_UART_TXD/BT_JTAG_TDO
BT_RX_ACTIVE/BT_GPIO_5
PCIE_PRST*
PCIE_CLKREQ*
PCIE_WAKE_CL
VD
D_
BT
VD
D3
P3
_F
EM
_C
O
RE
2
1P
2V
_E
N
C2_FEMCTRL_2/STRAP_1
BT_RF1
2G_ANT_CORE0
2G_ANT_CORE2
5G_ANT_CORE2
WL_GPIO_6/UART_RX
WL_GPIO_7/UART_TX
WL_JTAG_TDI/GPIO_3
BT_RST*
BT_GPIO_3
BT_GPIO_4
BT_GPIO_2/BT_JTAG_TRST_N
5G_ANT_CORE1
WL_JTAG_TCK
WL_JTAG_TMS
WL_JTAG_TDO
WLAN_EXT_POR*
WL_JTAG_TRST*
BT
_V
DD
IO
VD
D3
P3
_F
EM
_C
O
RE
0
W
L_
VD
DI
O
PCIE_TDP
BT
_O
TP
_V
DD
3P
3V
VD
D3
P3
_R
EG
1P
8
PCIE_RDN
PCIE_RDP
PCIE_TDN
PCIE_REFCLK_PC
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
G
ND
SPROM_CLK
SPROM_CS
BT_SPI2_CLK
BT_SPI2_CSN
SPROM_DIN
C0_FEMCTRL_2/STRAP_0
SPROM_DOUT
BT_SPI2_MISO
BT_SPI2_MOSI
VD
D3
P3
PCIE_REFCLK_NC
BT_XTAL32
WL_XTAL32
BT_HOST_WAKE/BT_HOST_WAKE*
BT_DEV_WAKE
BT_PCM_IN
BT_PCM_SYNC
BT_PCM_CLK
BT_PCM_OUT
BT_SWDCLK
BT_SWDIO
G
ND
G
ND
G
ND
G
ND
G
ND
BT_JTAG_SEL
VD
D3
P3
_P
AD
WL_JTAG_SEL
IN
IN
OUT
OUT
IN
IN
OUT
IN
OUT
WLAN Power Switch
Supervisor & CLKREQ# Isolation
Delay = 130ms +/- 20%
CORE0 DIPLEXER AND MATCHING
CORE1 DIPLEXER AND MATCHING
CORE2 DIPLEXER AND MATCHING
dvt-fab10
36 OF 121
051-00647
10.0.0
38 OF 145
50_A_0_MATCH
50_G_0_MATCH
50_A_0_DIPLEXER
50_G_0_DIPLEXER
50_0_ANT
50_A_1_MATCH
50_G_1_MATCH
50_A_1_DIPLEXER
50_G_1_DIPLEXER
50_1_ANT
50_A_2_MATCH50_A_2_DIPLEXER
50_G_2_MATCH50_G_2_DIPLEXER
50_2_ANT
AP_RESET_CONN_L
PP3V3_S4_WLAN_SW
AP_RESET_CONN_R_L
SMC_WIFI_PWR_EN
WLAN_3V3_VMON
SMC_WIFI_PWR_EN
WIFI_SW_CAP
PP3V3_S4_WLAN
PP3V3_S4_WLAN_SW
PP3V3_S4_WLAN
AP_RESET_L
50_0_COM
50_1_COM
50_2_COM
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
WIFI/BT: MODULE 2
BOM_COST_GROUP=WIRELESS
114 35 20 15 
0.1UF
25V
10%
X6S-CERM
0201
C38511
2
SLG5AP1443V
TDFN
U3840
7 3
8
2 5
1
10V
X7R
10%
201
4700PF
C38411
2
48 
46 36 35 
5%
MF
1/20W
201
0
WIFI_SAK:NO
R3854
1 2
SLG4AP041V
TDFN
U3850
6
5
7
3
8
4
2
9
1
MF
1/20W
1%
232K
201
R38561
2
100K
5%
1/20W
MF
201
R38571
2
5%
0
201
MF
WIFI_SAK:YES
1/20W
R3859
1 235 
2.
8N
H-
+/
-0
.1
NH
-0
.6
A-
0.
12
OH
M
CR
IT
IC
AL
02
01
L3
81
3
1
2
0.8NH-+/-0.05NH-1.1A-0.04OHM
CRITICAL
0201
L3830
1 2
2.4NH+/-0.1NH-0.6A
0201
CRITICAL
L3831
1 2
2.
4N
H+
/-
0.
1N
H-
0.
6A
CR
IT
IC
AL
02
01
L3
82
3
1
2
2.
4N
H+
/-
0.
1N
H-
0.
6A
CR
IT
IC
AL
02
01
L3
83
3
1
2
0201
CRITICAL
2.4NH+/-0.1NH-0.6A
L3821
1 2
0.2PF
+/-0.05PF
25V
COG-CERM
0201
CRITICALC38361
2
CRITICAL
2.4NH+/-0.1NH-0.6A
0201
L3811
1 2
CRITICAL
0
1/20W
201
MF
5%
R3824
1 2
+/-0.05PF
NO STUFF
25V
0.2PF
COG-CERM
0201
C38201
2
CRITICAL
0
MF
1/20W
5%
201
R3814
1 2
0201
CRITICAL
0.2PF
COG-CERM
25V
+/-0.05PF
C3825 1
2
COG-CERM
NO STUFF
0.2PF
+/-0.05PF
25V
0201
C3822 1
2
DPX205950DT
SM
OMIT_TABLE
U3820
2
135
4
6
COG-CERM
0.2PF
+/-0.05PF
25V
CRITICAL
0201
C38261
2
5%
0
CRITICAL
201
1/20W
MF
R3820
1 2
CRITICAL
F-ST-SM
20449-001E-03
J3830
2 3 4
1
CRITICAL
0201
C0G
0.1PF
+/-0.05PF
25V
C3827 1
2
CRITICAL
F-ST-SM
20449-001E-03
J3820
2 3 4
1
NO STUFF
COG-CERM
0.2PF
+/-0.05PF
25V
0201
C38101
2
0201
COG-CERM
+/-0.05PF
25V
NO STUFF
0.2PF
C38301
2
0201
+/-0.05PF
0.2PF
COG-CERM
25V
NO STUFF
C3837 1
2
0.2PF
NO STUFF
0201
25V
COG-CERM
+/-0.05PF
C3815 1
2
SM
OMIT_TABLE
DPX205950DT
U3810
2
135
4
6CRITICAL
0201
25V
+/-0.05PF
0.1PF
C0G
C38161
2
CRITICAL
5%
1/20W
201
0
MF
R3810
1 2
25V
+/-0.05PF
0.1PF
C0G
CRITICAL
0201
C3817 1
2
20449-001E-03
F-ST-SM
CRITICAL
J3810
2 3 4
1
+/-0.05PF
0201
COG-CERM
0.2PF
25V
NO STUFF
C3812 1
2
1/20W
201
MF
CRITICAL
5%
0
R3834
1 2
CRITICAL
0201
C0G
0.1PF
+/-0.05PF
25V
C3835 1
2OMIT_TABLE
SM
DPX205950DT
U3830
2
135
4
6
+/-0.05PF
25V
0.2PF
COG-CERM
NO STUFF
0201
C3832 1
2
113 35 
113 35 
113 
113 
113 
113 35 
113 35 
113 
113 
113 
113 35 113 
113 35 113 
113 
36 35 
48 46 36 35 
110 36 
36 35 
110 36 
113 
113 
113 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
CAP
ON S
D
VDD
GND
IN
NC
VREF
DLY
(OD)
PAD
-
+
RESET*
SENSE
VDD
IN
THRM
GND
MR*
EN
OUT
OUT
GND
COM
LO
HI
GND
COM
LO
HI
GND
COM
LO
HIT208
M7 needed stronger PU but should be fixed on M8
unstuff R3951 and stuff R3952 to enable boundary scan
4MB SPI ROM
T208 DFU_STATUS Isolation
T208 WDOG Isolation
U3910 creates version that is only high in S0
DFU_STATUS can be driven high outside of S0
U3910 creates version that is only high in S0
SEP ROM
STOCKHOLM
I2C Pullups
SOC_WDOG_RESET can be driven high outside of S0
SOCGREENCLK
32K CLK OPTION
SOC PMU
37 OF 121
PP1V1_SLEEP1_SW241 
PP1V8_AWAKE_SW3C
38 
39 
41 
37 
VOLTAGE=1.1V
PP1V8_S0109 
PP1V8_S037 38 42 109 
PP1V8_S042 109 
PP1V1_SLEEP3_BUCK241 
PP1V8_S037 38 42 109 
PP1V8_SLEEP2_SW3A39 41 
VOLTAGE=1.8V
PP1V8_AWAKE_SW3C37 38 39 41 
PP1V8_SLEEP2_SW3A 41 
VOLTAGE=1.8V
PP3V3_S0_LEFT110 
PCH_SOC_DBELL_L
PP1V1_SLEEP1_SW241 
VOLTAGE=1.8V
PP1V8_AWAKE_SW3C37 38 39 41 
VOLTAGE=1.8V
VOLTAGE=1.8V
39 OF 145
10.0.0
051-00647
dvt-fab10
343S00136 SOC:HYNIX
C3903
IC,M8+512MB 20NM DDR,A12,S,SCK,BGA7001 U3900 CRITICAL
UART_STOCKHOLM_TO_SOC_TXD
CERM-X5R
Y10
PP1V1_SLEEP1_PLL_DDR_FILT
DFU_SPI_STATUS
SEP_ROM_WC
SEP_I2C_SCL
SOC_SWCLK
SOC_SWDIO
TP_SOC_JTAG_TRST_L
SOC_JTAG_SEL
SOC_TO_STOCKHOLM_DWLD_REQ
SOC_WDOG_RST
PP1V8_AWAKE_SW3C
MESA_PWR_EN
PP1V8_AWAKE_SW3C PP1V8_S0SW_DFR
DFR_TOUCH_SPI_MISO
SOC_ROM_SPI_MOSI_R
SEP_I2C_SDA
MESA_I2C_SCL
ALS_SCL_I2C_1V8
ALS_SDA_I2C_1V8
ALS_SCL_I2C_1V8
I2C_CAM_SDA
PCH_SOC_WDOG
SOC_WDOG_RST
PCH_SOC_DFU_STATUS
ALS_SDA_I2C_1V8
PMU_TO_SOC_SYS_ALIVE
PMU_TO_SOC_SLEEP1_PWRGD
SOC_DDR_RREF
SOC_PAD_ZQ_A
MESA_I2C_SDA
DFR_TOUCH_SPI_MOSI
DFR_TOUCH_SPI_CS_L
SEP_I2C_SCL
SOC_ROM_SPI_RST_L
DFRDRV_I2C_SCL
PP1V8_S0SW_DFR
SOC_TO_STOCKHOLM_DEV_WAKE
DFRDRV_I2C_SDA
DFU_STATUS
SOC_SPI_BOOT_STATUS
DFR_TOUCH_ROM_I2C_SDASOC_PMU_I2C_SDA
PP_STOCKHOLM_VMID
TP_SOC_JTAG_TDI
PP1V8_SLEEP2_SW3A
SOC_SWDIO
PMU_TO_SOC_AWAKE_PWRGD
SOC_PMU_I2C_SCL
SOC_ROM_SPI_MISO_R
SOC_ROM_SPI_CS_L
SOC_ROM_SPI_CLK_R
PMU_TO_SOC_SLEEP1_PWRGD
SOC_JTAG_SEL
SOC_SLEEP1_REQ
SOC_SPI_BOOT_STATUS
SOC_TO_STOCKHOLM_DEV_WAKE
I2C_CAM_SCL
SOC_VDD_HI_LO
TP_SOC_JTAG_TDO
DFR_TOUCH_RESET_L
UART_STOCKHOLM_TO_SOC_RTS_L
SOC_TO_STOCKHOLM_DWLD_REQ
PP_STOCKHOLM_TVDD
UART_SOC_TO_STOCKHOLM_RTS_L
UART_SOC_TO_STOCKHOLM_TXD
PP1V8_AWAKE_SW3C
SEP_I2C_SDA
DFR_TOUCH_ROM_I2C_SCL
PMU_TO_SOC_IRQ_L
SOC_CLK_32K
PMU_TO_SOC_RESET_L
SOC_AWAKE_REQ
DFR_TOUCH_SPI_CLK
SOC_TO_STOCKHOLM_EN
PMU_TO_SOC_RESET_L
SOC_CLK_32KSOC_PMU_CLK_32K
PMU_TO_SOC_CLK_32K
PP1V8_SLEEP2_LPPLL_FILT
PPSVDD_STOCKHOLM
PPSVDD_STOCKHOLM
PPVDD_STOCKHOLM
PP1V8_AWAKE_SW3C
SOC_ROM_SPI_WP_L
TP_SOC_CLKOUT
PMU_TO_SOC_RESET_L
SOC_TO_STOCKHOLM_DWLD_REQ
IC,RTM2,MP,PN549A1,P61D0 CRITICAL SE:PRODU39051338S00097
CRITICAL SE:DEV1338S00147 IC,RTM2,DEV,PN549A1,P61D0 U3905
SYNC_MASTER=X363_SAKKOC
SYNC_DATE=04/29/2016
Camera/DFR 1
BOM_COST_GROUP=T151
U39061 IC,FLASH,SERIAL,SPI,4MX8,4X3MM,DFN8335S00203
UFBGA
OMIT_TABLE
M8-LPDDR4-H-A-FUSE
U3900
Y12
AB13
AC11
AC12
AA20
AB22
AD25
AE20
AB17
AB18
AE21
AD19
AA17
AC19
AE22
AE23
AB19
AA18
AE24
AD20
AC21
Y18
AE25
AC17
AE18
AE17
AA15
AA16
AE19
AD17
AC18
AD18
Y16
AB24
AD11
AE10
AA12
AB12
AD10
AD9
AA11
AC13
AB11
AA22
AE12
AA
23
AE11
M8-LPDDR4-H-A-FUSE
UFBGA
OMIT_TABLE
U3900
AD26
AD27
AB20
AE26
AE27
AA19
AA9
AB9
AE13
AE14
AB15
Y14
AE15
AD15
AA14
AC16
AA10
AB10
AC10
AC14
AA13
AD12
AD13
AC15
AB14
AA24
W24
AA21
Y24
AD22
AD23
AD24
Y20
AB21
AC22
AC23
AD21
AE16
AD16
AB16
L25
L26
N26
N27
P26
P25
M27
M26
M25
L27
J26
V27
E26
F26
G26
H26
G27
K25
H27
K26
AA25
Y25
W25
Y26
V26
U26
T26
T27
F27
W27
E27
W26
M24
L24
N24
P24
R26
U2
1
N2
5
1%
499
MF
201
1/20W
R3900
1 2
6.3V
0.47UF
0201
CERM-X5R
10%
C39021
2
0.22UF
6.3V
0201
10%
X5R-CERM
C39001
2
120-OHM-0.1A-1.5-OHM
0201
L3900
1 2
1/20W
MF
201
1%
78.7K
R3943
1
2
MLP
M24128
U3901
1
2
3
6 5
9
8
4
7
1/20W
300K
201
5%
MF
R39721
2
5%
201
10K
1/20W
MF
R39701
2
0201
0
1/20W
MF
5%
PLACE_NEAR=U3900.AA22:3mmR3990
1 2
42 
42 
38 
42 
5%
201
10K
MF
1/20W
R39411
2
1/20W
10K
5%
MF
201
R39421
2
6.3V
0201
0.1UF
10%
CERM-X5R
C39201
2
OMIT_TABLE
N25Q032A11E
UFDFPN
4MX8-1.8V
U3906
6 5
2
7
1
9 10
8
4
3
5%
0201
MF
0
1/20W
R3981
1 2
0201
5%
MF
0
NOSTUFF1/20W
R3980
1 2
38 
15 
SOT833
74LVC2G08GT/S505
U3910
5
6
4
8
3
74LVC2G08GT/S505
SOT833
U3910
1
2
4
8
7
42 37 
42 
25V
5%
C0G
100PF
0201
C39601
2
0.1UF
0201
6.3V
10%
C39261
2
X5R
20%
6.3V
1.0UF
0201-1
C39251
2
114 42 
45 
201
1/20W
100K
5%
MF
R39711
2
CERM-X5R
0201
0.1UF
10%
6.3V
C39501
2
15 
114 42 
42 37 
42 37 
MF
201
5%
3.0K
1/20W
R39601
2
3.0K
201
5%
1/20W
MF
R39611
2
1/20W
MF
5%
201
10K
R3973
1
2
38 
MF
5%
201
1/20W
100K
NOSTUFF
R39401
2
OMIT_TABLE
UFLGA
PN66VEU3-A101D004
U3905
D7
D4 D6 F3
A2
D2
B6 C4
B2
G7
G6
F4
C5
A7
D1
A3
D3
C2
A1
C1
F5
F6
F2
G1
B5
A4
E4
E3
F1
B4
B3
A6
E6
B7
A5
E7
G
4
B1
G3
G5
D5
C7C6
E1
F7
E2
G
2
E5
C3
38 
38 
38 
38 
20%
X5R
4.7UF
402
6.3V
C39191
2
X5R
6.3V
20%
1.0UF
0201-1
C39181
2
X5R
20%
6.3V
1.0UF
0201-1
C39171
2
0.1UF
10%
0201
6.3V
CERM-X5R
C39161
2
0.1UF
10%
6.3V
CERM-X5R
0201
C39151
2
20 15 
1K
201
1/20W
MF
5%
NOSTUFF
R3952
1
2
1/20W
201
1K
MF
5%
NOSTUFF
R3953
1
2
10K
5%
MF
1/20W
201
R3951
1
2
114 45 
114 45 
42 
42 
42 
41 
41 
41 20 
PLACE_NEAR=U3900.AA22:3mm
5%
0
MF
1/20W
0201
NOSTUFF
R3925
1 2
5%
4.7K
MF
201
1/20W
R39171
2
4.7K
MF
201
5%
1/20W
R39181
2
201
2.2K
1/20W
5%
MF
R39151
2
5%
2.2K
MF
201
1/20W
R39161
2
2.2K
201
MF
1/20W
5%
R39111
2
2.2K
201
MF
5%
1/20W
R39121
2
38 37 38 37 
1K
201
5%
MF
1/20W
R39061
2
1K
MF
201
5%
1/20W
R39071
2
41 37 
41 38 
41 
41 
41 
41 37 
41 37 
41 37 
41 
2.2K
5%
MF
201
1/20W
R39051
2
2.2K
MF
5%
201
1/20W
R39041
2
240
201
1%
1/20W
MF
R3901
1
2
201
1/20W
MF
1%
240R3902
1
2
PLACE_NEAR=U3901.8:2mm
0.1UF
CERM-X5R
6.3V
10%
0201
1
2
37 
37 
37 
41 
40 38 37 41 40 38 37 114 42 37 
42 37 
114 76 38 
37 
42 37 
38 37 
114 
42 38 
114 
42 37 
37 
114 42 38 
37 
114 
42 38 41 38 
41 40 
42 37 
41 38 
37 
37 
37 
114 76 38 
37 
41 40 38 37 
38 37 
114 42 38 
37 20 
41 37 
37 20 
37 
37 
41 40 38 37 
37 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#
TABLE_5_HEAD
BOM OPTIONCRITICAL
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
(2 OF 7)
AOP_DDR_PWRGOOD
JTAG_SEL
JTAG_TRSTN
JTAG_TDO
CFSB_AOP
COLD_RESETN
AWAKE_REQ
AWAKE_PWRGOOD
AOP_DOCK_ATTENTION
AOP_DOCK_CONNECT
RT_CLK32768
WDOG
SOC_VDD_HI_LO
AOP_DDR_REQ
JTAG_TDI
JTAG_TMS
JTAG_TCK
AOP_UART1_RTSN
AOP_UART1_RXD
AOP_UART1_TXD
AOP_UART2_RXD
AOP_UART2_TXD
AOP_UART0_RTSN
AOP_UART0_CTSN
AOP_SPI_CS_TRIG_9
AOP_SPI_CS_TRIG_7
AOP_SPI_CS_TRIG_5
AOP_SPI_CS_TRIG_4
AOP_SPI_CS_TRIG_3
AOP_SPI_CS_TRIG_2
AOP_SPI_CS_TRIG_15
AOP_SPI_CS_TRIG_14
AOP_SPI_CS_TRIG_13
AOP_SPI_CS_TRIG_12
AOP_SPI_CS_TRIG_11
AOP_SPI_CS_TRIG_10
AOP_SPI_CS_TRIG_6
AOP_UART1_CTSN
AOP_UART0_TXD
AOP_UART0_RXD
AOP_SPI_CS_TRIG_8
AOP_LSPI_MISO
AOP_LSPI_MOSI
AOP_SPI_CS_TRIG_0
AOP_SPI_CS_TRIG_1
VD
D1
8_
LP
PL
L
AOP_LSPI_SCLK
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(1 OF 7)
D
D
R
0
VD
DI
O
11
_P
LL
_D
DR
VD
DI
O
11
_R
ET
_D
DR
AOP_PSENSE_CTRL_5
AOP_PSENSE_CTRL_4
AOP_DETECT_0
AOP_DETECT_1
AOP_PDM_CLK
AOP_PDM_DAT
AOP_PLED_0
AOP_PLED_3
AOP_PLED_4
AOP_PLED_5
AOP_PLED_6
AOP_PLED_7
AOP_PLED_2
AOP_PLED_1
AOP_PSPI_CS_TRIG_3AOP_PSPI_CS_TRIG_4
AOP_PSENSE_CTRL_7
AOP_PSENSE_CTRL_6
AOP_PSPI_MISO
AOP_PSPI_MOSI
AOP_PSPI_SCLK
AOP_SPI0_MISO
AOP_SPI0_MOSI
AOP_MON_0
AOP_MON_1
AOP_MON_2
AOP_MON_3
AOP_MON_4
AOP_MON_5
AOP_MON_6
AOP_MON_7
AOP_SPI0_SCLK
AOP_SWD_TCK_OUT
AOP_I2S1_MCK
AOP_I2S0_MCK
AOP_SWD_TMS0
AOP_I2C1_SCL
AOP_I2C1_SDA
AOP_I2C0_SCL
AOP_I2C0_SDA
AOP_SWD_TMS1
DDR0_CA_0
DDR0_CA_1
DDR0_CA_2
DDR0_CA_3
DDR0_CA_4
DDR0_CA_5
DDR0_CS
DDR0_CK_N
DDR0_CK_P
DDR0_CKE
DDR0_DMI_0
DDR0_DMI_1
DDR0_DQ_0
DDR0_DQ_1
DDR0_DQ_2
DDR0_DQ_6
DDR0_DQ_7
DDR0_DQ_8
DDR0_DQ_9
DDR0_DQ_10
DDR0_DQ_5
DDR0_DQ_4
DDR0_DQ_3
DDR0_DQ_11
DDR0_DQ_12
DDR0_DQ_15
DDR0_DQS_N_0
DDR0_DQS_P_0
DDR0_DQS_P_1
DDR0_DQ_13
DDR0_DQ_14
DDR0_DQS_N_1
PAD_ZQ_A
DDR0_RREF
DDR0_RESET_N
DDR0_SYS_ALIVE
DDR0_RET_N
NC
NC
THM_P
EEPROM
VCC
VSS
E1
SCL SDA
E0
E2
WC*
OUT
IN
IN
IN
VCC
DQ1
DQ0
THRM_PADVSS
C
S*
W*/VPP/DQ2
HOLD*/DQ3
NC
IN
OUT
08B
A
Y
08B
A
Y
BI
IN
OUT
OUT
NC
OUT
NC
NC
NC
NC
NC
OUT
NC
NC
BI
OUT
NC
NC
IN
PV
DD
SV
DD
SI
M
_P
M
U_
VC
C
AV
DD
CLK_REQ
SPIM_SCK
SPIM_MISO
SPIM_MOSI
XTAL2
ESE_IO1
NFC_CLK_XTAL1
SMX_RST*
RTS
SMX_CLK
VEN
TX
CTS
RX
SVDD_REQ
DWL
IRQ
AV
SS
AV
SS
AV
SS
DV
SS
VS
S
DV
SS
TV
SS
PV
SS
VMID
TX2
RXN
TX1
RXP
GPIO0
SIM_SWIO
SPIM_IRQ
ESE_DWPM_DBG
ESE_DWPS_DBG
WKUP_REQ
SE2_SVDD_IN
SE2_PWR_REQ
TX_PWR_REQ
SPIM_NSS
VU
P
TV
DD
ES
E_
VD
D
VB
AT
VD
D
NC
OUT
OUT
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
NC
NC
OUT
BI
IN
OUT
OUT
NC
IN
NC
IN
NC
IN
NC
NC
BIIN
NC
IN
IN
OUT
OUT
NC
OUT
IN
IN
IN
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
T208 SOC_S2R_ACK_L bi-directional Isolation T208 SOC_S2R_ACK_L Isolation (NOSTUFF)
T208
PCH T208
Q4000 to act as bi-directional islation for SOC_S2R_ACK_L
When in system S0 and M8 AWAKE, FET will be on & line will be pulled high
Below S0, SOC_S2R_ACK_L will be low and FET will be open (isolated from M8 power rails)
To/From PCH for ALS
When M8 enters S2R, FET will be on, PP1V8_AWAKE_SW3C will turn off and SOC_S2R_ACK_L will be low
PCH
T208 FORCE_DFU Isolation
U4070 prevents it from leaking into PCH
T208
In the SOC_BOOT:DFU option
SOC_FORCE_DFU should be pulled up to S4
MIPIC FILTERING
PCH
To/From PCH for logging/debug
38 OF 121
VOLTAGE=5V
PP0V8_SLEEP1_SW1 41 
PP1V8_AWAKE_SW3C41 PP1V8_AWAKE_SW3C41 
PP1V8_AWAKE_SW3C37 38 39 41 
PP1V8_AWAKE_SW3C
VOLTAGE=1.1V
PP3V0_AWAKE_LDO7 38 41 
PP1V8_AWAKE_SW3C 37 38 39 41 
PP3V3_S4_SOC_PMU 42 110 
PP1V1_SLEEP1_SW2 41 
PP1V8_AWAKE_SW3C37 38 
39 41 
PP1V1_SLEEP1_SW241 
PP0V8_SLEEP1_SW141 
PP1V8_S442 109 
PP3V0_AWAKE_LDO738 41 
PP1V8_S037 38 42 109 
SOC_PCH_DBELL_L
PP1V1_SLEEP1_SW241 
PP1V8_AWAKE_SW3C
PP1V8_S037 38 42 109 
PP3V3_S0_LEFT42 110 
40 OF 145
10.0.0
051-00647
dvt-fab10
PP5V_S0_ALSCAM_F
PP1V8_AWAKE_SW3C
SOC_USB_VBUS
DFR_TOUCH_INT_L
SOC_BOARD_ID_3
MIPIC_DATA_N
PP1V1_SLEEP1_XTAL_FILT
SOC_NAND_CEN_0
MIPI_CLK_CONN_N
DFR_CLKIN_RESET_L
DFR_TOUCH_PANEL_DETECT
TP_SOC_TST_CKOUT
SOC_BOARD_REV_0
PMU_TO_SOC_AWAKE_PWRGD
MIPID_DATA_P
SOC_TO_PCH_UART_TXD
DFR_DISP_INT
SOC_TO_STOCKHOLM_EN
MESA_SNSR_INT
SOC_BOARD_REV_1
DFR_DISP_RST_L
DFRDRV_I2C_SCL
SOC_ROM_SPI_MOSI
MIPIC_CLK_N
MIPIC_DATA_P
DFR_DISP_TE
DFR_DISP_VSYNC
MIPID_CLK_N
MIPID_DATA_N
I2C_CAM_SCL
PP1V8_AWAKE_SW3C
PP1V8_AWAKE_SW3C
SOC_MIPI1C_REXT
I2C_CAM_SDA
USB_CAMERA_DFR_N
SOC_REQUEST_DFU1
USB_CAMERA_DFR_P
SOC_USB_REXT
PCH_TO_SOC_UART_TXD
UART_STOCKHOLM_TO_SOC_RTS_L
SOC_BOARD_REV_2
SOC_PMU_I2C_SCL
DFR_TOUCH_ROM_I2C_SCL
PP5V_S0
MIPIC_CLK_P
DFU_STATUS
S2R_ACK_L
SEP_I2C_SCL
SOC_REQUEST_DFU2SOC_REQUEST_DFU1
MIPIC_CLK_P
SEP_I2C_SDA
MIPIC_DATA_P
MIPIC_DATA_N
DFR_TOUCH_GPIO2
SOC_FORCE_DFU
MIPIC_CLK_N
UART_SOC_TO_STOCKHOLM_TXD
UART_STOCKHOLM_TO_SOC_TXD
MIPI_CLK_CONN_P
MIPI_DATA_CONN_N
MIPI_DATA_CONN_P
UART_SOC_TO_STOCKHOLM_RTS_L
MESA_SPI_MISO
SOC_ROM_SPI_CS_L
SOC_ROM_SPI_CLK
PCH_SOC_FORCE_DFU
MESA_SPI_CLK
SOC_XTAL_24M_O_R
MESA_SPI_MOSI
PCH_ALS_TO_SOC_UART_TXD
SOC_TO_PCH_ALS_UART_TXD
SOC_PANIC_L
DFR_TOUCH_ROM_WC
SOC_ROM_SPI_MISO
SOC_PMU_I2C_SDA
DFR_TOUCH_ROM_I2C_SDA
S2R_ACK_LSOC_S2R_ACK_L
SOC_S2R_ACK_L
S2R_ACK_L
SOC_XTAL_24M_I
SOC_XTAL_24M_O
DFRDRV_I2C_SDA
SOC_FORCE_DFU
SOC_REQUEST_DFU2
PMU_TO_SOC_VDD_OK
SOC_BOOT_CONFIG_0
MIPID_CLK_P
SOC_MIPI0D_REXT
SYNC_DATE=03/22/2016
SYNC_MASTER=X362_T208
Camera/DFR 2
BOM_COST_GROUP=T151
MF
PLACE_NEAR=U3900.K1:2mm
1/20W
1%
4.02K
201
R4003
1 2
200
PLACE_NEAR=U3900.H4:2mm
1%
1/20W
201
MF
R4001
1 2
113 14 
10K
5%
MF
1/20W
201
R40821
2
38 15 
NOSTUFF
1/20W
MF
201
5%
200K
R40801
2
DFN1006H4-3
DMN32D2LFB4
Q4000
3
1
2
20 15 
38 15 
SOC_BOOT:DFU
74LVC1G08FW5
DFN1010
U4070
3
1
2
5
4
6
NOSTUFF
DFN1010
74LVC1G08FW5
U4080
3
1
2
5
4
60201
CERM-X5R
6.3V
10%
NOSTUFF
0.1UF
C40801
2
15 
37 
114 42 
114 42 
42 
76 
76 
76 
76 
42 
42 
114 42 
114 42 
114 42 
114 42 
114 42 
114 42 
114 42 
114 42 
114 42 
15 
47K
201
5%
MF
1/20W
SOC_BOOT:DFU
R40701
2
0
MF
1/20W
5%
201 SOC_BOOT:SPI
R4071
1 2
CERM-X5R
6.3V
10%
0201
0.1UF
SOC_BOOT:DFU
C40701
2
0402A
FERR-120-OHM-1.5A
L4004
1 2
TAM0605-4SM
PLACE_NEAR=J8500:2.54mm3.25-OHM-0.1A-2.4GHZ
GND_VOID=TRUEGND_VOID=TRUE
GND_VOID=TRUE GND_VOID=TRUE
L4003
1
2 3
4
0201
X5R-CERM
10V
10%
0.1UF
C40621
2
GND_VOID=TRUE
PLACE_NEAR=J8500:2.54mm
TAM0605-4SM GND_VOID=TRUE
3.25-OHM-0.1A-2.4GHZ
GND_VOID=TRUE GND_VOID=TRUE
L4002
1
2 3
4
201
MF
1/20W
NOSTUFF10K5%
R40421
2
201
NOSTUFF 1/20W
5%
MF
2.2K
R4017
1
2
42 39 
37 
42 39 
42 39 
113 14 
10K
201
5%
1/20W
MF
R40371
2201
MF
1/20W
5%
10K
R40361
2
SOC_BOOT:DFU
201
47K
1/20W
MF
5%
R40351
2
1/20W
100K
5%
MF
201
R40241
2
10K
201
1/20W
5%
MF
R40221
2
201
MF
5%
100K
SOC_BOOT:SPI
1/20W
R40231
2
42 
42 
0201
120-OHM-0.2A-0.5-OHM
L4010
1 2
0.22UF
X5R-CERM
10%
6.3V
0201
C40501
2
6.3V
0.1UF
10%
0201
CERM-X5R
C40011
2
PLACE_NEAR=U3900.K2:3mm
1%
4.02K
201
1/20W
MF
R4004
1 2
39 
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
UFBGA
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
OMIT_TABLE
CKPLUS_WAIVE=PWRTERM2GND
M8-LPDDR4-H-A-FUSE
U3900
C1
H6
F2
D2
C2
D12
C12
A2
B2
J1
H2
J2
H1
K2
L2
M2
L1
M3
K1
N3
P6
P4
P3
N2
P5
R4
P2
D15
D17
B20
C16
E16
A19
B18
D16
C17
A21
B19
E17
A20
A18
A12
A11
B11
F10
B12
E11
C10
C11
B14
E13
A14
C13
F12
B13
A13
D24
E21
E22
D23
D22
F22
E24
B1
F5
G
3
G
4
G
24
G
23
V2
3
U2
3
F2
4
F3 L4 M
4
G
5
K4 N4
E12
M8-LPDDR4-H-A-FUSE
UFBGA
OMIT_TABLE
U3900D3
E2
P1
R3
F4
C23
F20
C22
E20
D25
C24
D21
C25
E19
D20
C21
A22
B22
B23
D19
F18
C19
B21
C3
B8
C8
A8
D8
E8
B7
C7
A7
B17
E15
A17
C15
C14
E14
A16
B16
B15
D13
A15
F14
E3
D1
E10
D10
B10
A10
A9
C9
B9
E9
A3
D18
E18
A23
T6
A6
D7
B3
D5
C4
B4
A4
E6
B5
D6
E7
A5
B6
C5
C6
G2
G1
J3
H4
K6
J1
2
H1
2
H1
0
Y8J2
2
J6 H3 J5
AA8
AB8
37 
37 
114 76 37 
114 76 37 
45 
39 
39 
39 
39 
45 
37 
114 42 37 
114 42 37 
114 42 37 
41 37 
114 42 37 
41 37 
41 
41 37 
37 
37 
37 
37 
42 
42 
5%
0201
C0G-CERM
50V
12PF
C40401
2C0G-CERM
0201
12PF
5%
50V
C40411
2
0.00
1%
1/20W
MF
0201
R40201
2
499K
201
MF
1%
1/20W
R4010
1 2
1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
Y4000
2 4
1 3
1.0UF
6.3V
20%
0201-1
X5R
C40061
2
10%
0.1UF
6.3V
CERM-X5R
0201
C40081
2
0.1UF
0201
10%
6.3V
CERM-X5R
C40071
2
CERM-X5R
0201
6.3V
10%
0.1UF
C40051
2
0.1UF
CERM-X5R
0201
10%
6.3V
C40041
2
10%
6.3V
CERM-X5R
0201
0.1UF
C40031
2
0.1UF
6.3V
0201
CERM-X5R
10%
C40021
2
0.1UF
6.3V
10%
0201
CERM-X5R
C40001
2
114 76 
41 40 38 37 
114 38 
114 38 
114 38 
41 40 38 37 
41 40 38 37 
38 
115 110 
114 38 
38 
38 38 
114 38 
114 38 
114 
38 
38 
114 38 
113 38 
38 
113 
113 
38 
38 
 II NOTTO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
BI S D
S
Y
M
_V
E
R
_1
G
NC
IN
OUT
NC
B
Y
A
NC
B
Y
A
NC
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
BI
BI
IN
IN
BI
BI
OUT
OUT
IN
NC
SYM_VER-1
SYM_VER-1
NC
NC
NC
NC
IN
OUT
OUT
OUT
NC
BI
NC
NC
OUT
IN
NC
IN
(4 OF 7)
VD
D1
2_
HS
IC
VD
D_
FI
XE
D_
M
IP
I
VD
D1
8_
AM
UX
VD
D1
8_
M
IP
I
VD
D1
8_
EF
US
E6
VD
D_
FI
XE
D_
HS
IC
VD
D1
8_
EF
US
E5
VD
D1
8_
EF
US
E4
VD
D1
8_
EF
US
E2
VD
D1
8_
EF
US
E1
MIPI1C_DNDATA0
MIPI0D_REXT
MIPI0D_DPDATA0
MIPI0D_DPCLK
MIPI0D_DNDATA0
MIPI0D_DNCLK
DISP_VSYNC
NAND_CEN_1
NAND_CEN_0
NAND_ALE
DISP_TE
NAND_CLE
NAND_REN
NAND_IO_6
NAND_IO_5
NAND_IO_4
NAND_IO_3
NAND_IO_2
NAND_IO_1
NAND_IO_0
NAND_WEN
NAND_IO_7
MON_7
MON_6
MON_5
MON_4
MON_3
MON_2
MON_1
MON_0
SEP_SPI0_SCLK
SEP_SPI0_MOSI
SEP_SPI0_MISO
SEP_I2C_SDA
SEP_I2C_SCL
SEP_GPIO1
SEP_GPIO0
ISP0_SDA
MIPI1C_REXT
MIPI1C_DPDATA0
MIPI1C_DPCLK
MIPI1C_DNCLK
ISP0_SCL
ENET_MDC
RMII_CLK
RMII_RXD_0
RMII_RXD_1
RMII_CRSDV
ENET_MDIO
RMII_RXER
RMII_TXD_0
RMII_TXD_1
RMII_TXEN
SD_CLKOUT
SD_CMD_IO
SD_DATA_IO_0
SD_DATA_IO_1
SD_DATA_IO_2
SDIO_IRQ
SWD_TMS2
SWD_TMS3
SD_DATA_IO_3
ANALOGMUX_OUT
WL_HOST_WAKE
BB_HSIC_STROBE
BB_HSIC_DATA
VD
D1
8_
EF
US
E3
(3 OF 7)
DFU_STATUS
SPI1_SSIN
SPI1_SCLK
SPI1_MOSI
SPI1_MISO
SPI0_SSIN
SPI0_SCLK
XO0
XI0
SPI0_MOSI
SPI0_MISO
I2C2_1_SDA
I2C2_1_SCL
I2C2_0_SDA
I2C2_0_SCL
I2C1_SCL
I2C1_SDA
I2C0_SDA
GPIO_17
I2C0_SCL
GPIO_16
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_11
GPIO_9
GPIO_10
GPIO_6
GPIO_7
GPIO_8
GPIO_2
GPIO_4
GPIO_5
HOLD_RESET
TST_CLKOUT
CLK32K_OUT
TESTMODE
GPIO_0
CFSB
REQUEST_DFU2
DROOP_N
I2S1_DIN
I2S1_DOUT
I2S1_LRCK
I2S2_BCLK
I2S2_DIN
I2S2_DOUT
I2S2_LRCK
I2S0_BCLK
I2S0_DIN
I2S0_DOUT
I2S0_LRCK
I2S1_BCLK
UART5_TXD
UART2_CTSN
UART2_RTSN
UART2_RXD
UART2_TXD
UART3_RTXD
UART4_RXD
UART4_TXD
UART5_RXD
TMR32_PWM1
TMR32_PWM2
UART0_RXD
UART0_TXD
UART1_CTSN
UART1_RTSN
UART1_RXD
UART1_TXD
TMR32_PWM0
USB_ID
USB_REXT
USB_VBUS
USB_DP
GPIO_3
GPIO_1
REQUEST_DFU1
VD
D_
FI
XE
D_
US
B
VD
D1
1_
XT
AL
VD
D3
0_
US
B
VD
D1
8_
US
B
VD
D1
8_
TS
AD
C
VD
D1
1_
UV
D
VD
D1
1_
PL
L_
SO
C1
VD
D1
1_
PL
L_
SO
C0
USB_DM
FORCE_DFU
OUT
BI
BI
OUT
IN
IN
IN
IN
IN
NC
IN
OUT
BI
OUT
BI
BI
OUT
OUT
IN
IN
OUT
IN
OUT
IN
OUT
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1100 T208_Rev3 (X362 P2)
1101 T208_Rev2 (X362 P1)
1110 T208_Rev1 (X363 P0)
1111 T208_Rev0 (X362 P0)
BOARD REV[3:0] MODE
1XXX T202 DEV
T208 BOARD REV/BOARD ID
3. READ
1. SET GPIO AS INPUT
S/W READ FLOW
ID_3 reserved for DEV 
2. DISABLE PU AND ENABLE PD
4. DISABLE PD AND ENABLE PU
BOARD ID[3:0] MODE
1010 T208_Rev5 (X363 EVT/X362 EVT1)
0010 T208
1011 T208_Rev4 (X363 P2/X362 localEVT)
39 OF 121
PP0V8_SLEEP2_BUCK141 
PP1V8_SLEEP2_SW3A37 41 
PP1V1_SLEEP3_BUCK241 
PP1V8_SLEEP3_BUCK341 
PP0V8_SLEEP1_SW139 41 
PP1V1_SLEEP1_SW241 
PP1V8_AWAKE_SW3C38 
PP1V8_AWAKE_SW3C37 38 39 41 
PP0V8_SLEEP1_SW1
PP1V8_AWAKE_SW3C 37 38 39 41 
PP1V8_AWAKE_SW3C37 38 39 41 
PP0V6_SLEEP2_LDO0 41 
PP0V6_SLEEP1_BUCK0
41 OF 145
10.0.0
051-00647
dvt-fab10
SOC_ROM_SPI_MOSI
SOC_ROM_SPI_MISO
SOC_ROM_SPI_CLK
SOC_BOARD_REV_1
SOC_BOARD_ID_3
SOC_BOARD_REV_2
SOC_BOARD_REV_0
BOM_COST_GROUP=T151
Camera/DFR 3
SYNC_MASTER=X362_T208 SYNC_DATE=04/25/2016
T208_CONFIG2_H,T208_CONFIG1_H,T208_CONFIG0_HT208_PROG:REV0
T208_PROG:REV1 T208_CONFIG2_H,T208_CONFIG1_H
T208_CONFIG2_HT208_PROG:REV3
T208_CONFIG2_H,T208_CONFIG0_HT208_PROG:REV2
T208_PROG:REV5 T208_CONFIG1_H
T208_CONFIG1_H, T208_CONFIG0_HT208_PROG:REV4
CERM-X5R
6.3V
0.1UF
10%
0201
C41061
2
CERM-X5R
0.1UF
10%
6.3V
0201
C41011
2
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
M8-LPDDR4-H-A-FUSE
OMIT_TABLE
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GNDCKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
UFBGA
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
CKPLUS_WAIVE=PWRTERM2GND
U3900
AC8
AB1
AB7
AE6
AD6
AE8
AD7
AC7
AD8
AE7
AE9
AD3
AA5
AA7
AC2
AB2
AA2
AB4
AC3
AD4
AE2
AC4
AB5
AE3
AE4
AE5
AA6
AC5
AB6
AC6
AD2
AD1
AB3
AC1
T3
T1
T2
R2
R1
T5
U2
U1
V2
V1
W2
W1
Y2
Y1
U5V5U4T4
M7
N7
R6
R7
U7
V4
V6
AA3
M6
P7
T8
V8
W5
W7
Y4
Y5
Y6
Y7
U3 V3 W
3
W
4 Y3
M8-LPDDR4-H-A-FUSE
OMIT_TABLE
UFBGA
U3900A1A25
A26
A28
AA1
AA26
AA27
AA28
AA4
AB27
AB28
AC20
AC26
AC9
AD14
AD28
AD5
AE1
AE28
B27
B28
C18
C20
C26
C28
D11
D14
D26
D27
D4
D9
E1
E23
E25
E28
F1
F16
F25
G20
G25
G28
G7
H11
H13
H15
H19
H21
H24
H25
H5
H7
H9
J10
J14
J16
J18
J20
J24
J25
J27
J4
J8
K11
K13
K15
K17
K19
K21
K24
K3
K7
K9
L10
L12
L14
L16
L18
L20
L22
L28
L3
L6
L8
M11
M13
M15
M17
M19
M21
M5
M9
N10
N12
N14
N16
N18
N20
N22
N28
N8
P11
P13
P15
P17
P19
P21
P27
P9
R10
R12
R14
R16
R18
R20
R22
R24
R25
R8
T11
T13
T15
T17
T19
T21
T24
T25
T7
T9
U10
U12
U14
U16
U18
U20
U22
U24
U25
U6
U8
V11
V15
V17
V19
V24
V25
V28
V7
V9
W14
W20
W22
W28
W6
W8
Y17
Y27
6.3V
X5R
20%
0201-1
1.0UF
C41001
2
6.3V
20%
X5R-CERM
2.2UF
0201
C41091
2
0.1UF
10%
6.3V
CERM-X5R
0201
C41021
2
0.1UF
CERM-X5R
6.3V
0201
10%
C41201
2
0.1UF
10%
6.3V
0201
CERM-X5R
C41211
2
CERM-X5R
10%
6.3V
0201
0.1UF
C41191
2
CERM-X5R
0201
6.3V
0.1UF
10%
C41161
2
X5R
6.3V
20%
1.0UF
0201-1
C41141
2 CERM-X5R
6.3V
0.1UF
10%
0201
C41151
2
0201-1
X5R
1.0UF
20%
6.3V
C41121
2 X5R
10%
0.1UF
0201
6.3V
C41131
2
6.3V
X5R
20%
1.0UF
0201-1
C41411
2
20%
6.3V
X5R-CERM
0201
2.2UF
C41421
2
4.3UF
20%
4V
CER-X5R
0402
C4123
1
2
3
44.3UF
4V
0402
CER-X5R
20%
C4122
1
2
3
4
CER-X5R
20%
4V
0402
4.3UF
C4118
1
2
3
4
CER-X5R
4V
20%
0402
4.3UF
C4117
1
2
3
4
4.3UF
20%
4V
CER-X5R
0402
C4108
1
2
3
44.3UF
4V
20%
CER-X5R
0402
C4107
1
2
3
4
4V
CER-X5R
0402
20%
4.3UF
C4111
1
2
3
4
20%
CER-X5R
0402
4V
4.3UF
C4110
1
2
3
4
4V
20%
0402
CER-X5R
4.3UF
C4104
1
2
3
4
4V
0402
4.3UF
CER-X5R
20%
C4103
1
2
3
4
NOSTUFF
MF
5%2.2K
201
1/20W
R4103
1
2
NOSTUFF
201
MF
1/20W
5%2.2K
R4104
1
2
1/20W
MF
5%2.2K
201
R4105
1
2
NOSTUFF
201
MF
2.2K
1/20W
5%
R4106
1
2
1/20W
MF
5%
2.2K
201
T208_CONFIG0_H
R4102
1
2
5%
201
MF
2.2K
1/20W
T208_CONFIG1_H
R4101
1
2
T208_CONFIG2_H
1/20W
MF
201
5%
2.2K
R4100
1
2
OMIT_TABLE
UFBGA
M8-LPDDR4-H-A-FUSE
U3900A24AC24
AC28
C27
K28
N1
R28
A27
AC25
AC27
B24
J28
K27
M1
M28
P28
T28
H23
E4
F11
F15
G17
G19
G22
G6
G8
H14
H16
H18
H8
J15
J19
J21
J9
K10
K12
K16
K18
L13
L15
L19
L21
L5
L7
L9
M10
M12
M16
N13
N15
N17
N19
N21
N6
N9
P10
P16
R11
R13
R15
R17
R19
R21
R9
T10
T16
U11
U13
U15
U17
U19
U9
V10
V12
V22
W11
W23
V14
V16
V18
V20
W17
W21
Y11
F13
F17
F23
F6
F8
G11
G13
G15
G18
G21
G9
H17
H20
H22
J11
J13
J17
J7
K14
K20
K22
K5
K8
L11
L17
M14
M18
M20
M22
M8
N11
N5
P12
P14
P18
P20
P22
P8
T12
T14
T18
T20
T22
V13
V21
W13
W9
Y23
W10
W15
W19
Y21
AB25
AB26
B25
B26
D28
F28
H28
J23
K23
L23
M23
N23
P23
R23
R27
T23
U27
U28
Y28
AB23
W12
W16
W18
Y13
Y15
Y19
Y22
Y9
E5
F19
F21
F7
F9
G10
G12
G14
G16
R5
42 38 
42 38 
42 38 
38 
38 
38 
38 
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEMTABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
(7 OF 7)
MAR_TX_THROTTLE_N
VD
D1
2_
M
AR
_P
LL
VD
D1
2_
M
AR
_L
V
VD
D1
2_
M
AR
_H
V
VD
D1
2_
M
AR
_B
G
VS
S_
M
XL
MAR_VDD1V2_PWR_REQ
MAR_RFIC_PDET_1
MAR_BT_RFIC_IRQ
MAR_WL_RFIC_IRQ
MAR_RFIC_PDET_0
MAR_SYSALIVE
MAR_RF_SWITCH_CTRL_2
MAR_VDD1V2_FORCE_PWM
MAR_RF_SWITCH_CTRL_1
MAR_RF_SWITCH_CTRL_0
MAR_ETIC_GPIO_1
MAR_ETIC_GPIO_0
MAR_PA_CTRL
MAR_PA_EN
MAR_RFIC_EN
MAR_RFFE_SCLK
MAR_RFFE_SDATA
MAR_SPARE_0
MAR_SPARE_1
MAR_SPI_CLK
MAR_SPI_CS
MAR_SPI_DATA_0
MAR_SPARE_2
MAR_SPI_DATA_1
MAR_COEX_UART_TXD
MAR_COEX_UART_RXD
MAR_SPI_DATA_3
MAR_SPI_DATA_6
MAR_SPI_DATA_7
MAR_SPI_DATA_5
MAR_SPI_DATA_4
MAR_SPI_DATA_2
CFSB_MAR
MAX_TX_IP
MAX_TX_IM
MAX_RX_QP
MAX_RX_QM
MAX_RX_IP
MAX_RX_IM
MAX_FREF
MAX_TX_BTAP
MAX_TX_BTAM
MAX_TEST_OUT
MAX_TX_QM
MAX_TX_QP
MAX_TX_WLETM
MAX_TX_WLETP
VDD_SOC_MAR
VDD_SRAM_MAR
VDDIO18_MAR
(6 OF 7)
VSS VSS
(5 OF 7)
VDD_SRAM
VDD_SRAM_AON
VDDIO11_DDR
VDD18_FMON
VDDIO18_GRP1
VDDIO18_GRP0
VDDIO18_AOP
VDD2
VDD1
VDD_SRAM
VDD_SOC_AON
VDD_SOC
Mirror Capacitors in Layout
Mirror Capacitors in Layout
Place same side as PMU
Not using Buck4
VDD_SRAM_AON
501MA MAX
Place same side as PMU
Place same side as PMU
Mirror Capacitors in Layout
VDD_SOC
VDD_FIXED_USB
VDD_FIXED_MIPI
FB for Bucks
Berkelium
VDD1
300MA MAX
100MA MAX
460MA MAX
VDDQ
Mirror Capacitors in Layout
VDD2
VDD_SOC_AON
VDD18_USB
VDD11_XTAL
VDDIO18_GRP0
VDD_SRAM
Place same side as PMU
40 OF 121
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
MIN_LINE_WIDTH=0.6000
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6000
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
DIDT=TRUE
SWITCH_NODE=TRUE
VOLTAGE=0.6V
VOLTAGE=1.8V
PP3V3_S4_SOC_PMU40 41 110 
PP3V3_S4_SOC_PMU40 41 110 
PP3V3_S4_SOC_PMU40 41 110 
PP3V3_S4_SOC_PMU40 41 110 
PP3V3_S4_SOC_PMU 40 41 110 
PP3V3_S4_SOC_PMU40 41 110 
PP3V3_S4_SOC_PMU40 41 110 
42 OF 145
10.0.0
051-00647
dvt-fab10
PP1V1_SLEEP3_BUCK2
SOC_PMU_BUCK3_FB
SOC_PMU_BUCK1_FB
PP1V1_SLEEP3_BUCK2SOC_PMU_BUCK2_FB
SOC_PMU_BUCK0_FB PP0V6_SLEEP1_BUCK0
PP0V8_SLEEP1_SW1
PP0V8_SLEEP2_BUCK1
PP0V8_SLEEP1_SW1
SW1_EXT_ON
PP0V6_SLEEP1_BUCK0
PP1V8_SLEEP3_BUCK3
SW1_EXT_ON
PP1V8_AWAKE_SW3C
PP1V8_SLEEP2_SW3A
PP1V1_SLEEP3_BUCK2
SOC_PMU_BUCK3_FB
SOC_PMU_BUCK3_LX
SOC_PMU_BUCK2_LX
SOC_PMU_BUCK1_LX
SOC_PMU_BUCK1_FB
SOC_PMU_BUCK0_LX
SOC_PMU_BUCK0_FB
PP1V8_SLEEP3_BUCK3
PP1V1_SLEEP1_SW2
PP0V8_SLEEP1_SW1
PP0V6_SLEEP2_LDO0
PP0V8_SLEEP2_BUCK1
PP1V8_ALWAYS_LDO9
PP1V8_SLEEP3_BUCK3
PP0V8_SLEEP2_BUCK1
SOC_PMU_BUCK2_FB
PP3V0_AWAKE_LDO7
Berkelium - 1
BOM_COST_GROUP=T151
SYNC_MASTER=X362_T208 SYNC_DATE=01/27/2016
6.3V
0201
X5R-CERM
20%
2.2UF
C42281
2
CRITICAL
PLACE_NEAR=U4200.K11:2mm
15UF
20%
6.3V
CERM
0402
C42031
2
15UF
PLACE_NEAR=U4200.F12:2mm
CRITICAL
20%
6.3V
CERM
0402
C42061
2
PLACE_NEAR=U4200.A2:2mm
CRITICAL
0402
6.3V
20%
CERM
15UF
C42051
2
15UF
CERM
6.3V
20%
CRITICAL
0402
PLACE_NEAR=U4200.A7:2mm C42041
2
15UF
6.3V
0402
20%
CERM
CRITICAL
C42081
2
MCFK1608T1R0M NA
1.0UH-1.3A-0.326OHM
CRITICAL
L4205
1 2
MCFK1608T1R0M NA
1.0UH-1.3A-0.326OHM
CRITICAL
L4204
1 2
1.0UH-1.3A-0.326OHM
MCFK1608T1R0M NA
CRITICAL
L4203
1 2
MCFK2012-SM
1.0UH-1.82A-0.203OHM
CRITICAL
L4202
1 2
20%
6.3V
0201
2.2UF
X5R-CERM
C42101
2
20%
6.3V
CERM
0402
15UF
CRITICAL
C42091
2
WLCSP
D2346A1-OTP-CE
CKPLUS_WAIVE=PWRTERM2GND
U4200
K3
N8
J3
E1
G1
H1
C9
A6
D9
A9
C2
A3
D10
E12
J10
H12
C10
N10
M5
N4
M1
N3
N9
N5
N6
M8
C6
D7
B10
A11
B1
C1
B12
B11
C11
C12
M2
K1
L1
K2
K1
2
L1
2
M
12
K1
0
N2
M4
L8
L3
D1 J1A7 A8 A2 F1
2
G
12
K1
1
L1
1
M
11
M6
M9
M10
N7
L2
B2 B9 C4 C5 E5 E6 H5 H6 F5 F6 G
5
G
6
M
3
M
7
G
8 H7 H8 E7 F7 F8 G
7 A1 A1
2 N1 N1
2
F1
A5
A10
A4
D12
J12
0201
X5R-CERM
0.022UF
10%
6.3V
C42261
20201
CERM-X5R
10V
20%
0.22UF
C42271
2
SON2X2
CSD58892Q2
Q4201
1 2 5 6 8
3
4 7
402
5%
1/16W
MF-LF
0
R4203
1 2
402
0
1/16W
MF-LF
5%
R4202
1 2
402
1/16W
MF-LF
0
5%
R4201
1 2
MF-LF
402
1/16W
5%
0
R4200
1 2
10%
16V
0402-1
X5R-CERM
4.2UF
CRITICAL
C42311
2
CERM-X5R
10UF
20%
6.3V
0402
CRITICAL
C42391
2
10%
16V
X5R-CERM
4.2UF
0402-1
CRITICAL
C42111
2
6.3V
0201
X5R-CERM
20%
2.2UF
C4220 1
2
6.3V
X5R-CERM
PLACE_NEAR=U4200.M4:2mm
2.2UF
20%
0201
C42191
2
2.2UF
20%
X5R-CERM
6.3V
0201
PLACE_NEAR=U4200.L8:2mm
C42181
2
PLACE_NEAR=U4200.D1:2mm
0402
CRITICAL
20%
CERM
6.3V
15UF
C42021
2
0402
CER-X5R
4.7UF
20%
6.3V
CRITICAL
C42371
2
4.7UF
0402
20%
6.3V
CER-X5R
CRITICAL
C42361
2CER-X5R
4.7UF
0402
6.3V
20%
CRITICAL
C42351
2
0402
6.3V
4.7UF
20%
CER-X5R
CRITICAL
C42341
2
4.7UF
0402
6.3V
20%
CER-X5R
CRITICALC42411
2
4.7UF
20%
6.3V
CER-X5R
0402
CRITICAL
C42401
2CERM-X5R
20%
10UF
6.3V
0402
CRITICAL
C42381
2
CER-X5R
4.7UF
0402
6.3V
20%
CRITICAL
C42321
2
4.7UF
6.3V
0402
CER-X5R
20%
CRITICAL
C42331
2
6.3V
20%
X5R-CERM
0201
2.2UF
C42301
2
15UF
CERM
0402
20%
6.3V
CRITICAL
PLACE_NEAR=U4200.E1:3mm
C42071
2
41 40 
40 
40 
41 40 40 
40 41 40 
41 40 
41 40 
41 40 
40 
41 40 
41 40 
40 
41 38 37 
41 37 
41 40 
40 
40 
40 
41 40 
41 
41 40 
41 
41 40 
41 40 
40 
41 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
SYM 1 OF 2
VD
D_
M
AI
N_
BU
CK
1
VD
D_
M
AI
N_
BU
CK
2
VD
D_
M
AI
N_
BB
VD
D_
M
AI
N_
CH
G
VD
D_
M
AI
N_
CH
G
AC
T_
DI
O
DE
*
VD
D_
M
AI
N_
SW
4
BB_LX1
SW1_EXT
SW0_EXT
VD
D_
M
AI
N_
CH
G
SW6_OUT
SW5_OUT
SW5_IN
SW3C_OUT
SW3A_OUT
LDO9_OUT
LDO8_OUT
AUX_PWR_OUT
SW2_IN
LDO6_OUT
VDD_MAIN_LDO_8
VDD_MAIN_LDO_16
VDD_MAIN_LDO_AUX
LDO1_OUT
VDD_MAIN_LDO_9
LDO7_OUT
SW4_OUT
LDO5_OUT
VDD_HVLDO_RTC
LDO2_OUT
LDO3_OUT
LDO4_OUT
VDD_HVLDO_SW6
VDD_HVLDO_45
VDD_HVLDO_237
BB_OUT
BB_FB
BB_LX2
BUCK4_LX
BUCK4_FB
VSS_BB
VSS_BUCK0
VSS_BUCK2
VSS_BUCK3
VSS_BUCK4
VSS_BUCK1
BUCK3_FB
BUCK3_LX
BUCK2_LX
BUCK2_FB
BUCK1_LX
BUCK1_FB
BUCK0_LX
BUCK0_FB
VD
D_
M
AI
N_
BU
CK
0
VD
D_
M
AI
N_
BU
CK
4
VD
D_
M
AI
N_
BU
CK
3
VD
D_
M
AI
N_
BB
CO
RE
VB
AT
VB
AT
VB
AT
VB
AT
_S
VS
S9
VS
S9
VS
S9
VS
S9
VS
S8
VS
S8
VS
S8
VS
S8
VS
S8
VS
S8
VS
S8
VS
S7
VS
S6
VS
S4
VS
S4
VS
S4
VS
S4
VS
S4
VS
S4
VS
S4
VS
S4
VS
S3
VS
S3
VS
S1
VS
S2
SW1_OUT
SW3B_OUT
SW3_IN
SW2_OUT
LDO0_OUT
SW1_IN
D
S
G
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N
C
N
C
N
C
N
C
N
C
Berkelium - 2
To SMC, Device ID=0x3C, READ=0x79, WRITE-0x78 
To T208, Device ID=0x3C, READ=0x79, WRITE-0x78 
T208 POWER ALIASES
We can remove R4304 this once we verify grounding is ok
BUCK0
LDO7
SW3C
SW3A
SW2
BUCK2
BUCK1
SW1
LDO0
BUCK3
Signal Aliases
41 OF 121
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
PP0V8_SLEEP2_BUCK139 
VOLTAGE=0.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=0.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=3.0V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.0520MIN_LINE_WIDTH=0.0900
VOLTAGE=1.1V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
SMBUS_SOC_PMU_SCL
SMBUS_SOC_PMU_SDA
PP1V1_SLEEP3_BUCK237 
PP0V6_SLEEP1_BUCK039 117 
VOLTAGE=0.6V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
PP0V8_SLEEP1_SW1 38 
PP0V8_SLEEP1_SW139 
PP1V8_SLEEP2_SW3A 41 
PP1V8_AWAKE_SW3C 38 
PP1V8_AWAKE_SW3C38 
PP1V8_AWAKE_SW3C 37 38 39 
PP1V8_SLEEP2_SW3A 37 
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
PP1V1_SLEEP1_SW2 37 
PP1V1_SLEEP1_SW2 38 
PP1V1_SLEEP1_SW2 38 
PP1V1_SLEEP1_SW2 38 
PP1V1_SLEEP1_SW2 37 
PP1V1_SLEEP1_SW239 
PP1V1_SLEEP3_BUCK2 39 
PP0V8_SLEEP1_SW1 38 
PP1V8_SLEEP2_SW3A 41 
PP1V8_SLEEP3_BUCK339 
SMC_SOCPMU_RESET46 
PP0V8_SLEEP1_SW1
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
PP1V8_SLEEP2_SW3A37 39 
PP3V0_AWAKE_LDO738 
PP0V6_SLEEP2_LDO039 
PP3V3_S4_SOC_PMU 40 110 
43 OF 145
10.0.0
051-00647
dvt-fab10
PP1V8_AWAKE_SW3C
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PP0V8_SLEEP2_BUCK1
PMU_SOC_VBUS_DET_L
BB_FORCE_PWM
MAKE_BASE=TRUE
PP0V8_SLEEP1_SW1
MAKE_BASE=TRUE
PP3V0_AWAKE_LDO7
MAKE_BASE=TRUE
PP0V6_SLEEP1_BUCK0
MAKE_BASE=TRUE
PP1V1_SLEEP1_SW2
MAKE_BASE=TRUE
PP1V1_SLEEP3_BUCK2
SMBUS_SOC_PMU_BR_SDA
SOC_PMU_I2C_SDA
SMBUS_SOC_PMU_BR_SCL
BB_FORCE_PWM
SOC_PMU_I2C_SCL
SOC_PMU_INCKT_OTP
SMC_SOCPMU_RESET
MAKE_BASE=TRUE
SOC_VDD_HI_LO
PMU_TO_SOC_SLEEP1_PWRGD
SOC_SLEEP1_REQ
PMU_TO_SOC_AWAKE_PWRGD
SOC_PMU_CLK_32K
SMC_SOCPMU_RESET
PMU_TO_SOC_IRQ_L
PMU_TO_SOC_RESET_L
PMU_TO_SOC_VDD_OK
PMU_TO_SOC_SYS_ALIVE
SOC_AWAKE_REQ
PMU_TO_SOC_CLK_32K
PMU_VPUMP
PMU_VDD_RTC
PMU_TCAL_PWR
PMU_VREF
PMU_SOC_VBUS_DET_L
PMU_SOC_UWAKE_L
PMU_IREF
MAKE_BASE=TRUE
PP0V6_SLEEP2_LDO0
PMU_TCAL_GND
PP1V8_SLEEP3_BUCK3
MAKE_BASE=TRUE
PMU_SOC_UWAKE_L
SOC_PMU_INCKT_OTP
PMU_TO_SOC_SYS_ALIVE
PP1V8_SLEEP2_SW3A
MAKE_BASE=TRUE
SYNC_DATE=03/15/2016SYNC_MASTER=X362_T208
BOM_COST_GROUP=T151
Berkelium - 2
0.01UF
25V
10%
0201
X5R-CERM
C43031
2X5R-CERM
16V
0201
10%
0.1UF
C43021
2
0.1%
1/20W
TF200K
0201
R4308
1
2
3.92K
1%
NOSTUFF
201
1/20W
MF
R4307
1
2
5%
100PF
NOSTUFF
25V
C0G
0201
C43001
2
SHORT-8L-0.1MM-SM
OMIT
XW4300
1 2
X5R-CERM
16V
10%
0.1UF
0201
C43011
2
MF01/20W5% 201R4321
1 2
5%
MF
2011/20W 0
R4320
1 2
49 
49 
WLCSP
D2346A1-OTP-CE
U4200
E9
D6
K6
L4
J6
K5
L5
E2
D3
D4
F4
F3
C3
B6
C7
B5
C8
D8
F9
F10
F11
G9
G10
G11
H9
H10
H11
J11
E3
E4
G3
G4
B3
N11
E11
J9
J2
K4
J4
B7
H2
H3
G2
E10
D5
F2
D11
L10
L9
K9
B8
L7
J5
D2
L6
B4
H4
E8 J7 J8 K8 K7
10K
1/20W
201
MF
5%
R43051
2
5%
MF
1/20W100K
201
R4301
1
2
5%
201
1/20W
MF
0
R4315
1
2
37 
37 
37 
38 37 
37 
37 
41 37 
38 
37 
37 
38 37 
38 37 
37 20 
1/20W
MF
5%
201
100K
R4303
1
2
100K
5%
201
MF
1/20W
R4302
1
2
40 38 37 
40 
41 
41 
40 
40 
40 
40 
40 
41 
41 
41 
41 
41 
41 
40 
40 
41 
41 
41 37 
40 37 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BI
IN
SYM 2 OF 2
VS
S8
VS
S8
VS
S8
VS
S8
VS
S8
NTC4
TBAT
NTC3
NTC2
NTC1
AMUX_IN2
AMUX_IN3
AMUX_IN4
GPIO15
AMUX_IN1
GPIO13
GPIO14
GPIO11
GPIO10
GPIO12
GPIO8
GPIO9
GPIO7
GPIO5
GPIO6
GPIO2
GPIO4
GPI3
DBLCLICK_DET
BUTTON3
BUTTON1
BUTTON2
SOC_VDD_CORE_HI_LO
SLEEP1_PWRGOOD
SLEEP1_REQUEST
ACTIVE_PWRGOOD
CLK_32K_IN
CLK_32K_ALT
RESET_IN1
RESET_IN2
IRQ*
RESET*
VDD_OK
SYS_ALIVE
ACTIVE_REQUEST
GPIO1
I2C2_SCL
I2C1_SDA
I2C1_SCL
VPUMP
VDD_RTC
I2C2_SDA
TCAL
VREF
BB_FORCE_PWM
VBUS_DET*
SHDN
INCKT_OTP
UWAKE*
AMUX_OUT
VDD_RTC_DIG
IREF
NC
NC
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
IN
IN
NC
SLG5AP1443V
Load Switch
Current
17 mOhm Typ
EDP: 182mA
3.3V DFR Switch
T208 I2C Mapping
Part
8-bit Address
U4405
R(on)
2.5A Max
@ 3.3V 19 mOhm Max
0x79 0x78
Bus
AP0
Type
7-bit Address
0011110 (0x3C)
DFR Connectors
Write
T208
M34128 EEPROM
0111001 (0x39)
101000x (0x50/0x51)
1010100 (0x4C)
MIPID FILTERING
1010000 (0x50)
0x99 0x98
DFR Disp Conn
Read
0xA1 0xA0
0xA3 0xA2
ALS/DEBUG UART
T208 LEVEL SHIFTING 
0xA1/A3 0xA0/A2
PMU
Device
AOP1 ALS
AP1
AP2_0 Tesla
Touch EEPROM
ACE SWD DBG 
(Default)
ACE
INT PU SOC 50k
SOC
SWD DEBUG MUX 
T208 SWD MUX ACE DBG
0x73 0x72
T208 Support
EDP: 32.6mA
DFR Touch Conn
PCH Mesa EEPROM
ALS
PCH
T208
(When SEL driven high)
SEP
AOP0
ALS I2C 
1010001 (0x51)
SPI TERM
44 OF 145
dvt-fab10
42 OF 121
051-00647
10.0.0
MIN_LINE_WIDTH=0.0900
MIN_NECK_WIDTH=0.0520
VOLTAGE=3.3V
PP3V3_S5_T139 42 
110 
PP3V3_S0_LEFT110 
PP1V8_S037 38 42 109 
PP1V8_S037 109 
PP3V3_S5_T139 42 110 
PP5V_S0_T139110 
PP3V3_S0_LEFT
38 110 
SOC_UART_D2R
SOC_UART_R2D
SOC_SWD_CLK
PP1V8_S438 109 
PP3V3_S4_SOC_PMU
38 42 110 
SOC_SWDIO_DBG 31 
SOC_SWCLK_DBG 31 
PP3V3_S4_SOC_PMU 38 42 110 
MIN_NECK_WIDTH=0.0520 MIN_LINE_WIDTH=0.0900
VOLTAGE=1.8V
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.0520
MIN_LINE_WIDTH=0.0900
PP1V8_S037 38 
42 
109 
PP3V3_S0SW_DFR
DFR_TOUCH_ROM_WC
DFR_DISP_PWR_EN
P3V3S0SW_RAMP
DFR_DISP_TEDFR_TOUCH_LID
DFR_TOUCH_SPI_MISO_R
MESA_SPI_MOSI_R
DFR_TOUCH_SPI_CLK_R SOC_ROM_SPI_MOSI_R
SOC_ROM_SPI_CLK_R
DFR_TOUCH_SPI_MOSI
DFR_TOUCH_SPI_CLK
DFR_TOUCH_SPI_MOSI_R
I2C_ALS_SDA SOC_TO_PCH_UART_TXD
PCH_TO_SOC_UART_TXD
PCH_ALS_TO_SOC_UART_TXD
SOC_TO_PCH_ALS_UART_TXD
I2C_ALS_SCL_R
I2C_ALS_SDA_R
SOC_ALS_LS_EN
ALS_SCL_I2C_1V8 I2C_ALS_SCL
SOC_UART_LS_EN
PCH_SWD_MUX_SEL
SMC_LID
MIPID_CLK_CONN_N
MIPID_DATA_CONN_P
DFR_DISP_PWR_EN
MIPID_CLK_CONN_P
PP1V8_S0SW_DFR
DFR_DISP_RESET_L
PP1V8_S0SW_DFR
MIPID_CLK_N
MIPID_CLK_P
PP1V8_S0SW_DFR
DFR_TOUCH_ROM_I2C_SDA
DFR_TOUCH_ROM_I2C_SCL
MESA_SPI_MOSI
MESA_SPI_CLK_R
SOC_ROM_SPI_MISO
DFRDRV_I2C_SDA
SOC_ROM_SPI_CLK
DFR_TOUCH_SPI_CS_L
MIPID_DATA_P
MIPID_DATA_N
MESA_SPI_CLK
SOC_XB_DBG2_1V8
SOC_XB_DBG1_1V8
ALS_SOC_UART_R2D
ALS_SOC_UART_D2R
PP1V8_S0SW_DFR
SOC_XB_DBG1_1V8
PCH_SWD_IO
SOC_XB_DBG2_1V8
PP1V8_S0SW_DFR
SOC_SWCLK
SOC_SWDIO
ALS_SDA_I2C_1V8
SOC_ROM_SPI_MISO_R
SOC_SWD_LS_EN
MAKE_BASE=TRUE
SOC_SWDIO_DBG
PP1V8_S0SW_DFR
DFR_TOUCH_SPI_MOSI_R
SOC_ROM_SPI_MOSI
MAKE_BASE=TRUE
SOC_SWCLK_DBG
DFR_DISP_RST_L
DFR_TOUCH_SPI_MISO
DFR_TOUCH_GPIO2
DFR_TOUCH_RESET_L
DFR_DISP_VSYNC
DFR_DISP_INT
DFRDRV_I2C_SCL
MIPID_DATA_CONN_N
PP1V8_S0SW_DFR
DFR_DISP_VSYNC
DFR_TOUCH_SPI_MISO_R
DFR_TOUCH_SPI_CLK_R
DFR_DISP_SMC_RST_L
DFR_TOUCH_PANEL_DETECT
DFR_TOUCH_INT_L
DFR_CLKIN_RESET_L
SYNC_DATE=06/30/2016SYNC_MASTER=X362_T208
BOM_COST_GROUP=T151
T208 Support
15 
6.3V
10%
CERM-X5R
0201
0.1UF
PLACE_NEAR=U4408:2mm
C44441
2
TQFN
PI3USB102EZLE
U4408
6
7
3
4
5
810
9
2
1
114 38 
114 38 
114 38 
114 38 
0201
16V
10%
0.1UF
X5R-CERM
C44611
2
NLSX4402
UDFN
U4402
5
4
7
6
2
3
81
1/20W
MF
201
5%
100K
R4460
1
2
0.1UF
0201
16V
10%
X5R-CERM
C44601
2
0.1UF
16V
X5R-CERM
0201
10%
C44411
2
20 
20 
76 42 
20 
20 
5%
MF
100K
1/20W
201
R4444
1
2
10%
16V
0201
X5R-CERM
0.1UF
C44401
2
47K
1/20W
201
5%
MF
R4440
1
2
NLSX5014MU_G
UQFN
U4401
12
6
2
3
4
5
10
9
8
7
111
47K
201
MF
1/20W
5%
R4441
1
2
38 
47K
1/20W
5%
201
MF
R4442
1
2
1/20W
MF
47K
201
5%
R4443
1
2
38 
0201
16V
X5R-CERM
10%
0.1UF
C44511
2
114 76 
MF
1/20W
201
5%
1K
R4472
1
2
114 
76 
1/20W
5%
1K
201
MF
R4471
1
2
MF
1/20W
100K
5%
201
R4470
1
2
16V
10%
0.1UF
0201
X5R-CERM
C44501
2
NLSX4402
UDFN
U4403
5
4
7
6
2
3
81
37 
37 
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
PLACE_NEAR=J4401:2.54mm
GND_VOID=TRUE
GND_VOID=TRUEGND_VOID=TRUE
GND_VOID=TRUE
L4400
1
23
4
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
F-ST-SM
DF40PG(1.5)-26DS-04V(51)J4401
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
PLACE_NEAR=J4401:2.54mm
3.25-OHM-0.1A-2.4GHZ
TAM0605-4SM
GND_VOID=TRUE
L4401
1
23
4
0201
6.3V
10%
CERM-X5R
0.1UF
C44031
2
76 42 
0402
1UF
10V
10%
X5R-CERM
C44021
2
AA07-S022VA1
F-ST-SM
J4402
23
24
25
26
12
34
56
78
910
1112
1314
1516
1718
1920
2122
10V
0201
X7R-CERM
10%
2200PF
C44101
2 X5R
6.3V
20%
1.0UF
0201-1
C44001
2
TDFN
SLG5AP1443V
U4405
7 3
8
2 5
1
38 
38 100
1/20W
5%
201
MF
R4421
1 2
MF
1/20W
5%
201
100
R4420
1 2
10V
0402
X5R-CERM
10%
1UF
C44011
2
MF
100K
1/20W
5%
201
R4492 1
2
NCP160AMX180
XDFN-COMBO
U4404
3
2
4
1
5
25V
0201
100PF
5%
C0G
C44901
2
DFN1006H4-3
DMN32D2LFB4
Q4400
3
1
2
5%
MF
1/20W
24K
201
R44911
2
4.7K
MF
1/20W
201
5%
NOSTUFF
R44851
2
201
MF
10K
1/20W
5%
NOSTUFF
R4480 1
2
PLACE_NEAR=J4401:5mm
10%
10V
X5R-CERM
1UF
0402
C44711
2
10%
0.1UF
0201
X5R
6.3V
C4470 1
2
1/20W
5%
MF
100K
201
R4400 1
2
5%
MF
201
1/20W
4.7K
R4481 1
2
DFN1010
74LVC1G08FW5
U4406
3
1
2
5
4
6
NOSTUFF
1/20W
5%
0
MF
201
R4490
1 2
39 38 
39 38 
39 38 
37 
37 
37 
45 
45 
37 
38 
38 
37 
37 
100
5%
SOC_BOOT:SPI
MF
201
1/20W
PLACE_NEAR=U3906.2:5mmR4450
1 2
SOC_BOOT:SPI
5%
201
0
1/20W
MF
PLACE_NEAR=U3900.D10:5mm R4451
1 2
SOC_BOOT:SPI
MF
201
1/20W
5%
0
PLACE_NEAR=U3900.B10:5mm R4452
1 2
0
MF
1/20W
5%
201
PLACE_NEAR=U3900.Y20:5mm R4454
1 2
201
MF
1/20W
5%
0
PLACE_NEAR=J4402.7:5mmR4453
1 2
PLACE_NEAR=U3900.AB21:5mm
0
5%
201
MF
1/20W
R4455
1 2
0
201
MF
5%
1/20W
PLACE_NEAR=U3900.B9:5mm R4457
1 2
201
MF
5%
0
1/20W
PLACE_NEAR=U3900.C9:5mm R4456
1 2
114 38 
114 38 
114 38 
114 42 38 
114 
38 37 
114 
38 37 
114 37 
114 38 
15 
37 
37 
76 
38 
114 38 
114 
42 38 
114 38 
114 38 37 
114 38 37 
20 15 
114 
114 
114 42 
114 42 
114 42 
114 48 47 43 
114 42 37 
114 
114 42 37 
114 42 37 
42 
42 
114 
42 37 
42 
42 
114 42 37 
114 42 37 
114 42 
114 42 
114 42 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
M-
M+
Y-
Y+
D-
D+
OE*SEL
GND
VCC
IN
IN
IN
IN
VCCVL
IO/VCC2
IO/VCC1
GND
IO/VL1
IO/VL2
EN
IN
OUT
IN
IN
OUTIOLV[4]
IOLV[3]
IOLV[2]
IOLV[1]
IOVCC[4]
IOVCC[3]
IOVCC[2]
IOVCC[1]
EN
VL VCC
GND
OUT
IN
BI
OUT
VCCVL
IO/VCC2
IO/VCC1
GND
IO/VL1
IO/VL2
EN
IN
BI
SYM_VER-1
GND
GND
GND
GND
SYM_VER-1
NC
IN
CAP
ON S
D
VDD
GND
IN
OUT
OUT
EPAD GND
EN
IN
D S
GSY
M
_V
E
R
_2
NC
B
Y
A
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
OUT
IN
OUT
BI
IN
IN
IN
BI
BI
IN
OUT
BI
IN
IN
OUT
OUT
OUT
IN
BI
IN
TPAD CONNECTORKBD CONNECTOR
MATE WITH PLUG 516S00054
518S00177 (RCPT, 0.3A per pin)
TRACKPAD ISOLATION GATES/FET
516S00187, MATE WITH 516S00188
43 OF 121
PP5V_S4110 
PP3V3_S4_TPAD43 110 
PP5V_S0_KBD43 110 
PP3V3_G3H48 109 
PP5V_S0_KBD 43 110 
VOLTAGE=0V
VOLTAGE=5V
PP5V_S0 56 110 117 SMC_ACTUATOR_DISABLE_L48 
SMC_PME_S4_WAKE_L48 
PP3V3_S4110 
PPBUS_S4_HS_TPAD109 
SMBUS_SMC_3_SDA 49 
PP3V3_S4_TPAD43 110 
SMBUS_SMC_3_SCL 49 
VOLTAGE=0V
VOLTAGE=12.6V
PP3V3_S043 110 
VOLTAGE=5V
PP3V3_S4_TPAD43 110 
PP3V3_S043 110 
PP3V3_S4_TPAD43 110 PP3V3_SUS110 
45 OF 145
10.0.0
051-00647
dvt-fab10
2.5A-16V-0.1OHM
TPAD_SPI_INT_L
100K
TPAD_SPI_INT_L_CONNTPAD_SPI_IF_EN
FAN_LT_PWM
FAN_LT_TACH
PP5V_S0_FAN_CONN
GND_FAN
PP5V_S0_FAN_CONN
FAN_RT_TACH
FAN_RT_PWM
GND_FAN
KBD_BLC_GSSOUT
KBD_BLC_GSLAT
KBD_I2C_SDA
KBD_BLC_XBLANK
KBD_BLC_GSSIN
KBD_BLC_GSSCK
KBD_BLC_GSSCK
TPAD_SPI_CLK
SMC_LID
KBD_I2C_SCL
KBD_BLC_XBLANK
TPAD_SPI_MOSI
TPAD_SPI_MISO
TPAD_SPI_CLK_CONN
TPAD_SPI_IF_EN_CONN KBD_BLC_GSSOUT
TPAD_SPI_INT_L_CONN
ACT_GND
PPVIN_S4_TPAD_FUSE
PPVIN_S4_TPAD_FUSE
SMC_VIBE_L
KBD_I2C_SDA
KBD_BLC_GSSIN
ACT_GND
KBD_INT_L
KBD_BLC_GSLATPP5V_S4_TPAD_CONN
SMC_LSOC_RST_L
KBD_I2C_SCL
KBD_INT_L
PM_SLP_S4_L
TPAD_SPI_CS_L_CONN
TPAD_SPI_CS_L_CONNTPAD_SPI_CS_LTPAD_SPI_IF_EN_CONN
SYNC_MASTER=X363_SAMANTHA SYNC_DATE=01/08/2016
Connectors&ESD
BOM_COST_GROUP=KEYBOARD
1812
F4500
1 2
SM
XW4502
1 2
SM
XW4500
1 2
NOSTUFF
201
5%
MF
1/20W
0
R4541
12
NOSTUFF
201
5%
MF
1/20W
0
R4531
12
NOSTUFF
201
5%
MF
1/20W
0
R4520
12
74LVC1G08GW
SOT353
U4540
3
2
1
4
5
MF
201
1/20W
5%
R45401
20201
16V
10%
0.1UF
X5R-CERM
C45401
2
MF
201
1/20W
5%
100K
R45301
2
DFN1006H4-3
DMN32D2LFB4
Q4530
3
1
2
74LVC1G08FW5
DFN1010
U4520
3
1
2
5
4
6
X5R-CERM
0201
16V
10%
0.1UF
C45201
2
DF40PC-40DS-0.4V-51
F-ST-SM
J4500
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
5%
NP0-C0G
0201
25V
12PF
NOSTUFF
C4511 1
2
5%
0
201
1/20W
MF
R4510
1 2
SM
XW4501
1 2
DF40C-50DS-0.4V-51
CRITICAL
F-ST-SM
J4501
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
FERR-120-OHM-1.5A
0402A
L4500
1
2
0.1UF
X5R
25V
10%
402
C4500 1
2
15 
114 43 15 
115 114 56 
115 114 56 
114 43 
114 43 
115 114 56 
115 114 56 
114 43 
114 43 
114 43 
114 43 
114 43 
114 43 
114 43 
114 43 
114 13 
114 48 47 42 
114 43 
114 43 
114 13 
114 13 
114 43 114 43 
114 43 
114 43 
114 43 
114 46 
114 43 
114 43 
114 43 
114 43 
114 43 
114 48 
114 43 
114 43 
73 70 46 20 12 
114 43 
114 43 13 114 43 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
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A
D
2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
A
Y
B
G
S
SYM_VER_3
D
NC
B
Y
A
NC
Debug Stuff Was Here
dvt-fab10
051-00647
10.0.0
44 OF 121
47 OF 145
SYNC_DATE=08/26/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=DEBUG
External A USB3 Connector
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
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DRAWING NUMBER SIZE
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 IV ALL RIGHTS RESERVED
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A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
3.0V MESA
Option to feed LDO from 5V in case of dropout issue
EDP:100mA
1.8V MESA
I2C pullups on same rail as EEPROM VCC
EDP:12.5mA
EDP:1.5mA
MOJAVE 16V BOOST
ISOLATE FROM OTHER COMPONENTS/NETS AS MUCH AS POSSIBLE
Power On: 1V8 -> 3V3 -> 16V0
Mesa Power Sequencing Requirements
Recptacle (516S00203) - X362/X363 MLB
PLUG (516S00115) - X434/ X435 Jumper
Proto1 Connector for X434/X435 Support
MESA FLEX CONNECTOR
45 OF 121
PP3V3_S4_T15145 110 
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3000
VOLTAGE=0V
PP3V3_S4_T15145 110 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
VOLTAGE=1.8V
PP3V3_S4_T15145 110 
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
VOLTAGE=16V
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.0V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
VOLTAGE=3.0V
VOLTAGE=17V
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1200
PP3V3_S4_T15145 110 
VOLTAGE=16V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
49 OF 145
10.0.0
051-00647
dvt-fab10
PP3V3_S4_MESA_SW
PP1V8_MESA_CONN
PP3V0_MESA_CONN
PP1V8_MESA_CONN
P16V0_AGND
MESA_I2C_SCL
MESA_SNSR_INT_CONNMENU_KEY_L
MESA_BOOST_EN_CONN
MESA_SPI_MOSI_CONN
MESA_BOOST_EN
MESA_SNSR_INTMESA_SPI_MOSI_R
PP1V8_MESA
MESA_PWR_EN
PP1V8_MESA
MESA_BOOST_EN
PP16V0_MESA PP16V0_MESA_CONN
PP3V0_MESA_CONNPP3V0_MESA
MOJAVE_EN_M
MESA_I2C_SDA
PP3V0_MESA
PP17V0_MOJAVE_LDOIN
MESA_SPI_MISO
PP1V8_MESA PP1V8_MESA_CONN
MESA_I2C_SCL
MESA_BOOST_EN_CONN MESA_SPI_MOSI_CONN
MESA_SNSR_INT_CONN
MESA_SPI_MISO_CONN
MESA_I2C_SDA
PP16V0_MESA_CONN
MENU_KEY_L
PP16V0_MESA
MESA_SPI_CLK_CONN
SMC_ONOFF_LMESA_SPI_MISO_CONN
MESA_SPI_CLK_CONNMESA_SPI_CLK_R
BOM_COST_GROUP=T151
MESA
SYNC_MASTER=X362_P49 SYNC_DATE=01/08/2016
114 45 37 
114 45 37 37 
1/20W
5%
0201
MF
0R49161 2
NOSTUFF
MF
0201
5%
1/20W
0R49151 2
SHORT-0201
XW4900
1 2
X5R-CERM
0402
10V
10%
1UF
C49161
2
1UF
X5R-CERM
0402
10%
10V
C49111
2
XDFN-COMBO
NCP160AMX300
U4910
3
2
4
1
5
1/20W
5%
201
MF
2.2K
R49211
2
1/20W
5%
201
MF
2.2K
R49201
2
NP0-C0G
56PF
5%
25V
0201
C49261
2
2.2UF
25V
20%
X5R
0402-3
C49251
2
0402-3
2.2UF
X5R
25V
20%
C49241
2
LM3638
BGA
U4900
B3
B2
A3
C2
A1
C1
B1
A2 C3
1UF
X5R-CERM
10%
10V
0402
C49141
2
1UF
X5R-CERM
0402
10%
10V
C49121
2
0201
X5R-CERM
16V
0.1UF
10%
C4928 1
2
100PF
25V
C0G
0201
5%
C4929 1
2X5R-CERM
2.2UF
0201
6.3V
20%
C49201
2 X5R-CERM
0201
6.3V
20%
2.2UF
C49211
2
0201
6.3V
20%
2.2UF
X5R-CERM
C49221
2
2.2UF
X5R
20%
25V
0402-3
C49231
2
X5R-CERM
0201
6.3V
20%
2.2UF
C49181
2
0201
5%
100PF
25V
C0G
C49171
2
0201
25V
100PF
5%
C0G
C49271
2
0201
80-OHM-25%-500MA
FL4920
1 2
0201
80-OHM-25%-500MA
FL4910
1 2
80-OHM-25%-500MA
0201
FL4900
1 2
42 
42 
38 
1/20W
5%
MF
201
0R49111 2
25V
5%
0201
C0G
100PF
C49551
2
MF
201
1/20W
5%
680R49541 2
100PF
0201
25V
5%
C0G
C49541
2
5%
680
1/20W
MF
201
R4953
1 2
100PF
0201
25V
5%
C0G
C49531
2
PLACE_NEAR=J4900:3MM
MF
5%
0
1/20W
0201
R4912
1 2
5%
NP0-C0G
56PF
25V
0201
C49521
2
201
56
5%
1/20W
MF
R4951
1 2
5%
0201
NP0-C0G
56PF
25V
C49511
2
56PF
NP0-C0G
0201
5%
25V
C49501
2
0402-9
6.3V
20%
CERM-X5R
10UF
C49101
2
5%
0
0201
MF
1/20W
R4950
1 2
F-ST-SM
505066-1220
J4900
12
34
56
78
910
1112
1314
1516
LP5907SNX-1.825
X2SON
U4920
3
2 5
4 1
1.0UH-0.4A-0.636OHM
0402
L4901
1 2
114 45 
114 45 
114 45 
114 45 
114 45 
114 45 
45 
45 
45 
45 114 45 
114 45 45 
45 
45 114 45 
114 45 37 
114 45 
114 
45 
114 45 
114 45 
114 45 37 
114 45 
114 45 
45 
114 45 
114 
45 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
ININ
OUT
EPADGND
EN
IN
PMID
VOUT
EN_S
LDOIN
EN_M
SW
VIN
PG
ND
AG
ND
OUT
OUTIN
IN
OUT
VIN
EN
EPADGND
VOUT
Unused pins have "SMC_Pxx" names. Unused
(OD)
(IPD when sampling)
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
(OD)
(OD)
(OD)
(OD)
NOTE:
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
NOTE:
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(IPD)
(IPU)
(OD)
(OD)
(OD)
(IPD)
(OD)
(IPU)
(OD)
46 OF 121
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
SMC_GPU_VDDCI_ISENSE
SMC_CPUGT_VSENSE
TP_SMC_DEBUGPRT_EN_L
SMC_GFX_PWR_LEVEL_L
NC_SPI_SMC_MISO
NC_SPI_SMC_CLK
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.2V
MIN_LINE_WIDTH=0.2000
SMC_CPU_HI_ISENSE
SMC_CPU_IMON_ISENSE
SMC_CPUSA_VSENSE
SMC_CPUDDR_ISENSE
SMBUS_SMC_4_G3H_SCL
SMBUS_SMC_4_G3H_SDA
TP_SYS_ONEWIRE
SMC_GPU_HS_ISENSE
SMC_SSDLIM_ISENSE
SMC_GPU_FB_ISENSE
SMC_CPUSA_ISENSESMBUS_SMC_2_S4_SCL
SMBUS_SMC_2_S4_SDA
SMC_DCIN_VSENSE
SMC_CPUGT_ISENSE
SMC_GPU_FBIC_ISENSE
SMC_GPU_VDDCI_VSENSE
SMC_GPU_1V8_ISENSE
SMC_DDR1V2_ISENSE
SMC_GPU_CORE_VSENSE
SMC_GPU_CORE_ISENSE
SMC_DCIN_ISENSE
SMC_SOCPMU_RESET
SMC_BMON_ISENSE
SMC_PBUS_VSENSE
SMC_CPU_ISENSE
NC_SMC_DP_HPD_L
NC_SPI_SMC_CS_L
NC_SPI_SMC_MOSI
SMC_CPU_VSENSE
SMC_CPUGT_IMON_ISENSE
PP3V3_G3H 47 76 109 
50 OF 145
10.0.0
051-00647
dvt-fab10
PP3V3_S5_SMC_VDDA
PM_SLP_S4_L
CPU_CATERR_L
PM_THRMTRIP_L
SMC_TOPBLK_SWP_L
SMC_PME_S4_WAKE_L
SMC_PCH_SUSWARN_L
SMC_CLK12M_EN
NC_SMC_OSC1
SMC_WAKE_L
BUF_SMC_RESET_L
NC_SMC_HIB_L
PM_RSMRST_L
SMBUS_SMC_5_G3_SCL
LPC_FRAME_L
LPC_AD<1>
PP1V2_S5_SMC_VDDC
SMC_BT_PWR_EN
SMC_CBC_ON
PM_DSW_PWRGD
SMC_FAN_1_CTL
PM_PCH_SYS_PWROK
SMC_PECI_L
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SDA
SMC_FAN_0_TACH
SMC_GFX_SELF_THROTTLE
SMC_DEV_SUPPLY_L
SMC_PCH_SUSACK_L
CPU_PECI_R
SMC_FAN_0_CTL
SMC_FAN_1_TACH
SMC_SENSOR_PWR_EN
SMC_ACTUATOR_DISABLE_L
GND_SMC_AVSS
PP3V0_S5_AVREF_SMC
SMC_CLK32K
SYSCLK_CLK12M_SMC
SMBUS_SMC_3_SCL
SMC_PM_G2_EN
SMC_BC_ACOK
CPU_PROCHOT_L
SMBUS_SMC_0_S0_SDA
SMC_WAKE_SCI_L
LPC_SERIRQ
LPC_AD<0>
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_1_S0_SDA
LPC_CLKRUN_L
SMC_TDO
SMC_TMS
SMC_TCK
LPC_CLK24M_SMC
LPC_AD<3>
LPC_AD<2>
LPC_PWRDWN_L
SMC_LRESET_L
SMBUS_SMC_1_S0_SCL
SMC_CHGR_INT_L
PM_BATLOW_L
SMC_OOB1_R2D_L
SMC_OOB1_D2R_L
SMC_ADAPTER_EN
PM_PWRBTN_L
PM_SYSRST_L
SMC_GFX_OVERTEMP
TCON_BKLT_PWM
SMC_WIFI_EVENT_L
SMC_RUNTIME_SCI_L
ALL_SYS_PWRGD
NC_SMC_XOSC1
SMC_THRMTRIP
S5_PWRGD
SMC_PROCHOT
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
SMC_USBC_INT_L
SMC_ONOFF_L
SMC_WIFI_PWR_EN
SMC_DEBUGPRT2_RX_L
SMC_VCCIO_CPU_DIV2
SPI_DESCRIPTOR_OVERRIDE_L
SMC_DELAYED_PWRGD
PM_SLP_S5_L
SMC_LID_RIGHT
SMC_SENSOR_ALERT_L
SMC_PME_S4_DARK_L
SMC_PMIC_INT_L
SMC_LID_LEFT
PM_SLP_S3_L
PM_SLP_S0_L
SMC_DEBUGPRT2_TX_L
SMC_TDI
SMC_VIBE_L
SMC
BOM_COST_GROUP=SMC
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
114 43 
48 
47 
48 
48 
48 
48 
48 36 35 
48 
76 48 
TM4EA231H6ZXRI
OMIT_TABLE
BGA
U5000
A10
D5
D6
D9
E5
E8
E9
E10
F5
F9
G5
G9
H5
H8
J5
J6
J7
J8
K9
F2
F4
L13
B7
F13
F12
B9
C9
B10
C10A11
F11
K13
E6
E7
F6
F7
F8
G6
G7
G8
H6
H7
F3
D7
H9
J1
J9
J13
E2
E1
M13
K11
K12
TM4EA231H6ZXRI
BGA
OMIT_TABLE
U5000
L3
K5
N2
N3
L4
M4
N4
L5
E11
D11
D13
D12
A4
B4
E3
E4
M3
M2
N1
M1
B1
C1
D3
D4
A2
A1
C3
C2
G1
G2
G3
G4
B3
A3
C5
C4
L10
N11
N12
M11
K10
M10
N10
K8
N9
M9
L9
L8
M8
N8
N5
M5
L2
L1
K3
K2
K1
J3
J2
J4
D8
A8
B8
C8
A6
B6
C7
C6
H4
H3
H1
H2
B11
A12
B12
A13
C11
B13
D10
C12
C13
E12
E13
F10
G12
G11
G13
G10
H10
H13
H11
A5
B5
K4
A9
L12
M12
N13
L11
J10
H12
K6
J11
J12
K7
A7
L6
D2
D1
F1
M6
N6
L7
M7
N7
19 
89 
48 47 13 6 
47 
48 47 
BYPASS=U5000.H9::5MM
6.3V
X5R
0201-1
1.0UF
20%
C50171
2
BYPASS=U5000.J9::5MM
6.3V
X5R
0201-1
1.0UF
20%
C50141
2
10%
0.1UF
10V
X5R-CERM
BYPASS=U5000.J1::5MM
0201
C50121
2
BYPASS=U5000.J13::5MM
X5R-CERM
10V
10%
0.1UF
0201
C50111
2
48 
BYPASS=U5000.E1:F2:1MM
10%
0.01UF
X5R-CERM
10V
0201
C50201
2
BYPASS=U5000.E1:F2:1MM
6.3V
X5R
0201-1
1.0UF
20%
C50211
2
114 48 
41 
BYPASS=U5000.E6::5MM
6.3V
X5R
0201-1
1.0UF
20%
C50021
2
0.1UF
X5R-CERM
10%
10V
0201
C50011
2
BYPASS=U5000.D7::5MM
6.3V
X5R
0201-1
1.0UF
20%
C50101
2
BYPASS=U5000.J9::5MM
X5R-CERM
10V
10%
0.1UF
0201
C50131
2
BYPASS=U5000.D7::5MM
X5R-CERM
0.1UF
10%
10V
0201
C50151
2
BYPASS=U5000.H9::5MM
10%
0.1UF
X5R-CERM
10V
0201
C50161
2
48 
35 
6 
114 73 12 
48 
48 
48 
65 47 6 
FERR-30-OHM-2.2A-0.035-OHM
0402
L5001
1 2
19 
73 
48 
48 
48 
19 
103 29 12 
70 47 
103 48 47 29 
114 48 47 45 
73 20 12 
73 70 43 20 12 
114 101 89 76 73 70 27 20 12 
70 20 12 
48 47 
103 29 
114 48 47 
48 
56 
56 
48 
47 
56 
56 
47 
47 
12 
47 
115 18 12 
48 18 
47 
73 70 
89 48 
64 
48 
48 
48 
48 
115 73 18 12 
114 47 29 
114 47 29 
47 
47 
12 
73 70 47 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
48 
114 49 
114 49 
48 
48114 49 
114 49 
48 
48 
49 
49 
114 49 
114 49 
12 
12 
12 
12 
20 
89 12 
12 
89 12 
89 12 
89 12 
89 12 
BYPASS=U5000.G8::5MM
10V
10%
X5R-CERM
0.1UF
0201
C50071
2
0.1UF
10%
10V
X5R-CERM
BYPASS=U5000.E6::5MM
0201
C50031
2
BYPASS=U5000.F6::5MM
10%
10V
X5R-CERM
0.1UF
0201
C50041
2
BYPASS=U5000.H6::5MM
10%
10V
0.1UF
X5R-CERM
0201
C50081
2
10%
0.1UF
10V
X5R-CERM
BYPASS=U5000.H7::5MM
0201
C50091
2
BYPASS=U5000.F8::5MM
0.1UF
X5R-CERM
10%
10V
0201
C50051
2 10V
0.1UF
10%
X5R-CERM
BYPASS=U5000.G6::5MM
0201
C50061
2
1M
5%
201
MF
1/20W
R50021
2
47 
PLACE_NEAR=U5000.A10:6MM
SM
XW5000
12
55 
53 
51 
50 
48 
47 
47 
47 
114 57 47 
114 57 47 
47 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
BI
OUT
OUT
IN
IN
OUT
IN
NC
IN
SYM 2 OF 2
VREFA-
GNDA
GNDA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDA
VDDC
VDDC
XOSC1
XOSC0
OSC0
OSC1
VBAT
VDDC
VDDC
VDDC
RST*
WAKE*
HIB*
PK4
NC
VREFA+
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
PC0/SWCLK/TCK
PC1/SWDIO/TMS
PC3/SWO/TDO
PC2/TDI
SYM 1 OF 2PL3
PM2
PM0
PM1
PG0
PA2/SSI0CLK
PJ7
PH2
PN7
PJ6
PN4
PN5
PH3
PN2
PK7
PM7
PM6
PK6
PN3
PN0
PK5
PL1
PL0
PM5
PL4
PL5
PM4
PB2/I2C0SCL
PB3/I2C0SDA
PA6
PA7
PF6
PF7
PG1
PG2
PG3
PG7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PQ0
PQ1
PQ2
PQ3
PQ4
PQ5
PQ6
PQ7
PA0/U0RX
PA1/U0TX
PL7
PL6
PE2
PE1
PD6
PD5
PD4
PE5
PE4
PB4
PD2
PD0
PK0
PK1
PK2
PA3/SSI0FSS
PA4/SSI0RX
PA5/SSI0TX
PF0
PF1
PF2
PF3
PF4
PF5
PG4
PG5
PH0
PH1
PH4
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PM3
PG6
PB5
PD3
PD1
PB7
PB6
PK3
PE7
PE6
PN1
PC7
PB1
PB0
PJ4
PJ5
PC5
PC4
PC6
PD7
PE0
PE3
PL2
PN6
IN
OUT
IN
IN
IN
BI
BI
OUT
OUT
OUT
IN
IN
BI
OUT
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
IN
IN
IN
BI
BI
BI
BI
IN
From/To CPU/PCH
PROCHOT/THRMTRIP Support PECI Support
To SMC
From SMC
Place near CPU
SMC AVREF Supply
Top-Block Swap
47 OF 121
MIN_LINE_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
VOLTAGE=3.0V
PP3V3_S0 110 
PP1V0_S347 110 SMC_BC_ACOK
PP1V0_S3 47 110 
PP3V3_S448 110 
PP3V3_S0110 
PP3V3_G3H46 76 109 
PP3V3_G3H109 
MIN_LINE_WIDTH=0.4000
VOLTAGE=0V
MIN_NECK_WIDTH=0.1000
51 OF 145
10.0.0
051-00647
dvt-fab10
PP3V0_S5_AVREF_SMC
SMC_CLK32K
SMC_ADAPTER_EN
SMC_VCCIO_CPU_DIV2
CPU_PECI_R
SMC_THRMTRIP_LPM_THRMTRIP_L
CPU_PROCHOT_L SMC_PROCHOT_L
SMC_PROCHOT CPU_PECI
PCH_STRP_TOPBLK_SWP_L
PM_CLK32K_SUSCLK_R
SMC_TOPBLK_SWP_L
SMC_THRMTRIP
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_WIFI_EVENT_L
SMC_PMIC_INT_L
SMC_BC_ACOK
MAKE_BASE=TRUE
SMC_DELAYED_PWRGD
SMC_PM_G2_EN
SMC_THRMTRIP
SMC_ONOFF_L
SMC_TDI
SMC_LID
SMC_SENSOR_ALERT_L
SMC_TCK
SMC_BC_ACOK
SMC_TDO
SMC_TMS
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
GND_SMC_AVSS
SMC_PECI_L
SMC Shared Support
BOM_COST_GROUP=SMC
SYNC_MASTER=J80_ZIFENGSHEN_MLB_BAFFIN SYNC_DATE=11/19/2015
CRITICAL
TS3330-COMBO
QFN
U5165
4
5
1
2
3
6
7
8
2011/20W5% MF
100KR5192 1 2
15 
1/20W
1K
201
MF
5%
R51821
2
5%
1K
MF
201
1/20W
R5183
1 246 
0201
10V
10%
X5R-CERM
0.1UF
C51671
2
20%
6.3V
10UF
0402-1
CERM-X5R
C5166 1
2
20%
1.0UF
0201-1
X5R
6.3V
C5165 1
2
2011/20W5% MF
10KR5186 1 2
5% 1/20W MF 201
100KR5191 1 2
100K
5% 1/20W 201MF
R5185 1 2
2011/20W5% MF
100KR5166 1 2
48 46 13 6 
PLACE_NEAR=Q5159.3:5MM
1/20W
1%
201
MF
100
R5159
1 2
65 46 6 
PLACE_NEAR=Q5159.6:5MM
1/20W
1%
201
MF
100
R5158
1 2
DMN5L06VK-7
SOT563
Q5159
6
21
DMN5L06VK-7
SOT563
Q5159
3
54
MF 2015% 1/20W
100KR5169 1 2 5% 201MF
100K
1/20W
R5168 1 2
NOSTUFF
0201
47PF
C0G
PLACE_NEAR=Q5150.2:5MM
5%
25V
C5134 1
2
201
10K
MF5% 1/20W
R5172 1 2
CRITICAL
DFN1006H4-3
DMN32D2LFB4
Q5150 3
1 2
MF
5%
1/20W
33
201
R5134
1 246 13 6 
1/20W5% 201MF
100KR5167 1 2
1/20W
5%
201
MF
330
R51511
2
46 
1/20W
1%
201
MF
100K
R51961
2
1/20W
1%
201
MF
100K
R51971
2
1/20W5% 201MF
20KR5176 1 2 1/20W5% 201MF
20KR5175 1 2
46 
201
5%
MF
1/20W
22
R5112
1 212 
NOSTUFF 100K
1/20W5% 201MF
R5187 1 2
46 
47 46 
NOSTUFF
1/20W5% 201MF
10KR5180 1 2
NOSTUFF 10K
1/20W5% 201MF
R5179 1 2
NOSTUFF 10K
1/20W5% MF 201
R5178 1 2
NOSTUFF 10K
1/20W5% 201MF
R5177 1 2
NOSTUFF
1/20W5% 201MF
330KR5171 1 2
MF 2011/20W5%
10KR5170 1 2
46 
46 
46 
47 46 
114 48 46 
103 48 46 29 
46 
70 46 
48 47 46 
46 
73 70 46 
114 48 46 45 
46 
114 48 43 42 
48 46 
114 57 46 
48 47 46 
46 
114 57 46 
114 46 29 
114 46 29 
55 53 51 50 48 46 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC1
NC2
IN
NC3
NC0
NC4
OUT
G
ND
OUTIN
NC
NC
NC
NC
NC
OUT
BI
GS
D
VER 3
GS
D
VER 3
D
SG
SYM_VER_2
OUT BI
IN
OUTIN
IN
IN
Debug Power "Buttons"
SMC12 ADC Assignments
Thermal Alerts
Specify one of these BOM GROUPs.
Specify one of these BOM GROUPs.
Debug RESET "Buttons" Hall Effect Pads - Left
Hall Effect Pads - Right
SMC12 Pin Assignments
S4 SMC Wake Sources
48 OF 121
SMC_PCH_SUSWARN_L
SMC_PCH_SUSACK_L
SMC_SENSOR_PWR_EN 74 
SMC_SENSOR_PWR_EN 50 
TP_SMC_DEBUGPRT_EN_L46 
SMBUS_SMC_4_G3H_SCL 46 
SMC_GPU_HS_ISENSE
PP3V3_S447 110 
SMC_CPU_HI_ISENSE
TP_SYS_ONEWIRE46 
SMC_GFX_PWR_LEVEL_L46 
SMC_DCIN_VSENSE
SMC_BMON_ISENSE
SMC_CPUGT_VSENSE
SMC_GPU_VDDCI_VSENSE
SMC_GPU_1V8_ISENSE
SMC_CPUDDR_ISENSE
SMC_CPUSA_ISENSE
SMC_CPUSA_VSENSE
SMC_CPU_VSENSE
SMC_CPU_IMON_ISENSE
SMC_CPUGT_IMON_ISENSE
SMC_CPU_ISENSE
SMC_SSDLIM_ISENSE
SMC_GPU_VDDCI_ISENSE
SMC_GPU_FBIC_ISENSE
SMC_PBUS_VSENSE
SMC_DCIN_ISENSE
SMC_BC_ACOK 64 
SMC_CHGR_INT_L 64 
SMC_ACTUATOR_DISABLE_L 43 
SMC_OOB1_D2R_L 77 80 114 
SMC_BC_ACOK 50 
SMBUS_SMC_4_G3H_SDA 46 
SMC_CPUGT_ISENSE
SMC_GPU_CORE_ISENSE
SMC_GPU_CORE_VSENSE
SMC_DDR1V2_ISENSE
PP3V3_G3H 43 109 
NC_SPI_SMC_MISO46 
NC_SPI_SMC_CS_L46 
PM_PWRBTN_L 12 
PP3V3_G3H48 109 
SMBUS_SMC_2_S4_SCL 46 
SMBUS_SMC_2_S4_SDA 46 
SMC_OOB1_R2D_L 77 80 114 
PP3V3_G3H 48 109 
PP3V3_G3H 48 109 
SMC_GPU_FB_ISENSE
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
NC_SMC_DP_HPD_L46 
NC_SPI_SMC_CLK46 
NC_SPI_SMC_MOSI46 
PP3V3_G3H 109 
52 OF 145
10.0.0
051-00647
dvt-fab10
PM_THRMTRIP_L
SMC_CPUGT_IMON_ISENSE
MAKE_BASE=TRUE
NC_SPI_SMC_CLK TRUE
MAKE_BASE=TRUE
SMC_PME_S4_DARK_L
SMC_LSOC_RST_L
MAKE_BASE=TRUE
SMC_PME_S4_WAKE_L
SMC_LID_LEFT_R
SMC_SENSOR_ALERT_L
BKLT_PWM_TCON2MLBTCON_BKLT_PWM
SMC_LID_RIGHT
SMC_DEV_SUPPLY_L
NC_SPI_SMC_MOSI TRUE
MAKE_BASE=TRUE
SMC_CPU_ISENSE
SMC_WIFI_PWR_EN
SMC_SENSOR_PWR_EN
TBTTHMSNS_T_ALERT_L
CPUTHMSNS_THM_L
TBTTHMSNS_T_THM_L
SMC_CPUSA_ISENSE
MAKE_BASE=TRUE
SMC_GPU_FBIC_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_DDR1V2_ISENSE
SMC_GPU_FB_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_CPUSA_VSENSE
CPUTHMSNS_ALERT_L
MAKE_BASE=TRUE
SMC_GPU_1V8_ISENSE
SMC_CPUHI_COMP_ALERT_L
TBTTHMSNS_X_ALERT_L
SMC_PCH_SUSACK_L
MAKE_BASE=TRUE
NC_SMC_DP_HPD_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_GFX_PWR_LEVEL_L
TP_SMC_DEBUGPRT_EN_L
MAKE_BASE=TRUE
SMC_GPU_HS_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_SYS_ONEWIRE
MAKE_BASE=TRUE
SMC_CPUGT_VSENSESMC_PBUS_VSENSE
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_GPU_CORE_ISENSE
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
SMC_ONOFF_L
SMC_CPU_VSENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_4_G3H_SDA
MAKE_BASE=TRUE
SMBUS_SMC_2_S4_SDA
MAKE_BASE=TRUE
SMBUS_SMC_2_S4_SCL
MAKE_BASE=TRUE
SMC_OOB1_R2D_L
SMC_OOB1_D2R_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_CHGR_INT_L
SMC_ACTUATOR_DISABLE_L
MAKE_BASE=TRUE
SMC_CPUDDR_ISENSE
MAKE_BASE=TRUE
SMBUS_SMC_4_G3H_SCL
MAKE_BASE=TRUE
SMC_BC_ACOK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_GPU_VDDCI_ISENSE
MAKE_BASE=TRUE
SMC_SSDLIM_ISENSE
TBTTHMSNS_X_THM_L
MAKE_BASE=TRUE
SMC_CPUGT_ISENSE
SMC_CPU_IMON_ISENSE
MAKE_BASE=TRUE
SMC_GPU_CORE_VSENSE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_BMON_ISENSE
MAKE_BASE=TRUE
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
SMC_GPU_VDDCI_VSENSE
GND_SMC_AVSS
SMC_4FINGERS_RST
NC_SPI_SMC_MISO TRUE
SMC_GFX_OVERTEMP
SMC_PCH_SUSWARN_L
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
MAKE_BASE=TRUE
PM_PWRBTN_L
MAKE_BASE=TRUE
SMC_DEBUGPRT2_TX_L
SMC_RESET_L
SMC_ONOFF_L
SMC_LID_R
SMC_LID_LEFT
SMC_LID
BUF_SMC_RESET_L
NC_SPI_SMC_CS_L TRUE
SMC_LID_RIGHT
SMC_LID_LEFT_R
HALL_SENSOR_RIGHT
HALL_SENSOR_LEFT
SMC_DEV_SUPPLY_R_L
WLAN_UART_RX
WLAN_UART_TXSMC_DEBUGPRT2_RX_L
SMC_DEBUGPRT2_R_TX
SMC_DEBUGPRT2_R_RX
CPUTHRM_THRM:SMC,CPUTHRM_ALRT:SMCCPUTHRM:BOTH
CPUTHRM_ALRT:SMCCPUTHRM:ALRT
TBTTHRM_THRM:PU,TBTTHRM_ALRT:PUTBTTHRM:NONE
TBTTHRM:BOTH TBTTHRM_THRM:SMC,TBTTHRM_ALRT:SMC
TBTTHRM_THRM:SMC,TBTTHRM_ALRT:PUTBTTHRM:THRM
CPUTHRM:THRM CPUTHRM_THRM:SMC
TBTTHRM_THRM:PU,TBTTHRM_ALRT:SMCTBTTHRM:ALRT
SMC Project Support
BOM_COST_GROUP=SMC
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
201
1/20W
100
5%
MF
TBTTHRM_ALRT:SMC
R5210
1 254 
TP-P6 TP5201
1
TP-P6
TP52001
114 47 46 
NOSTUFF
3300PF
X7R-CERM
0201
10V
10%
C5257 1
2
201
10
MF
5%
1/20W
R5260
12
MF
1/20W
201
0
5%
R5259
1 2
NOSTUFF
0201
1000PF
16V
X7R-1
10%
C5260 1
2
NOSTUFF 16V
0201
10%
X7R-1
1000PF
C5250 1
2
48 46 
10K
MF
5%
1/20W
201
R5253
1 2
201
MF
10K
1/20W
5%
R5252
1 2
46 
LID_FEATURE_OFF
201
MF
1/20W
5%
0
R52571
2
5%
MF
201
LID_FEATURE_ON
1/20W
0
R5258
1 2
100K
5%
1/20W
MF
201
R52561
2
5%
201
MF
1/20W
10K
R52811
2
MF
5%
1/20W
201
100K
R52801
2
MF
0
5%
1/20W
0201
PLACE_SIDE=BOTTOM
R5278
1 2
PLACE_SIDE=BOTTOM
0
5%
1/20W
MF
0201
R5277
1 2
MF
PLACE_SIDE=BOTTOM
NOSTUFF
1/20W
0201
5%
0
R5276
1 2
PLACE_SIDE=BOTTOM
0
5%
0201
NOSTUFF
1/20W
MF
R5275
1 2
BYPASS=U5256.5::5MM
10V
10%
0.1UF
X5R-CERM
0201
C5256 1
2
64 
CRITICAL
SOT553-5
SN74LVC1G02
U5256
1
2
3
5
4
114 43 
114 48 47 46 45 
47 46 13 6 
89 46 
DFN1006H4-3
DMN32D2LFB4
CRITICALQ52903
12
43 
BOMOPTION=DBG_BTN
SILK_PART=PWR_BTN
SM
PLACE_SIDE=BOTTOM
EVQPUA02K
SW5200
1
3
2
4
114 76 64 57 29 
BOMOPTION=DBG_BTN
SOX-152HNT
CRITICAL
SM
SILK_PART=RESET_BTN
PLACE_SIDE=BOTTOM
SW5227
1 2
35 
SM
OMIT_TABLE
AMR-MLB-X502
J5260
1
2
3
45
6
7
8
AMR-MLB-X502
OMIT_TABLE
SM
J5250
1
2
3
45
6
7
8
54 
54 
201
5%
MF
100
1/20W
TBTTHRM_ALRT:SMCR5211
1 2
54 TBTTHRM_THRM:SMC
100
201
1/20W
5%
MF
R5221
1 2
5%
1/20W
MF
201
100K
R52741
2
10K
MF
201
5%
1/20W
R52731
2
114 48 47 46 45 
BOMOPTION=OMIT
PLACE_SIDE=TOP
RES
0603-NSP
SILK_PART=PWR_BTN
R5226
12
114 47 43 42 
201
1/20W
5%
MF
10K
R5255
1 2
BYPASS=U5255.6::5MM
X5R-CERM
0.1UF
10V
10%
0201
C5255 1
2
74LVC1G32
SOT891
CRITICAL
U5255
2
1
35
6
4
12 46 
46 12 
55 
55 
55 
51 
1/20W
NOSTUFF
5%
100
201
MF
R5217
1 2
NOSTUFF
1/20W5% MF
10K
201
R5294 1 2
2015% MF
NOSTUFF
1/20W
10KR5295 1 2
55 
55 
53 
51 
NOSTUFF
16V
0201
X7R-CERM
10%
1000PF
C5270 1
2
54 
54 
100
201
MF
TBTTHRM_THRM:SMC
1/20W
5%
R5220
1 2
100
MF
5%
CPUTHRM_THRM:SMC
1/20W
201
R5216
1 2
50 
53 
51 
55 
55 
51 
55 
55 
53 
55 
53 
55 51 
55 53 
50 
50 
47 46 
50 
50 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
46 
MF
5%
201
CPUTHRM_ALRT:SMC
100
1/20W
R5214
1 2
115 
103 47 46 29 
48 
114 76 46 
48 46 
46 
115 
46 36 35 
48 46 
89 
49 
49 
49 
46 
46 
46 
114 46 
49 
47 46 
55 53 51 50 47 46 
115 
48 46 
46 18 
46 
76 46 
115 
48 
114 
35 
35 46 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
IN
A
A
OUT
OUT
OUT
OUT
02
IN
IN
OUT
IN
D
S G
SYM_VER_2
IN
OUT
IN
IN
IN
IN
OUT
OUT
NC
NC
OUTIN
OUT IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
USB-C PORT CONTROLLER XA
thru
(Write: 0x20 Read: 0x21)
SMC SMBus "0" S0 Connections
(Write: 0x3E Read: 0x3F)
SMC SMBus "1" S0 Connections
CPU, Mem, Airflow,
Fixstack Prox
TMP513AISAR:U5870
USB-C PORT CONTROLLER TB
CD3215A (ACE) - UB300
(WRITE: 0X4E READ: 0X4F)
(WRITE: 0X40 READ: 0X41)
UA000
(Write: 0x82 Read: 0x83)
(MASTER)
U5000
USB-C PORT CONTROLLER TA
(WRITE: 0X70 READ: 0X71)
(WRITE: 0X7E READ: 0X7F)
CD3215A (ACE) - U3100
USB-C PORT CONTROLLER XB
Battery
LYNX POINT LP S0 "SMBus 0" Connections
SMC
GPU
TMP442A: UA960
(Write: 0x98 Read: 0x99)
GPU THERM
( when VRR_FLAG = 0 )
16 addresses
Internal DP
DPMUX Connections
DPMUX IC
(MASTER)
(Write: 0xB8 Read: 0xB9)
LYNX POINT LP
SMLink 1 is slave port to
DPMUX Connections
U9800
(MASTER)
LYNX POINT LP S0 "SMLink 0" Connections
(MASTER)
DPMUX IC
U9800
LYNX POINT LP
(MASTER)
U0500
SMC
EADC2
U0500
(MASTER)
LYNX POINT LP
(MASTER)
U5000
(MASTER)
SMC
ISL6259 - U7000
U0500
access PCH. 
U5000U5000
J6950
TMP105: J9510
(Write: 0x88 Read: 0x89)
SMC SMBus "5" G3H Connections
SMC SMC
SMC
CD3215A (ACE) - U3200
CD3215A (ACE) - UB400
(Write: 0x16 Read: 0x17)
Battery Charger
(Write: 0x12 Read: 0x13)(MASTER)
TBT & Airflow Left
X100 Temp
Banjo
(Write: 0x92 Read: 0x93)
U5000
LYNX POINT LP S0 "SMLink 1" Connections
TMP461: U5800
(Write: 0x96 Read: 0x97)
(MASTER)
(Write: 0x90 Read: 0x91)
TMP461: U5850
TBT & Airflow Right
SMC SMBUS "4" G3H CONNECTIONS
J4501
Trackpad
Berkelium
(Write: 0x78 Read: 0x79)
U6000
EADC1
(Write: 0x99 Read: 0x98)
UGLY HACK
SMC SMBus "2" S4 Connections
(Write: 0x10 Read: 0x11)
U5700
CARBON
(Write: 0xD5 Read: 0xD4)
U5710
(Write: 0x14 Read: 0x15)
U4200U5000
J8500
SMC SMBus "3" S0 Connections
U7800
(Write: 0x68 Read: 0x69)
49 OF 121
dvt-fab10
051-00647
10.0.0
53 OF 145
PP3V3_G3H109 
PP3V3_S0110 
SMBUS_SMC_5_G3_SDA 63 
SMBUS_SOC_PMU_SDA 41 
SMBUS_SOC_PMU_SCL 41 
SMBUS_SMC_2_S4_SDA 53 
SMBUS_SMC_3_SCL56 
SMBUS_SMC_1_S0_SCL 54 
PP3V3_S0110 
PP3V3_S089 98 110 
NC_I2C_DPMUX_A_SDA89 
SMBUS_SMC_5_G3_SCL70 
SMBUS_SMC_3_SDA 54 
PP3V3_S049 110 
I2C_DPMUX_UC_SCL89 
NC_I2C_DPMUX_A_SCL89 
I2C_DPMUX_UC_SDA89 
PP3V3_S049 110 
SMBUS_SMC_2_S4_SCL 53 
PP3V3_G3H109 
SMBUS_SMC_5_G3_SCL 64 
SMBUS_SMC_1_S0_SDA15 
SMBUS_SMC_1_S0_SCL15 
SMBUS_SMC_5_G3_SCL 63 
SMBUS_SMC_5_G3_SDA 64 
SMBUS_SMC_4_G3H_SDA 29 
SMBUS_SMC_4_G3H_SCL 29 
SMBUS_SMC_4_G3H_SCL 29 
SMBUS_SMC_4_G3H_SDA103 
SMBUS_SMC_4_G3H_SDA103 
SMBUS_SMC_0_S0_SDA 76 114 
SMBUS_SMC_2_S4_SDA 53 
SMBUS_SMC_3_SCL 54 
SMBUS_SMC_3_SDA 54 
SMBUS_SMC_1_S0_SCL100 
SMBUS_SMC_4_G3H_SDA 29 
SMBUS_SMC_1_S0_SDA100 
SMBUS_SMC_0_S0_SCL 76 114 
SMBUS_SMC_1_S0_SDA 99 
SMBUS_SMC_1_S0_SCL
99SMBUS_SMC_4_G3H_SCL103 
SMBUS_SMC_3_SDA 54 
SMBUS_SMC_5_G3_SDA70 
SMBUS_SMC_4_G3H_SCL103 
SMBUS_SMC_1_S0_SDA 54 
PP3V3_S0110 
SMBUS_SMC_3_SCL 54 
SMBUS_SMC_3_SCL 54 
SMBUS_SMC_3_SDA56 
SMBUS_SMC_3_SCL43 
PP3V3_S4110 
SMBUS_SMC_3_SDA
SMBUS_SMC_2_S4_SCL 53 
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_5_G3_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SCL
MAKE_BASE=TRUE
SMBUS_PCH_CLK
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
SMBUS_SOC_PMU_SCL
SMBUS_SMC_2_S4_SDA
SMBUS_SMC_2_S4_SCL
SMBUS_SMC_3_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_I2C_DPMUX_A_SCL
MAKE_BASE=TRUE
NC_I2C_DPMUX_A_SDA
MAKE_BASE=TRUE
I2C_DPMUX_UC_SCL
MAKE_BASE=TRUE
I2C_DPMUX_UC_SDA
MAKE_BASE=TRUE
SML_PCH_0_CLK
MAKE_BASE=TRUE
SML_PCH_0_DATA
SMBUS_SOC_PMU_SDA
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_4_G3H_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMBUS_SMC_4_G3H_SDA
SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
BOM_COST_GROUP=SMC
SMBus Connections
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
1/20W
MF
5%
0201
0
R5373
1 2
0
5%
0201
MF
1/20W
R5372
1 2
1/20W
5%
2.0K
MF
201
R53051
2 201
MF
1/20W
2.0K
5%
R53061
2
5%
MF
201
1K
1/20W
R53011
2
1/20W
MF
5%
201
1K
R53001
2
201
1/20W
MF
1K
5%
R53711
2
1/20W
1K
MF
201
5%
R53701
2
1/20W
5%
201
MF
8.2K
R53101
2
1.5K
MF
1/20W
5%
201
R53211
2
1.5K
MF
5%
1/20W
201
R53201
2
1/20W
5%
201
MF
8.2K
R53111
2
2.0K
MF
5%
201
1/20W
R53811
2
2.0K
201
MF
5%
1/20W
R53801
2
1.5K
1/20W
201
5%
MF
R53511
2
1.5K
5%
201
MF
1/20W
R53501
2
201
MF
5%
2.0K
1/20W
R53911
2
1/20W
5%
2.0K
201
MF
R53901
2
201
MF
1/20W
5%
2.0K
R53611
2
1/20W
MF
5%
201
2.0K
R53601
2
114 46 
114 46 
114 46 15 
15 
48 
48 
114 46 
15 
15 
114 46 
46 
46 
48 
48 
114 46 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
(PRODUCTION)
(PRODUCTION)(PRODUCTION)
(PRODUCTION)
(PRODUCTION)SMC ADC: 00 
CPU High Side Current Sense (IC0R)
Vsense: 16.8 mV, Range: 30 A 
Rsense: 0.001 (R5400)
Gain: 100x, EDP: 16.8 A
Charger (BMON) Current Sense (IPBR)
Trackpad Actuator X239 Current Sense (ITAR)
Rsense: 0.02 (R5460)
LCD Backlight Current Sense (IBLR)
Vsense: 21.75 mV, Range: 1.32 A
Vnominal: 12.6 V, Range: 17.97 V 
DC In Voltage Sense & Enable (VD0R)
Charger Gain: 20x, EDP: 4.6 A
Gain: 49.8x, EDP: 2.61 A (Transient)
Vsense: 52.2 mV, Range: 3.31 A
100x 
100x 
EADC1: CH0
PBUS Voltage Sense & Enable (VP0R)
EADC2: CH7 
Enables PBUS VSense
SMC ADC: 01 
Rthevenin = 4573 Ohms
divider when in S0.
Gain: 0.167x
200x SMC ADC: 02 
Rsense: 0.005 (R7060)
200x 
Gain: 1000uA/V * 24.9KOhm = 24.9
SMC ADC: 03 
Rsense: 0.020 (R7020)
DC-IN (AMON) Current Sense (ID0R)
Alert circuit)
(to CPU High Side Threshold
Charger Gain: 20x, EDP: 7.2 A
Rthevenin = 4573 Ohms
SMC ADC: 04 
divider when AC present.Enables DC-In VSense
Vnominal: 20 V, Range: 22 V 
Gain: 0.13067x
Rsense: 0.025 (R8400)
Gain: 100x. EDP: 0.87 A
SMC ADC:8 
Gain: 200x, EDP: 1.22 A
OTHER 5V High Side Current Sense (IO5R)
Gain: 200x, EDP: 4.31 A
Vsense: 12.93 mV, Range: 5 A
Rsense: 0.003 (R5440) or Rsense SHORT
OTHER 3.3V High Side Current Sense (IO3R)
SMC ADC:7 
Rsense: 0.01 (R5410) or Rsense SHORT
Vsense: 12.2 mV, Range: 1.5 A 
50 OF 121
PP3V3_S4SW_SNS50 51 52 53 55 110 
SMC_BC_ACOK
PP3V3_S4SW_SNS50 110 
PPBUS_HS_CPU109 
PPBUS_G3H109 
PP3V3_S4SW_SNS50 51 52 53 55 110 
PPBUS_G3H109 
PP3V3_S0_LEFT110 
SMC_SENSOR_PWR_EN
PPBUS_G3H
PP3V3_S4SW_SNS52 55 110 50 51 53 
PP3V3_S4SW_SNS50 110 
PPBUS_HS_OTH3V3109 117 
PPBUS_G3H109 
PPBUS_S4_HS_TPAD
PP3V3_S4SW_SNS50 51 52 53 55 
110 
PPBUS_HS_OTH5V109 
PPBUS_G3H109 
54 OF 145
10.0.0
051-00647
dvt-fab10
0.005
R5440
0.005
OMIT PLACE_NEAR=U5410.2:3:10MM
PLACE_NEAR=U5440.2:3:10MM
PLACE_NEAR=U5410.4:5:10MM
ISNS_HS_OTHER5V_N
ISNS_HS_OTHER5V_P
0.005
R5410 1
43
21
0306-SHORT
2
1 3
40306-SHORT
2
3
40306-SHORT
MF
1/3W
R5400
PLACE_NEAR=U5400.6:5MM
C5429
PLACE_NEAR=U5000.G2:5MM
GND_SMC_AVSS
PPDCIN_G3H
PLACE_NEAR=U5000.G2:5MM
HS_OTHER5V_IOUT
PLACE_NEAR=U5410.10:5MM
PLACE_NEAR=U5700.22:5MM
EADC1_LCDBKLT_ISENSE
UQFN
TPADISNS
TPADISNS
TPADISNS TPADISNS
R5465
ISNS_X239_IOUT
BYPASS=U5450.6::5MM
R5468
ISNS_TPAD_P
201
1/20W
1%CRITICAL
ISNS_X239_IOUT_BUF
ISNS_X239_INT_I
1/20W
1 C5469
0.22UF
TPADRC:YES
PLACE_NEAR=U5710.5:5MM
PLACE_NEAR=U5710.5:5MM
4.53K
MSOP
1/3W
MF
PLACE_NEAR=U5460.4:7MM
ISNS_TPAD_N
R5467
1
5
CRITICAL
U5462
OPA2340
ISNS_X239_INT_NITPADISNS
OMIT
OMIT
1%
U5450
CRITICAL
LOADISNS
R5460
PLACE_NEAR=U5460.3:7MM
1%
TPADISNS
R5469
SMC_TPAD_ISENSE
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
U5460
4
LOADRC:NO
C5419,C54492
OTHERISNS
OTHERISNS
1/3W
PLACE_NEAR=U5440.4:5:10MM
MF
1%
ISNS_HS_OTHER3V3_N
10K
1 C5469 TPADRC:NO117S0008
6.3V
5
PLACE_NEAR=U5710.4:5MM
ISNS_HS_OTHER3V3_P
OTHERISNS R5445
HS_OTHER3V3_IOUT
1/20W
2
OTHERRC:YES
C5459
OTHERISNS
0.22UF
OTHERRC:YES
PLACE_NEAR=U5700.3:5MM
OTHERISNS
BYPASS=U5410.6::5MM
6.3V
LOADISNS
117S0008
0.22UF
6.3V
0201
20%
LOADRC:YESPLACE_NEAR=U5700.22:5MM
LOADISNS
ISNS_LCDBKLT_N
PLACE_NEAR=R8400.3:5MM
INA214A
0.1UF
0201
MF
DCINVSENS_EN_L
DCIN_S5_VSENSE
PDCINVSENS_EN_L_DIV
PBUSVSENS_EN_L_DIV
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
SMC_DCIN_VSENSE
GND_SMC_AVSS
EADC1_OTHER5V_HI_ISENSE
CHGR_AMON
GND_SMC_AVSS
GND_EADC1_COM
GND_EADC2_COM
GND_EADC2_COM
GND_EADC1_COM
SMC_PBUS_VSENSE
PBUS_S0_VSENSE
PBUS_S0_VSENSE_IN
SMC_BMON_ISENSECHGR_BMON
GND_SMC_AVSS
ISNS_X239_IOUT_INT
SMC_DCIN_ISENSE
ISNS_LCDBKLT_P ISNS_LCDBKLT_IOUT
EADC2_OTHER3V3_HI_ISENSE
SMC_CPU_HI_ISENSECPUHI_IOUT
PBUSVSENS_EN_L
GND_SMC_AVSS
Power Sensors: High Side
BOM_COST_GROUP=SENSORS
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
1
117S0008 OTHERRC:NO
MF
201
1%
300K
1/20W
R5429
1 2
48 
53 
X5R
C54591
2
1%
1/20W
MF
201
453K
R5459
1 2
2200PF
X7R-CERM
0201
10%
10V PLACE_NEAR=U5000.G1:5MM
C54391
2
PLACE_NEAR=U5400.5:10MM
PLACE_NEAR=U5400.4:10MMCRITICAL
0.001
1W
1%
0612
MF-3
1
2
3
4
1/20W
201
45.3K
MF
1%
PLACE_NEAR=U5000.G1:5MM
R5439
1 2
48 
53 
PLACE_NEAR=U5710.4:5MM
6.3V
0.22UF
0201
20%
X5R
C54491MF
1%
201
453K
R5449
1 2
PLACE_NEAR=R5400.1:70 MM
SM
XW5480
1 2
48 
48 
CRITICAL
NTUD3169CZ
SOT-963
Q5480
6
3
2
5
1
4
48 
48 
0.22UF
X5R
0201
20%
6.3V PLACE_NEAR=U5000.G3:5MM
C54891
2
PLACE_NEAR=U5000.C2:5MM6.3V
20%
X5R
0.22UF
0201
C54991
2
53 
SOT963
CRITICAL
DMC31D5UDJ
Q5490
6
3
2
5
1
4
CRITICAL
INA214
SC70
U5400
2
5
4
6
1
3
6
7
4
8
MSOP
OPA2340
U5462
2
3
1
4
8
UQFN
PLACE_NEAR=R8400.4:5MM
9
4
2
5
3
1
7
10
8
6
CRITICAL
INA210A
U5440
9
4
2
5
3
1
7
10
8
6
PLACE_NEAR=U5000.G4:5MM
201
1/20W
1%
MF
4.53K
R5409
1 2
UQFN
OTHERISNS
CRITICAL
INA210A
U5410
9
4
2
3
1
7
10
8
6
201
MF
1/20W
1%
PLACE_NEAR=U5000.C2:5MM
31.6K
R54981
2
201
MF
1/20W
5.49K
1%
PLACE_NEAR=U5000.G3:5MM
R54891
2
201
4.75K
PLACE_NEAR=U5000.C2:5MM
1%
1/20W
MF
R54991
2
201
MF
1/20W
27.4K
1%
R54881
2
0.22UF
PLACE_NEAR=U5000.G4:5MM
6.3V
20%
X5R
0201
C54091
2
MF
1%
201
1/20W
200K
R54921
2
1%
1/20W
69.8K
MF
201
R54911
2
1%
100K
1/20W
MF
201
R54821
2
201
100K
1%
1/20W
MF
R54811
2
PLACE_NEAR=U5460.1:5MM
201
TPADISNS
MF
1/20W
24.9K
1%
R54611
2
0201
10%
CERM-X5R
TPADISNS
6.3V
0.1UF
BYPASS=U5462.8::5MM
C5462 1
2
BYPASS=U5460.5::5MM
CERM-X5R
TPADISNS
6.3V
10%
0.1UF
0201
C5460 1
2
0201
10%
CERM-X5R
6.3V
C54501
2
10%
CERM-X5R0.1UF
BYPASS=U5440.6::5MM
C54411
2
0201
0.1UF
CERM-X5R
10%
C54111
2
CERM-X5R
BYPASS=U5400.3::5MM
10%
6.3V
0.1UF
0201
C54011
2
MF
1 2
114 64 
1/20W
201
10K
MF
1%
1 2
MF
10K
1%
201
2
INA139
SOT23-5
CRITICAL
TPADISNS
2
15
3
6.3V
0201
20%
X5R
C54191
2
453K
201
MF
1%
1/20W
PLACE_NEAR=U5700.3:5MM
R5419
1 2
53 
109 
X5R
20%
6.3V
0201
2
1/20W
MF
201
1%
1 2
109 
51 
1/20W
201
15K
5%
MF
R54051
2
201
1%
MF
6.04K
PLACE_NEAR=U5450.10:5MM
1/20W
LOADISNS
R54551
2
48 
15K
1/20W
1%
201
OTHERISNS
PLACE_NEAR=U5440.10:5MM
1
2
1%
MF
15K
1/20W
201
OTHERISNS
R54151
2
75 
75 
X7R-CERM
10%
0201
10V
3300PF
1
2
114 64 
46 55 
52 
116 114 64 29 
52 
55 53 51 50 48 47 46 
55 53 51 50 48 47 46 
53 52 51 50 
53 52 51 50 
53 52 51 50 
53 51 50 
55 53 51 50 48 47 46 
53 51 50 48 47 
55 53 51 50 48 47 46 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
OUT
IN
OUT
OUT
OUT
D
S
S
P-CHANNEL
G
D
G
N-CHANNEL
IN
OUT
OUT
D
S
S
P-CHANNEL
G
D
G
N-CHANNEL
GND
V+
REFIN+
IN- OUT
V-
V+
V-
V+
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
IN
V+
VIN-VIN+
OUT
GND
OUT
OUTIN
OUT
OUT
IN
IN
IN
T139 Current Sense (IF3C)
Rsense: 0.005 (R5510) or Rsense SHORT
SMC ADC: 18 
CPU DDR 1.2V S3 (CPU Only) Current Sense (IMCC)
100x 
Trip Target on CPU High current: TBD A
1.8V Current Sense (I18C)
PCH 1.0V Current Sense (ISCC)
CPU High Side Current (IC0R) Threshold Alert
DDR 1.2V S3 (CPU & Memory) Current Sense (IM0C)
Rsense: 0.05 (R5580) or XWTBD
Vsense: 25.05 mV, Range: 1.88 A
Rsense: 0.01 (R5530) or Rsense SHORT
WLAN Current Sense (IAPC)
200x 
Gain: 200x, EDP: 0.06 A
Rsense: 0.05 (R5520) or Rsense SHORT
Vsense: 3 mV, Range: 0.25 A 
EADC1: CH3 
200x 
BT Current Sense (IBTC)
Vth = 0.616 V -> 2.054 A on CPU High current
Gain: 100x
Vsense: 10 mV, Range: 3 A 
Vtl = 0.771 V -> 2.571 A on CPU High current 
Gain: 200x, EDP: 1.67 A
145x 
EADC1: CH4
200x 
EADC2: CH05 
200x 
Gain: 100x, EDP: 9.01 A
Gain: 200x, EDP: 0.06 A
Rsense: 0.001 (R5400)
SMC ADC: 09 
Vsense: 11.33 mV, Range: 5 A
Vsense: 27.03 mV, Range: 10 A
Rsense: 0.003 (R7918) or XWTBD
Gain: 200x, EDP: 4.11 A
Rsense: 0.003 (R8004) or XWTBD
CPU Fixed Current Sense (ICAC)
Hysteresis Margin = 0.518 A 
Vref = 0.737 V
EADC1: CH1 
Gain: 200x, EDP: 0.7 A
Vsense: 17.5 mV, Range: 0.6 A
Gain: 177.71x, EDP: 67 A
Rsense: 0.025 (R8024) or Rsense SHORT
Rsense: 3x of 0.00075 (R7210, R7220,R7230), Rsum: 0.00025
Vsense: 16.75 mV, Range: 67.52 A 
SMC ADC: 22 
SMC ADC: 06 
200x 
Gain: 200x, EDP: 2 A
Hysteresis Circuit:
Vsense: 3 mV, Range: 0.25 A
51 OF 121
PP3V3_S5_T139110 
PP3V3_S4SW_SNS50 51 
53 55 110 
52 
PP3V3_S0110 
PP3V3_S4_WLAN110 
PP3V3_S4SW_SNS50 51 
52 53 
55 
110 PP3V3_S0110 
PP3V3_S4SW_SNS50 51 52 53 
55 110 
PP3V3_S5110 
PP3V3_S4110 
VOLTAGE=5V
PP5V_S453 110 
PP3V3_S4SW_SNS50 
51 
52 
53 55 110 
PP1V2_S3_CPUDDR109 
PP3V3_S4SW_SNS50 51 52 
53 55 110 
PP3V3_S4SW_SNS50 52 53 55 110 51 
PP3V3_S4_BT110 
PP3V3_S4110 
PP1V2_S3109 
55 OF 145
10.0.0
051-00647
dvt-fab10
0306-SHORT
R5510
OMIT
PLACE_NEAR=R7918.4:5MM
PLACE_NEAR=R8004.3:5MM
PLACE_NEAR=R8004.4:5MM
ISNS_1V0_P
LOADISNS
0306-SHORT
PLACE_NEAR=R5533.1:10MM
0.005
R5530
R5580
0.005
1%
2
1 3
4
2
1 3
40306-SHORT
NOSTUFFPLACE_NEAR=U5590.10:5MM
117S0008 DDRRC:NO1 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5579
LOADISNS
C5519,C5529,C5539,C5549,C5589,C5599
20K
LOADISNS
BYPASS=U5590.6::5MM
0.1UF
CERM-X5R
P1V8SUS_IOUT
R5595
PLACE_NEAR=U5700.23:5MM
BMON_IOUT_D
CPUHI_COMP_VREF
1/20W
R5589
NO_XNET_CONNECTION=1
PLACE_NEAR=U5540.4:5MM
X5R
6.3V
LOADRC:YES
GND_SMC_AVSS
EADC2_BT_ISENSE
LOADRC:YES
C5589
X5R-CERM
NOSTUFF
EADC1_P1V8SUS_ISENSE
C5599
0.22UF
EADC1_PP3V3S4_WLAN_ISENSE
PLACE_NEAR=U5700.2:5MM
PLACE_NEAR=U5000.H1:5MM
48 
R5565
C5560
MF
C5579
0.22UF
GND_SMC_AVSS
PLACE_NEAR=U5000.B5:5MM
NOSTUFF
0.22UF
C5569
6.3V
X5R
0201
PLACE_NEAR=U5000.B3:5MM
SMC_DDR1V2_ISENSE
LOADRC:NO
0.1UF
C5551
6 RES,MTL FLIM,100K,1/16W,0201,SMD,LF
LOADRC:YES
1/20W
5%
R5552
CPUHYS
LOADISNS
0201
LOADISNS
BYPASS=U5580.6::5MM
R5585
CRITICAL
PLACE_NEAR=U5580.2:3:10MMOMIT
ISNS_CPUDDR_N
ISNS_BT_N
MF
1/3W
PLACE_NEAR=U5580.4:5:10MM
GND_EADC2_COM
CPUVR_ISNS_N
R5543
2.55K
CERM-X5R
PLACE_NEAR=R5532.1:10MM
ISNS_CPUDDR_P
PLACE_NEAR=R7918.3:5MM
ISNS_WLAN_P
LOADISNS
LOADISNSD5530
ISNS_WLAN_R_P
2
5
1
4
3
U5530
IAPC_OPA_OUT
CRITICAL
LOADISNS
LTC2050HVCS5
TSOT23-5
ISNS_WLAN_R_N
LOADISNS
OMIT
OMIT
R5520
0.005
1/3W
GND_EADC1_COM
MF
1%
1/3W
1/20W
PLACE_NEAR=U5700.1:5MM
LOADRC:YES
0201
1/20W
R5529
BYPASS=U5520.6::5MM
PLACE_NEAR=U5700.1:5MM
LOADISNS
0.005
0306-SHORT 2
1 3
4
PLACE_NEAR=U5520.4:5:10MM
MF
1%
PLACE_NEAR=U5520.2:3:10MM
MF
1/20W
0201
ISNS_BT_P
PLACE_NEAR=U5000.H1:5MM
PLACE_NEAR=U5510.4:5:10MM
PLACE_NEAR=U5570.6:5MM DDRRC:YES
GND_SMC_AVSS
5%
20K
1/20W
201
NOSTUFF
U5510
INA210
1%
2 0201
NOSTUFF
LOADRC:YES
ISNS_1V8_SUS_P
CRITICAL
LOADISNS
PLACE_NEAR=U5700.23:5MM
GND_EADC1_COM
LOADISNS
7
53 
R5539
LOADISNS
R5551PLACE_NEAR=R7220:5MM
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
PLACE_NEAR=R7210:5MM
CPUCORE_ISNS2_P
LOADISNS
1/20W
5%
LOADISNS
BYPASS=U5540.5::5MM
PLACE_NEAR=U5000.A1:5MM
SMC_CPU_ISENSE
MF
NOSTUFF
NO_XNET_CONNECTION=1
R5519
DDRISNS
1/20W
R5599
RB521ZS-30
PLACE_NEAR=U5000.B3:5MM
1/20W
2
PLACE_NEAR=R8024.3:5MM
DDRISNS
BYPASS=U5570.3::5MM
C5570
4.53K
CERM-X5R
U5570
1/3W
1%
R5575
ISNS_T139_N
BYPASS=U5530.6::5MM
ISNS_1V8_SUS_N
PLACE_NEAR=R8024.4:5MM
117S0008
LOADISNS
ISNS_CPUDDR_IOUT
20K
NO_XNET_CONNECTION=1
LOADISNS
LOADISNS
R5515
CRITICAL
5
LOADISNS
2
1 3
4
PLACE_NEAR=U5510.5:3:10MM
NOSTUFF
4
CPUHI_IOUT_R
ISNS_PP3V3S0_IOUT
CPUVR_ISNS_R_N
ISNS_1V0_N
CPUCORE_ISNS3_N
CPUCORE_ISNS2_N
PCH_1V0_IOUT
ISNS_BT_IOUT
ISNS_CPUVDDQ_P
SMC_CPUHI_COMP_ALERT_L
CPUCORE_ISNS1_P
CPUCORE_ISNS3_P
CPUVR_ISNS_R_PCPUVR_ISNS_P
CPUCORE_ISNS1_N
CPUHI_COMP_OUT
GND_EADC1_COM
CPUHI_IOUT
CPUHI_COMP_FB
GND_SMC_AVSS
SMC_CPU_IMON_ISENSE
ISNS_DDR_IOUT
PP5V_S4_ISNS_D
ISNS_PP3V3S4_WLAN_IOUT
ISNS_CPUVDDQ_N
ISNS_T139_P
ISNS_WLAN_N
SMC_CPUDDR_ISENSE
CPUVR_ISUM_IOUT
EADC1_PP3V3S5_T139_ISENSE
BOM_COST_GROUP=SENSORS
Power Sensors: Load Side
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
48 
4.53K
1/20W
1%
201
R5549
1 2
PLACE_NEAR=U5000.A1:5MM
0.22UF
20%
C55491
2
ISL28133
LOADISNSCRITICAL
SC70-5
U5540
3
1
4
2
5
66 
66 
66 
66 
0201
1/20W
MF
0.1%
17.4K
LOADISNS
R55341
2201
100K
5%
MF
1/20W
LOADISNS
R55351
2
DMP31D0UFB4
LOADISNSDFN1006H4-3
Q5530
3
1
2
DSF01S30SCAP
SC2
A K
55 48 
72 
72 
LOADISNS
CERM-X5R
0201
6.3V
10%
0.1UF
BYPASS=U5560.6::5MM
1
2
20%
1
2
NO_XNET_CONNECTION=1
201
1/20W
453K
1%
PLACE_NEAR=U5000.B5:5MM
NOSTUFF
R5569
1 2
PLACE_NEAR=U5560.10:5MM
201
NOSTUFF
1/20W
MF
51K
5%
1
2
CRITICAL
INA210A
UQFN
U5560
9
4
2
5
3
1
7
10
8
6
53 
6.3V
10%
0201
0.1UF
C55801
2
20K
201
1/20W
5%
MF
NOSTUFF
1
2
0201
20%
2.2UF
6.3V
1
2
MF
1%
4.53K
1/20W
201
1 2
LOADISNS
UQFN
INA210A
U5580
9
4
2
5
3
1
7
10
8
6
LOADISNS
120
1/20W 0.1% 0201MF
R5532
1 2
1/20W MF0.1% 0201
120
LOADISNSR5533
1 2
MF
0.1%
LOADISNS
1 2
66 
LOADISNS
PLACE_NEAR=R7230:5MM
0.1%
1/20W
MF
4.42K
0201
R5550
1 2
66 
1/20W 0201
MF
PLACE_NEAR=R7230:5MM
NO_XNET_CONNECTION=1
0.1%
4.42K1 2
72 
72 
DDRISNS
CRITICAL
SC70INA214
2
5
4
6
1
3
INA210A
UQFN
U5590
9
4
2
5
3
1
10
8
6
LOADISNS
CRITICAL
INA210A
UQFN
U5520
9
4
2
5
3
1
7
10
8
6
SC70
2
6
1
3
10%
0201
6.3V
C55901
2
255K
CPUHYS
201
1%
1/20W
MF
R5553
1 2
LOADISNS
0.1%
MF
715K
0201
NO_XNET_CONNECTION=1
R55441
2
0201
LOADISNS
715K
0.1%
1/20W
MF
R5541
1 2
0201
6.3V
10%
CERM-X5R
0.1UF
C55521
2
X7R
0201
6.3V
10%
0.1UF
C55401
2
MF
4.42K
1/20W 0201
0.1%
R5548
1 2
02011/20W
MF0.1%
PLACE_NEAR=R7210:5MM
4.42K
LOADISNS
NO_XNET_CONNECTION=1
R5547
1 2
PLACE_NEAR=R7220:5MM
0.1%
4.42K
MF
1/20W 0201
R5546
1 2
LOADISNS
NO_XNET_CONNECTION=1 MF0.1%
4.42K
1/20W 0201
R5545
1 2
0.1UF
0201
6.3V
10%
CERM-X5R
C55301
2
0.1UF
6.3V
0201
10%
CERM-X5R
C55201
2
LOADISNS
0.1UF
6.3V
0201
10%
CERM-X5R
BYPASS=U5510.3::5MM
C55101
2
0.1UF
10%
6.3V
0201
1
2
0201
0.1%
2.55K
LOADISNS
1/20W
MF
R5542
1 2
50 
1/20W
MF
201
5%
1
2
201
MF
1%
453K1 2
6.3V
20%
0201
X5R
1
2
53 
1%
12K
201
MF
CPUHYS
R5556
1 2
MF
201
PLACE_NEAR=U5510.6:5MM
5%
1/20W
1
2
CPUHYS
SC70-5
CRITICAL
MAX9119EXK-T
U5551
3
4
1
5
2
6.3V
0201
X5R
0.22UF
NOSTUFF
20%
C5553
1 2
48 CPUHYS
DFN1006H4-3
DMN32D2LFB4
U5552 3
1 2
BYPASS=U5551.5::5MM
10%
CERM-X5R
0201
6.3V
CPUHYS
1
2
MF
0
0201
1
2
294K
MF
201
1/20W
CPUHYS
1%
R55541
2
1/20W
MF
201
CPUHYS
84.5K
R55551
2
NOSTUFF
1/20W
5%
MF
0
R55571
SM-201
D5557 A
K
1/20W
20K
MF
201
R55401
2
PLACE_NEAR=U5520.10:5MM
MF
201
NOSTUFF
5%
20K
R55251
2
MF
1
2
71 
71 
1/20W MF1%
4.53K
201
1 2
0201
X5R-CERM
2.2UF
PLACE_NEAR=U5700.2:5MM
6.3V
20%
C5539 1
2
1%
201
MF
453K1 2
6.3V
X5R
20%
0.22UF
C55291
2
53 
1%
4.53K
1/20W
MF
201
1 2
0.22UF
20%
6.3V
0201
X5R
LOADRC:YES
C55191
2
48 
0201
6.3V
X5R
20%
1MF
201
1%
R5579
1 2
46 47 
46 
53 52 51 50 
53 52 50 
55 53 51 50 48 47 46 
55 53 51 50 48 47 
53 52 51 50 
55 53 51 50 48 47 46 
53 52 51 50 
55 53 51 50 48 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
V-
V+
IN
IN
IN
IN
DS
G
OUT
IN
IN
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
OUT
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
IN
IN
IN
IN
NC
NC
NC
NC
GND
V+
REFIN+
IN- OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
OUTIN-
IN+ REF
V+
IN
OUT
OUT
D
SG
SYM_VER_2
IN
IN
OUT
OUT
OUT
OUT
Thunderbolt TBT LEFT Current Sense (IULC)
Rsense: 0.025 (R5640) or Rsense SHORT
Vsense: 12.5 mV, Range: 0.5 A
Camera Current Sense (ICMC)
Rsense: 0.015 (R5610) or XW5610
Vsense: 12.3 mV, Range: 0.83 A
EADC2: CH0
Trackpad 3V Current Sense (IT3C)
Gain: 200x. EDP: 0.5 A
T151 Current Sense (IIDC)
200x 
Rsense: 0.05 (R5650) or Rsense SHORT
Vsense: 10 mV, Range: 0.25 A 
LCD Panel Current Sense (ILDC)
RSENSE: 0.01 (R8520) or Rsense SHORT
200x 
Vsense: 819 mV, Range: 0.25 A 
Thunderbolt TBT RIGHT Current Sense (IURC)
Rsense: 0.025 (R5680) or Rsense SHORT
Vsense: 12.5 mV, Range: 0.5 A
Rsense: 0.05 (R5630) or Rsense SHORT
Gain: 200x, EDP: 0.004 A
T139 5V Current Sense (IF5C) CPU High Side (IC0R) Peak Detection Support
In battery discharge scenario negative voltage will be
200x 
EADC2: CH4 
200x 
200x 
SENSE+ pins of EMC1704 sink 10-20uA current.
200x 
Gain: 200x. EDP: 1 A
EADC1: CH7
200x 
Vsense: 0.2 mV, Range: 0.25 A 
EADC1: CH6 
With 20uA sink: 0.125A - 2.1A -> 23mV - 92 mV
With 10uA sink: 0.125A - 2.1A -> 13mV - 83 mV
This deviation has been designed in our Peak Detection circuit.
present on IN+/- pins with INA output voltage decreasing
from 3.3V with increasing discharge current.
200x 
Vsense: 5 mV, Range: 1.25 A
EADC2: CH1 
Gain: 200x, EDP: 0.2 A
EADC2: CH2
Gain: 200x. EDP: 0.82 A
Gain: 200x. EDP: 0.5 A
EADC1: CH2
Gain: 200x, EDP: 0.1638 A
Rsense: 0.05 (R5690) or Rsense SHORT
52 OF 121
PP5V_S0110 
PP3V3_S0_LEFT110 
PP3V3_TBT_T_S0110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP5V_S0_T139110 
PP3V3_S0_LEFT110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP3V3_S4_SOC_PMU110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP3V3_S4SW_SNS52 50 110 55 53 51 
PP3V3_S0110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP3V3_S4_TPAD110 
PP3V3_TBT_X_S0110 
PP3V3_S0110 
PLACE_NEAR=U5670.2:3:10MM
PP3V3_S4110 
PP3V3_S4110 
PP3V3_S4_T151110 
PP3V3_S4110 
56 OF 145
10.0.0
051-00647
dvt-fab10
ISNS_TBT_X_N
PLACE_NEAR=U5640.4:5:10MM
OMIT
R5640
1%
R5690
0.005
0.005
0.005
0.005
R5630
PLACE_NEAR=U5710.2:5MM
20K
5%
1/20W
LOADISNS
PLACE_NEAR=U5710.24:5MM
EADC2_CAMERA_ISENSE 53 
PLACE_NEAR=U5700.5:5MM
TBTRC:YES
C5649
EADC1_TBT_X_ISENSE
LOADRC:YES
PLACE_NEAR=U5700.4:5MM
R5639
453K 2
C5639
GND_EADC1_COM
PLACE_NEAR=U5710.22:5MM
C5629
C5649,C5689
C5619,C5629,C5639,C5699
C5659
PLACE_NEAR=U5700.5:5MM
ISNS_T151_N
ISNS_T151_P
OMIT
TPADRC:YES
X5R
C5659
EADC2_PP3V3_TPAD_ISENSE
GND_EADC2_COM
PLACE_NEAR=U5710.24:5MM
0.22UF
LOADISNS
BYPASS=U5610.6::5MM
OMIT
10%
OMIT
R5650
1/3W
0306-SHORT
R5610
1/3W
2
1 3
40306-SHORT
PLACE_NEAR=U5610.4:5:10MM
PLACE_NEAR=U5610.2:3:10MM
1%
MF
ISNS_PP3V3_TPAD_N
PLACE_NEAR=U5650.2:3:10MM
C5650
BYPASS=U5650.6::5MM
PLACE_NEAR=U5710.23:5MM
TPADISNS
1 TPADRC:NO117S0008 RES,MTL FLIM,100K,1/16W,0201,SMD,LF
LOADISNS
1
5%
TPADISNS
CERM-X5R2
0.005
1%
1/3W
MF
0306-SHORT
ISNS_LCDPANEL_N
1%
2
1 3
4
MF
PLACE_NEAR=U5650.4:5:10MM
LOADISNS
C5610
PLACE_NEAR=U5710.22:5MM
R5629
453K
0201
GND_EADC2_COM
CRITICAL
Power Sensors: Extended
53 
51K
INA210A
TBTISNS
53 
LOADISNS
PLACE_NEAR=U5700.4:5MM
EADC1_PP5V_T139_ISENSEUQFN
PLACE_NEAR=U5630.2:3:10MM INA210A
ISNS_PP5V_T139_IOUT
1/20W
PLACE_NEAR=U5630.10:5MM
ISNS_LCDPANEL_IOUT
CERM-X5R
6.3V
ISNS_LCDPANEL_P
GND_EADC1_COM
EADC2_LCDPANEL_ISENSE
BYPASS=U5620.6::5MM
PLACE_NEAR=U5630.4:5:10MM
PLACE_NEAR=U5640.2:3:10MM
2
1R5661
1%
MF
1/20W
16K
201
2
1R5662
1%
1K
1/20W
201
MF
2
1 C5665
X5R
6.3V
20%
0201
0.22UF
NOSTUFF
21
R5665
0
MF
1/20W
0201
5%
21
R5660
5%
47
MF
1/20W
201
50 52 
50 52 
76 
2
1 C5619
0.22UF
20%
LOADRC:YES
6.3V
X5R
0201
21
R5619
453K
MF
1%
201
1/20W
76 53 
2
1
20%
6.3V
LOADRC:YES
0.22UF
X5R
2
R5645
5%
1/20W
MF
201
NOSTUFF
PLACE_NEAR=U5640.10:5MM
2
1
LOADISNS
5%
1/20W
MF
201
2
1R5615
PLACE_NEAR=U5610.10:5MM
5%
201
MF
20K
NOSTUFF
1/20W
2
1R5664
1/20W
15K
5%
MF
201
PLACE_NEAR=U5660.10:5MM
54 21
R5666
MF
0
5%
0201
NOSTUFF
1/20W
PLACE_NEAR=U5660.10:10MM
21
R5667
1/20W
MF
PLACE_NEAR=U5660.10:10MM
0201
5%
0
50 52 
54 21
R5668
1/20W
0
5%
MF
0201
PLACE_NEAR=U5660.10:10MM
NOSTUFF
21
R5669
1/20W
0201
5%
0
MF
PLACE_NEAR=U5660.10:10MM
50 52 
2
1R5635
5%
201
MF
1/20W
NOSTUFF
20K
2
1
X5R
0.22UF
0201
6.3V
20%
1
201
1%
MF
53 
1
6.3V
PLACE_NEAR=U5710.23:5MM
21
R5659
453K
MF
201
1%
1/20W
2
1R5655
201
1/20W
MF
NOSTUFF
20K
6
8
10
7
1
3
5
2
4
9
U5630
CRITICAL
LOADISNS
6
8
10
7
1
3
5
2
4
9
U5640
INA210A
CRITICAL
TBTISNS
UQFN
6
8
10
7
1
3
5
2
4
9
U5620
INA210A
UQFN
LOADISNS
CRITICAL
6
8
10
7
3
5
2
4
9
U5650
INA210A
UQFN
TPADISNS
6
8
10
7
1
3
5
2
4
9
U5610
INA210A
CRITICAL
LOADISNS
UQFN
6
8
10
7
1
3
5
2
4
9
U5660
INA210A
CKPLUS_WAIVE=NdifPr_badTerm
CRITICAL
UQFN
PLACE_NEAR=R5400.4:10MM
CKPLUS_WAIVE=NdifPr_badTerm
CKPLUS_WAIVE=NdifPr_badTerm
PLACE_NEAR=R5400.3:10MM
CKPLUS_WAIVE=NdifPr_badTerm
LOADISNS
2
1 C5630
0.1UF
6.3V
0201
10%
CERM-X5R
2
1
0201
2
1 C5620
0.1UF
0201
10%
1
0201
6.3V
10%
0.1UF
2
1
0.1UF
6.3V
0201
CERM-X5R2
1 C5660
0.1UF
10%
6.3V
CERM-X5R
0201
BYPASS=U5660.6::5MM
6
8
10
7
1
2
9
U5670
2 X5R
0201
6.3V
53 1
453K
201
1/20W
MF
1%
2
1 C5680
10%
6.3V
0.1UF
CERM-X5R
0201
2
1R5685
MF
1/20W
20K
201
5%
PLACE_NEAR=U5670.10:5MM
6
8
10
7
1
5
2
4
U5690
CRITICAL
UQFN 21
R5699
MF
453K
201
1%
1/20W
2
1
0.1UF
10%
CERM-X5R
6.3V
0201
53 
1 C5699
LOADRC:YES
X5R
6.3V
20%
0201
0.22UF
1R5695
1 453K
1/20W
201
MF
2
1
0.22UF
20%
6.3V
X5R
0201
21
201
1%
MF
1/20W
SYNC_DATE=04/14/2016SYNC_MASTER=X363_ZIFENGSHEN
BOM_COST_GROUP=SENSORS
ISNS_HS_COMPUTING_N
ISNS_CPUHIGAIN_NISNS_PP5V_T139_P
ISNS_CAMERA_IOUT
ISNS_CAMERA_N
ISNS_CAMERA_P
ISNS_CPUHIGAIN_OUT
ISNS_CPUHIGAIN_P
ISNS_CPUHIGAIN_R_N
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
ISNS_CPUHIGAIN_OUT_RISNS_HS_COMPUTING_P
ISNS_PP3V3_TPAD_P ISNS_PP3V3_TPAD_IOUT
GND_EADC2_COM
GND_EADC2_COM
EADC2_T151_ISENSE
ISNS_CPUHIGAIN_R_P
ISNS_TBT_X_P ISNS_TBT_X_IOUT
ISNS_TBT_T_IOUT
PLACE_NEAR=U5650.10:5MM
LOADRC:NO117S0008
117S0008
R5625
PLACE_NEAR=U5620.10:5MM
20%
2
0201
ISNS_T151_IOUT
PLACE_NEAR=U5690.10:5MM
BYPASS=U5670.6::5MM
INA210A
UQFN
CRITICAL3
MF
LOADISNS
4
31
2
EADC1_TBT_T_ISENSE
C5689
0.22UF
20%
1
2
R5689
PLACE_NEAR=U5700.24:5MM
TBTISNS
TBTISNS
PLACE_NEAR=U5670.4:5:10MM
ISNS_TBT_T_N
ISNS_TBT_T_P
NOSTUFF
PLACE_NEAR=U5700.24:5MM
TBTRC:YES
GND_EADC1_COM
TBTRC:NO
CERM-X5R
MF
1/3W
ISNS_PP5V_T139_N0306-SHORT 4
3
2
BYPASS=U5630.6::5MM
3
9
LOADISNS
RES,MTL FILM,100K,1/16W,0201,SMD,LF
RES,MTL FILM,100K,1/16W,0201,SMD,LF
4
5
0306-SHORT
1/3W
1
1%
1
20K4
31
2
OMIT
6.3V
10%
0.1UF
C5640
2
R5649
BYPASS=U5640.6::5MM
TBTISNS
TBTISNS
2
PLACE_NEAR=U5710.2:5MM
2MF
2
NOSTUFF
1%
0.005
R5680
OMIT
4
31
20306-SHORT
MF
1/3W
1%
201
BYPASS=U5690.6::5MM
C5690
LOADISNS
LOADISNS
4
50 53 
50 51 52 53 
50 51 52 53 
50 51 52 53 
50 51 52 53 
51 52 
50 51 52 53 
50 51 52 53 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
OUT
NC
NC
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
OUT
OUT
IN
OUT
IN
OUT
OUTIN
OUT
IN
IN
IN
Vsense: 10.5 mV, Range: 0.36 A 
(PRODUCTION)
CPU SA Voltage Sense (VCSC)
EADC2: CH3 
200x 
Rsense: 0.002 (R7570)
Vsense: 16 mV, Range: 7.5 A
Gain: 200x, EDP: 8 A
CPU SA Current Sense (ICSC)
KB backlite Current Sense (IKBC)
Rsense: 0.025 (R5720) or Rsense SHORT
LPDDR 1.8V Current Sense (IM1C)
SSDLIM Current Sense (IHDC)
Vsense: 13.05 mV, Range: 3.0 A 
Gain: 200x, EDP: 2.61 A
RSENSE: 0.005 (R5750)
100x 
SMC ADC: 23 (OPTIONAL) 
SMC ADC: 17 
200x 
200x 
Vsense: 13.875 mV, Range: 0.6 A 
Gain: 200x, EDP: 300m A
SMC ADC: 19
(Write: 0x14 Read: 0x15)
(Write: 0x10 Read: 0x11)
SMC ADC: 5 
EADC1
EADC2
Gain: 200x, EDP: 0.555 A
Vsense: 20.625 mV, Range:57.62 A 
Rsense: 2x of 0.00075 (R7410, R7420), Rsum: 0.000375
Gain: 202.93x, EDP: 55 A
CPU GT Current Sense (ICTC)
SMC ADC: 14
Rsense: 0.035 (R5730)
53 OF 121
PP5V_S4110 53 51 
VOLTAGE=5V
VOLTAGE=5V
PP3V3_S4SW_SNS52 50 55 53 51 110 
PP1V8_S3_MEM109 
PP1V8_S3109 
PP3V3_S4SW_SNS55 53 52 51 50 110 
PP5V_S4110 53 51 
SMBUS_SMC_2_S4_SCL 49 
SMBUS_SMC_2_S4_SDA 49 
PP5V_S4 110 53 51 
VOLTAGE=0V
SMBUS_SMC_2_S4_SCL49 
PP3V3_S0110 
VOLTAGE=0V
PPVCCSA_S0_CPU109 8 
SMBUS_SMC_2_S4_SDA49 
VOLTAGE=5V
VOLTAGE=5V
PP3V3_S4SW_SNS
110 55 
53 52 51 50 
PP5V_S0_KBD110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP5V_S0110 
57 OF 145
10.0.0
051-00647
dvt-fab10
LOADISNS
LOADISNS
BYPASS=U5770.3::5MM
PLACE_NEAR=U5000.H2:5MM
SMC_CPUSA_ISENSE
C5779
PLACE_NEAR=U5000.H2:5MM
ISNS_CPUSA_IOUT
OMIT
PLACE_NEAR=U5750.5:5:10MM
MAKE_BASE=TRUE
BYPASS=U5710.21::5MM
SM
XW5778
PLACE_NEAR=U5730.2:3:10MM
PLACE_NEAR=U5730.10:5MM
GND_EADC2_COM
PLACE_NEAR=U5730.4:5:10MM
ISNS_SSDNAND_N
C5714
4.7UF
1
C5739,C5749,C5779,C57894
NOSTUFF
R5775
CRITICAL
PLACE_NEAR=U5710.1:5MM
LOADISNS
BYPASS=U5730.6::5MM
OMIT
ISNS_KBBLT_IOUT
1ISNS_KBBLT_N
1/3W
0306-SHORT
1%
2
1 3
40306-SHORT
MF
SMC_CPUGT_IMON_ISENSE
R5735
U5770
C5729
C5701
68 
67 
67 
2
1
MF
5%
20K
1/20W
201
0.22UF
X5R
20%
0201
6.3V
21
R5779
1/20W
1%
4.53K
201
MF
48 
21
1/20WNO_XNET_CONNECTION=1
PLACE_NEAR=R7410.4:5MM
4.42K
0201
MF
0.1%
LOADISNS
21
R5746
PLACE_NEAR=R7420.4:5MM
NO_XNET_CONNECTION=1 1/20W
0.1%
4.42K
0201
MF
LOADISNS
21
R5748
PLACE_NEAR=R7410.3:5MM
1/20WNO_XNET_CONNECTION=1
4.42K
0201
0.1%
MFLOADISNS
21
R5757
PLACE_NEAR=R7420.3:5MM
NO_XNET_CONNECTION=1
MF
4.42K
0.1%
0201
1/20W
LOADISNS
2
1R5744
1/20W
0.1%
0201
715K
MF
LOADISNS
21
R5741
NO_XNET_CONNECTION=10201
1/20W
715K
0.1%
2 1
XW5710
PLACE_NEAR=U5710.25:1MM
PLACE_NEAR=U5710.6:1MM
SM2 1
XW5700
SM
PLACE_NEAR=U5700.25:1MM
PLACE_NEAR=U5700.6:1MM
21
R5700
BYPASS=U5700.12::5MM
LOADISNS
1/20W
MF
201
5%
10
21
R5710
10
5%
MF
201
LOADISNS
1/20W
BYPASS=U5710.12::=5MM
21
R5742
2.94K
1%
201
MF
1/20W
21
R5743
2.94K
201
MF
1/20W
1%
LOADISNS
6
8
10
7
3
5
2
4
9
2
1 C5730
0201
0.1UF
10%
CERM-X5R
2
1 C5770
0201
X7R
10%
0.1UF
6.3V
2
1 C5711
BYPASS=U5710.12::5MM
LOADISNS
CERM-X5R
10%
6.3V
0201
0.1UF
2
1 C5740
0201
BYPASS=U5740.5::5MM
X7R
10%
6.3V
0.1UF
21
1/20W
MF
1%
201
4.53K
2
1 C5789
PLACE_NEAR=U5000.C1:5MM
6.3V
20%
X5R
0.22UF
0201
48 
21
PLACE_NEAR=R7370.2:5 MM
21
R5778
PLACE_NEAR=U5000.H3:5MM
1/20W
1%
4.53K
MF
201
2
1 C5778
6.3V
0.22UF
20%
0201
X5R PLACE_NEAR=U5000.H3:5MM
48 
7
25
17
16
8
20191811109
21
6
5
4
3
2
1
24
23
22
1312
15
14
U5710
LOADISNS
LTC2309
CRITICAL
QFN
7
25
17
16
8
20191811109
21
6
5
4
3
2
1
24
23
22
1312
15
14
U5700
QFN
LOADISNS
CRITICAL
LTC2309
2
1
0201
X5R-CERM
10V
10%
0.1UF
BYPASS=U5700.12::5MM LOADISNS
2
1 C5703
X5R-CERM
BYPASS=U5700.21::5MM
LOADISNS
10V
0201
0.1UF
10%
2
1 C5706
10V
20%
10UF
0402-10
X5R-CERM
LOADISNS
BYPASS=U5700.8::5MM
2
1 C5704
0402
10V
X5R-CERM
LOADISNS
BYPASS=U5700.21::5MM
4.7UF
20%
2
1 C5700
6.3V
0201
X5R-CERM
2.2UF
20%
LOADISNS
BYPASS=U5700.7::5MM
2
1 C5705
6.3V
0.1UF
10%
CERM-X5R
0201
LOADISNS
BYPASS=U5700.8::5MM
2
1
201
1/20W
5%
MF
NOSTUFF
2
1 C5715
CERM-X5R
LOADISNS
BYPASS=U5710.10::5MM
0.1UF
10%
0201
6.3V 2
1 C5716
BYPASS=U5710.10::5MM
20%
10V
10UF
X5R-CERM
0402-10
LOADISNS
2
1 C5710
LOADISNS
2.2UF
6.3V
20%
0201
X5R-CERM
BYPASS=U5710.7::5MM
2
1 C5713
LOADISNS
BYPASS=U5710.21::5MM
0201
10%
10V
X5R-CERM 2
LOADISNS
10V
0402
21
R5712
1/20W
100K
BOMOPTION=NOSTUFF
MF
5%
201
3
1
6
4
5
2
SC70
CRITICAL
INA210
2
1R5755
PLACE_NEAR=U5750.6:5MM
1/20W
20K
5%
MF
201
NOSTUFF
2
1 C5739
0.22UF
20%
6.3V
0201
X5R
LOADRC:YES
PLACE_NEAR=U5710.1:5MM
2
1 C5750
BYPASS=U5750.3::5MM
6.3V
0201
0.1UF
10%
4
3
2
1R5720
PLACE_NEAR=U5720.4:5:10MM
PLACE_NEAR=U5720.2:3:10MM
0306
1/3W
0.025
MF
1%
CRITICAL
2
1 C5702
0402
4.7UF
BYPASS=U5700.12::5MM
10V
X5R-CERM
LOADISNS
20%
2
1 C5712
BYPASS=U5710.12::5MM
0402
10V
X5R-CERM
LOADISNS
4.7UF
20%
6
8
10
7
1
3
5
2
4
9
U5720
INA210A
CRITICAL
UQFN
LOADISNS
21
R5739
453K
1/20W
1%
MF
201
2
1R5725
20K
NOSTUFF
201
1/20W
5%
MF
2
1 C5720
BYPASS=U5730.6::5MM
0.1UF
6.3V
0201
10%
CERM-X5R
LOADISNS
1
R5729
453K1/20W
MF
201
NOSTUFF
NO_XNET_CONNECTION=1
2
1
NOSTUFF
0201
X5R
6.3V
48 55 
3
1
6
4
5
2
PLACE_NEAR=R7370.3:20.5MM
SC70
INA214
LOADISNS
68 
68 
68 
5
2
4
1
3
U5740
CRITICAL
SC70-5
ISL28133
LOADISNS
2
1R5740
5%
1/20W
201
MF
20K
NOSTUFF
2
1 C5749
PLACE_NEAR=U5000.C3:5MM
6.3V
X5R
20%
21
MF
1%
1/20W
201
48 
SYNC_DATE=04/14/2016SYNC_MASTER=X363_ZIFENGSHEN
BOM_COST_GROUP=SENSORS
Power Sensors: Extended 2
CPUSA_ISNS_P
CPUSA_ISNS_N
GND_SMC_AVSS
ISNS_KBBLT_P
CPUGT_ISNS1_P
ISNS_LPDDR_P
ISNS_LPDDR_N
EADC2_T151_ISENSE
EADC2_BT_ISENSE
EADC2_OTHER3V3_HI_ISENSE
PP5V_EADC2_AVDD
CPUGT_ISNS2_N
EADC2_KBBLT_ISENSE
PP3V3_SSD_ISNS_R
PP3V3_SSD_LIM
SMC_SSDLIM_ISENSE
GND_SMC_AVSS
ISNS_SSDNAND_IOUT
GND_SMC_AVSS
PP5V_EADC1_AVDD
EADC2_PP3V3_TPAD_ISENSE
EADC2_CAMERA_ISENSEEADC1_TBT_T_ISENSE
EADC1_OTHER5V_HI_ISENSE
EADC1_PP5V_T139_ISENSE PP2V5_ADC1_VREF
SMC_TPAD_ISENSE
EADC2_KBBLT_ISENSE
EADC2_LCDPANEL_ISENSE
GND_EADC2_COM ADC2_REFCOMP
EADC2_AD0
PP2V5_ADC2_VREF
CPUGT_ISNS2_P CPUGT_ISNS_R_P
GND_EADC1_COM
EADC1_LCDBKLT_ISENSE
EADC1_PP3V3S5_T139_ISENSE
EADC1_P1V8SUS_ISENSE
EADC1_TBT_X_ISENSE
EADC1_PP3V3S4_WLAN_ISENSE
CPUSAVSENSE_IN
CPUGT_ISNS1_N
CPUGT_ISUM_IOUT
CPUGT_ISNS_R_N
SMC_CPUSA_VSENSE
SMC_CPUGT_ISENSE
GND_SMC_AVSS
ADC1_REFCOMP
1%
0.22UF
20K
2
20%
0.1UF
20%
X5R-CERM
PLACE_NEAR=R7370.4:20.5MM
LOADRC:NO117S0008
CERM-X5R PLACE_NEAR=U5000.C1:5MM
R5789U5750
ISNS_SSDNAND_P
INA210A
CRITICAL
LOADISNS
LOADISNS
LOADISNS
LOADISNS
GND_SMC_AVSS
LOADRC:YES
RES,MTL FLIM,100K,1/16W,0201,SMD,LF
LOADRC:YESISNS_LPDDR_IOUT
MF
1%
1/3W
31
2 4
CPUGT_ISNS_N
NO_XNET_CONNECTION=1
CPUGT_ISNS_P
LOADISNS
R5745
0.22UF
0201
LOADRC:YES
LOADISNSMF
4.53K
R5749 PLACE_NEAR=U5000.C3:5MM
LOADISNS
PLACE_NEAR=U5740.4:5MM
1
2
PLACE_NEAR=U5770.6:5MM
LOADISNS
0.005
R5730
U5730
PLACE_NEAR=U5750.4:3:10MM
MAKE_BASE=TRUE
0.005
UQFN
6.3V
LOADISNS
R5750
53 
52 
46 47 48 50 51 53 55 
52 
51 
50 
50 51 53 
53 
84 
78 84 86 
46 47 48 50 51 53 55 
46 47 48 50 51 55 
46 47 48 50 51 53 
52 
52 52 
50 
52 
50 
53 
52 
50 51 52 53 
50 51 52 
50 
51 
51 
52 
51 
46 47 48 50 51 53 
55 
55 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
OUT
V-
V+
IN
IN
IN
GND
V+
REFIN+
IN- OUT
OUT
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
GND
OUTIN-
IN+ REF
V+
PAD
REFCOMP
VREF
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
SCL
SDA
AD1
AD0
AVDD DVDD
THRMGND
COM
PAD
REFCOMP
VREF
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
SCL
SDA
AD1
AD0
AVDD DVDD
THRMGND
COM
OUT
OUT
NC
NC
GND
IN+
V+
REF
NC
NC
IN+
IN-
IN-
OUT
OUTIN
IN
IN
U5800 I2C Address:TMP461 A1->Floating A0->GND 0X96/0X97
CPU Proximity, Memory Proximity, Fin Stack Left, Fin Stack Right
Placement Note:
of the board, 1" to the right of USB connector.
PLACE U5820 ON BOTTOM NEAR X100
Note: Use GND pin AC22 on U2800 for N leg.
I2C Write: 0x98, I2C Read: 0x99
READ ADDRESS: 0X93
WRITE ADDRESS: 0X92
I2C Write: 0x98, I2C Read: 0x99
Thermal Sensor C:
chip, the N leg connect to pin AC22.
Placement Note:
between channel A and B, on the BOTTOM side.
Place Q5872 between two rows of Memory devices,
Placement Note:
Thermal Diode: Memory Proximity (TM0P)
The P leg connects to THERMDA pin of the TBT
Placement Note:
Note: Use GND pin AC22 on UB000 for N leg.
U5850 I2C Address:TMP461 A1->GND A0->GND 0X90/0X91
Thunderbolt Die, Air Flow Right
Placement Note:
chip, the N leg connect to pin AC22.
The P leg connects to THERMDA pin of the TBT
Placement Note:
I2C Write: 0xD8, I2C Read: 0xD9
Thermal Sensor A:
Thunderbolt Die, Airflow Left
Thermal Diode: TBT Die (TTLD)
Thermal Diode: TBT Die (TTRD)
Thermal Diode: Airflow Left Proximity (TaLC)
Place U5850 on the TOP side, on the left portion
of the board, 1" to the right of USB connector.
Placement note:
Place U5800 on the TOP side, on the left portion
Thermal Diode: Airflow Right Proximity (TaRC)
Placement Note:
on the TOP side.
Place U5870 at corner near right Fan,
the X100, on the TOP side.
Place Q5871, Airflow thermal indicator, above
Thermal Diode: Fin Stack Right (Th1H)
on the BOTTOM side.
Placement Note:
Place Q5873 under the CPU,
I2C ADDRESS (U5870): 0XB8/0XB9
Thermal Diode: Fin Stack Left (Th2H)
Thermal Sensor B & CPU High Peak Detection:
Thermal Sensor: CPU Proximity (TC0P)
X100 PROXIMITY (TW0P)
54 OF 121
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
TBTTHMSNS_T_D1_N
SMBUS_SMC_3_SCL
TBTTHMSNS_X_D1_N
PP3V3_S0110 
PP3V3_S0110 
TBTTHMSNS_X_D1_P
SMBUS_SMC_3_SDA
PP3V3_S0_LEFT110 
SMBUS_SMC_3_SCL
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
PP3V3_S0_LEFT110 
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2500
TBTTHMSNS_T_D1_P
58 OF 145
10.0.0
051-00647
dvt-fab10
TBTTHRM_SNS
TMP461
U5800
TBTTHRM_SNS
TBTTHRM_SNS
TBTTHRM_SNS
R5800
PLACE_NEAR=U5800.3:5MM
TBTTHRM_THRM:PU
0.1UF
TBTTHMSNS_X_THM_L
AP_TEMP
PLACE_NEAR=U5850.3:5MM
PLACE_NEAR=U5800.2:5MM
C5801
0201
TBTTHRM_SNS
PP3V3_S0_TBTTHMSNS_X_R
SOT563
AP_TEMP
C5820
PP3V3_S0_CPUTHMSNS_R
CPUTHMSNS_ALERT_L
CPUTHMSNS_D2_N
ISNS_CPUHIGAIN_P
CPUTHMSNS_D3_N ISNS_CPUHIGAIN_N
CPUTHMSNS_D1_P
CPUTHMSNS_D1_N
CPUTHMSNS_D3_P
CPUTHMSNS_D2_P
CPUTHMSNS_THM_L
CPUTHMSNS_FILTER
X29THMSNS_A0
TBTTHMSNS_T_ALERT_L
TBTTHMSNS_T_THM_L
MAKE_BASE=TRUE
TBTTHMSNS_X_D1_P
MAKE_BASE=TRUE
TBTTHMSNS_T_D1_N
PP3V3_S0_TBTTHMSNS_T_R
TBTTHMSNS_X_D1_N
MAKE_BASE=TRUE
TBTTHMSNS_T_D1_P
MAKE_BASE=TRUE
TBTTHMSNS_X_ALERT_L
CPUTHMSNS_ADDR_SEL
Thermal Sensors
BOM_COST_GROUP=SENSORS
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
49 
49 
5%
1/20W
MF
201
47
R5850
1 2
201
MF
5%
47
1/20W
R5870
1 2
PLACE_NEAR=U5870.8:5MM
X7R-CERM
0201
2200PF
10%
10V
PLACE_NEAR=U5870.9:5MM
C5872 1
2
PLACE_NEAR=U5870.6:5MM
10V
X7R-CERM
10%
2200PF
0201
PLACE_NEAR=U5870.7:5MM
C5871 1
2
PLACE_NEAR=U5850.2:5MM
10%
X7R-CERM
0201
2200PF
10V
C5851 1
2
0201
X7R
6.3V
0.1UF
10%
BYPASS=U5870.1::5MM
C58701
2
CERM-X5R
0201
6.3V
0.1UF
10%
BYPASS=U5850.1::5MM
C58501
2
28 
27 
CRITICAL
TMP461
QFN
U5850
5
10
7
3
2
6
9
8
4
1
5%
201
MF
10K
1/20W
R58731
2
52 
52 
CRITICAL
TMP513AISAR
QFN
U5870
5
13
7
9
11
6
8
10
15
14
12
4
3
17
16
2
1
48 
1/20W
100K
1%
MF
201
R58711
2
1/20W
201
MF
1%
100K
R58721
2
201
1/20W
MF
1%
100K
TBTTHRM_ALRT:PU
R58521
2
100K
TBTTHRM_THRM:PU
1%
MF
1/20W
201
R58511
2
48 
48 
CRITICAL
DFN1006H4-3
BC846BLP
Q5873 1
3
2
DFN1006H4-3
BC846BLP
CRITICAL
Q5872 1
3
2
49 
49 
BC846BLP
DFN1006H4-3
CRITICAL
Q5871 1
3
2
HPA00330AI
CRITICAL
PLACE_NEAR=U3730::10MM
PLACE_SIDE=BOTTOM
U5820
4
3
2
1
6
5
48 
54 49 
54 49 
49 
49 
0201
CERM-X5R
0.47UF
6.3V
10%
C58741
2
2200PF
PLACE_NEAR=U5870.10:5MM
PLACE_NEAR=U5870.11:5MM
10%
X7R-CERM
10V
0201
C5873 1
2
BYPASS=U5850.1::5MM
10%
6.3V
0201
CERM-X5R
C58001
2
48 
100K
MF
1/20W
1%
201
R58011
2
100K
TBTTHRM_ALRT:PU
201
1/20W
1%
MF
R58021
2
48 
102 
101 
54 49 
54 49 
X7R-CERM
10V
2200PF
TBTTHRM_SNS
10%
1
2
47
1/20W
201
5%
MF
1 2
QFN
CRITICAL
5
10
7
3
2
6
9
8
4
1
5%
10K
1/20W
MF
201
AP_TEMP
R58201
2
6.3V
0.1UF
10%
0201
CERM-X5R
1
2
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVEDSHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
BI
BI
A1 THERM*
D-
D+
ALERT*/THERM2*
SDA
SCL
GND
V+
A0
IN
IN
PAD
SCL
FILTER C
GPIO
ALERT
SDA
A0
DXN2
GND
VIN-
VIN+
DXN3
DXP3
DXP2
DXN1
DXP1
V+
THRM
OUT
OUT
OUT
BI
BI
SDA
SCL ALERT
ADD0
V+
GND
NC
OUT
BI
BI
BI
BI
OUT
OUT
BI
BI
BI
BI
A1 THERM*
D-
D+
ALERT*/THERM2*
SDA
SCL
GND
V+
A0
NC
SENSORS: EXTENDER 3
CPU Core Voltage Sense (VCAC) CPU Core IMON Current Sense (ICAM)
GPU VDDCI Voltage Sense (VG2C)
Gain: 100x, EDP: 10.7 A
100x 
Vsense: 7.5 mV, Range: 3 A 
SMC ADC: 23
SMC ADC: 13 
SMC ADC: 20 
SMC ADC: 21 
SMC ADC: 7 
SMC ADC: 10 
Rsense: 0.003 (RA368)
Rsense: 0.005 (R5950)
SMC ADC: 12 
Rsense: 0.002 (RA300)
Vsense: 16 mV, Range: 15 A
Gain: 100x, EDP: 9.7 A
Gain: 200x, EDP: 2.3 A
200x 
Gain: 200x, EDP: 4 A
SMC ADC: 8 
SMC ADC: 11 
R7410 (Rsen) set to 0.75 mOhm,
200x 
Vsense: 8 mV, Range: 7.5 A 
100x 
With R7154 (Ri) set to 365 Ohm,
With R7150 (Ri) set to 432 Ohm,
R7160 set to 100 kOhm,
Gain: 122.01x, EDP: 64.2 A
GPU CORE Voltage Sense (VG0C)
SMC ADC: 22 
CPU GT IMON Current Sense (ICTM)
Num Phases (N) is 3, and Io (ICCmax) is 67A,
R7194 set to 100 kOhm,
R7210 (Rsen) set to 0.75 mOhm,
then 1A of Io gives 17.123mV at the Vimon. 
Gain: 1 A / 21.701 mV, Range: 64 A.
then 1A of Io gives 21.701mV at the Vimon. 
Gain: 1 A / 17.123 mV, Range: 67 A.
CPU GT Voltage Sense (VCTC)
200x 
SMC ADC: 15 
Vsense: 22.875 mV, Range: 65.57 A 
Rsense: 2x of 0.00075 (RA651, RA641), Rsum: 0.000375
GPU FB Current Sense (IG1C)
Num Phases (N) is 2, and Io (ICCmax) is 55A,
GPU FB IC Current Sense (IG4C)
Gain: 200x, EDP: 4.8 A
Rsense: 0.005 (R5970)
Vsense: 10 mV, Range: 3 A 
Vsense: 24 mV, Range: 10 A
GPU 1V8 Current Sense (IG3C)
(PRODUCTION)
(PRODUCTION)
(PRODUCTION)
GPU SENSORS
(PRODUCTION)
(PRODUCTION)
GPU CORE Current Sense (IG0C)
SMC ADC: 16 
Rsense: 0.002 (R5990) or Rsense SHORT
GPU HIGH SIDE Current Sense (IG0R)
GPU VDDCI Current Sense (IG2C)
10.0.0
59 OF 145
051-00647
dvt-fab10
55 OF 121
PP1V5R1V35_S0_GPU_MEM110 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP1V8_GPU110 
PPBUS_G3H109 
PPVCCGT_S0_CPU
109 8 
PPVCORE_S0_GPU
110 92 90 
PPVDDCI_S0_GPU
110 
92 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PP3V3_S4SW_SNS
110 
55 53 52 51 50 
PP3V3_S4SW_SNS110 55 53 52 51 50 
PPVCC_S0_CPU
109 8 6 
PP3V3_S4SW_SNS
55 
50 
110 
53 52 51 
PP1V8_S0_GPU116 110 
PP1V5R1V35_S0_GPU_IC110 
PP3V3_S4SW_SNS52 110 55 53 51 50 
PPBUS_HS_GPU109 
4.42K 2
R5920
RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5921,C5941,C5951,C5961,C59715
LOADISNS
20K
R5991
ISNS_GPU_HS_IOUT
C5990
BYPASS=U5990.3::5MM
0.005
48 
PLACE_NEAR=U5000.A2:5MM
LOADISNS
R5931
4.53K
C5920
BYPASS=U5920.5::5MM
U5920
LOADISNSCRITICAL
ISL28133
4
LOADISNS
1/20W
NO_XNET_CONNECTION=1
GFXIMVP_ISNS_N23.65K
R5927
201
1/20W
1
R5921
1/20W
0.1%
MF
LOADISNS
GFXIMVP_ISNS2_P
GFXIMVP_ISNS1_P
LOADISNS
0201
LOADISNS
GFXIMVP_ISNS_P
715K
0201
0201
1/20W
4.53K
R5910
PLACE_NEAR=U5000.C4:5MM
0201
SMC_CPUGT_VSENSE
21
R5900
1/20W
MF
1%
201
4.53K
21
R5992
PLACE_NEAR=U5000.H4:5MM
4.53K
201
1%
MF
1/20W
2
1 C5992
0.22UF
PLACE_NEAR=U5000.H4:5MM
20%
X5R
0201
6.3V
48 
3
1
6
4
5
2
U5970
4
3
2
1R5990
CRITICAL
0.002
1W
0612
1%
CYN
2
1 C5900
PLACE_NEAR=U5000.C4:5MM
X5R
6.3V
0.22UF
20%
48 21
R5982
201
1%
MF
1/20W
4.53K
2
1 C5983
0.22UF
6.3V
20%
0201
X5R
21
XW5982
SM
48 
21
R5911
PLACE_NEAR=U5000.A5:5MM
MF
0
5%
1/20W
0201
LOADISNS
2
1 C5911
PLACE_NEAR=U5000.A5:5MM
0.22UF
0201
6.3V NOSTUFFX5R
20%
2
1 C5901
NOSTUFFX5R
20%
0201
6.3V
0.22UF
PLACE_NEAR=U5000.B5:5MM
21
R5901
0
5%
0201
MF
1/20W
PLACE_NEAR=U5000.B5:5MM
LOADISNS
48 53 
48 51 
48 21
R5980
MF
1%
1/20W
4.53K
201
PLACE_NEAR=U5000.A3:5MM
2
1 C5981
PLACE_NEAR=U5000.A3:5MM
X5R
6.3V
20%
0.22UF
0201
21
XW5980
PLACE_NEAR=RA651.2:5 MM
SM
97 
97 
97 
97 
21
XW5910
PLACE_NEAR=R7410.2:5 MM
SM
21
R5924
4.42K
0.1%
1/20W
LOADISNS MF
0201
21
R5923
LOADISNS
1/20W
MF
4.42K
0.1%
0201
21
0201
1/20W
0.1%
4.42K
MF
1
1
1%
1/20W
MF
201
LOADISNS
2
R5926
1%
3.65K
MF
2
1R5928
MF
1/20W
0.1%
21
R5929
NO_XNET_CONNECTION=1
0.1%
MF
715K
21
PLACE_NEAR=U5000.C5:5.2MM
1%
MF
201
2
1R5930
PLACE_NEAR=U5920.4:5MM
5%
1/20W
201
MF
NOSTUFF
20K
5
2
1
3
SC70-5
2
1
CERM-X5R
0201
10%
6.3V
21
1%
1/20W
201
MF
2
1 C5921
0.22UF
6.3V
X5R
0201
LOADRC:YES
20%
94 
94 
2
0201
CERM-X5R
6.3V
10%
0.1UF
2
1R5960
MF
201
2
1R5971
NOSTUFF
1/20W
MF
5%
20K
201
21
R5972
201
1%
MF
4.53K
2
1
X5R
0201
6.3V
20%
PLACE_NEAR=U5000.A1:5MM
2
1 C5961
X5R
6.3V
20%
0.22UF
21
R5961
PLACE_NEAR=U5000.D3:5MM
1%
1/20W
4.53K
MF
201
3
1
6
4
5
2
U5960
INA214
CRITICAL
SC70
2
1 C5960
BYPASS=U5960.3::5MM
0201
X7R
0.1UF
6.3V
10%
48
 
2
1 C5910
PLACE_NEAR=U5000.C5:5MM
0201
20%
6.3V
X5R
0.22UF
48 
2
1 C5941
0.22UF
X5R
6.3V
20%
21
R5941
PLACE_NEAR=U5000.A4:5MM
201
1/20W
MF
4.53K
1%
2
1 C5950
0.1UF
10%
6.3V
CERM-X5R
0201
2
1 C5940
0201
BYPASS=U5940.3::5MM
X7R
10%
0.1UF
6.3V
1R5940
1/20W
20K
5%
MF
48 
3
1
6
4
5
2
U5940
INA214
SC70
CRITICAL
21
R5952
1/20W
1%
MF
201
4.53K
2
1
X5R
0201
20%
2
1R5951
PLACE_NEAR=U5950.6:5MM
MF
NOSTUFF
20K
1/20W
201
5%
3
1
6
4
2
U5950
LOADISNS
SC70
INA210
94 
21
XW5900
SM
PLACE_NEAR=R7210.2:5 MM
94 
3
1
6
4
5
2
U5990
CRITICAL
SC70
INA210
2
1
0201
10%
0.1UF
2
1
MF
201
5%
1/20W
PLACE_NEAR=U5990.6:5MM
SYNC_DATE=05/19/2016SYNC_MASTER=X363_ZIFENGSHEN
Sensor Extended 3
GFXIMVP_ISUM_IOUT
GPUVDDCIVSENSE_IN
SMC_GPU_FB_ISENSE
ISNS_GPUVDDCI_IOUT
SMC_GPU_HS_ISENSE
ISNS_GPUFBIC_P
ISNS_GPUFBIC_N
ISNS_GPU1V8_P
ISNS_GPU1V8_N
ISNS_GPU_HS_P
GND_SMC_AVSS
ISNS_GPU1V8_IOUT
ISNS_GPUFBIC_IOUT
GFXIMVP_ISNS2_N
GND_SMC_AVSS
GND_SMC_AVSS
GFXIMVP_ISNS_R_P
CPUGTVSENSE_IN
SMC_GPU_FBIC_ISENSE
GND_SMC_AVSS
IMON_B_CPUGT SMC_CPUGT_IMON_ISENSE
SMC_CPU_VSENSE
GPUCOREVSENSE_IN SMC_GPU_CORE_VSENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_GPU_VDDCI_VSENSE
GFXIMVP_ISNS1_N
VDDCIS0_CS_N
GND_SMC_AVSS
ISNS_GPUFB_IOUT
GFXIMVP_ISNS_R_N
GND_SMC_AVSSGND_SMC_AVSS
SMC_CPU_IMON_ISENSEIMON_A_CPUCORECPUVSENSE_IN
SMC_GPU_VDDCI_ISENSE
1/20W
GND_SMC_AVSS
MF
1%
SMC_GPU_CORE_ISENSE
PLACE_NEAR=U5000.A1:5MM
CERM-X5R
SC70
PLACE_NEAR=U5970.5:5:10MM
ISNS_GPU_HS_N
LOADISNS
LOADRC:NO117S0008
1/3W
BOM_COST_GROUP=SENSORS
PLACE_NEAR=U5970.4:3:10MM
R5970
GPUFB_CS_P
4
31
2
0.1UF
GPUFB_CS_N
PLACE_NEAR=U5000.D3:5MM
0201
LOADISNS
C59701
INA210
CRITICAL
LOADISNS
LOADISNS
LOADISNS
C5971
0.22UF
LOADISNS
LOADRC:YES
BYPASS=U5970.3::5MM
PLACE_NEAR=U5970.6:5MM
6.3V
LOADRC:YES
LOADISNS
PLACE_NEAR=U5000.A2:5MM
GND_SMC_AVSS
1/20W
20K
5%
NOSTUFF
PLACE_NEAR=U5960.6:5MM
0201
PLACE_NEAR=U5000.A4:5MM
6.3V
SMC_GPU_1V8_ISENSE
PLACE_NEAR=U5000.D4:5MM
LOADISNS
CRITICAL
5
1/3W
MF
1%
0.005
R5950
0306-SHORT 4
31
2
0306-SHORT
OMIT
OMIT
PLACE_NEAR=U5950.4:3:10MM
PLACE_NEAR=U5950.5:5:10MM
VDDCIS0_CS_P
2 201
NOSTUFFPLACE_NEAR=U5940.6:5MM
BYPASS=U5950.3::5MM
LOADISNS
LOADISNS
LOADISNS
GND_SMC_AVSS
C5951
0.22UF
PLACE_NEAR=U5000.D4:5MM
LOADISNS
LOADRC:YES
LOADRC:YES
55 53 51 50 48 47 46 
46 47 48 50 51 53 55 
48 
46 47 48 50 51 53 55 
46 47 
48 50 51 53 55 
46 47 48 50 51 53 55 
48 
46 47 48 50 51 53 55 
65 
46 47 48 50 51 53 55 
46 47 48 50 51 53 55 
46 47 48 50 51 53 55 
46 47 48 50 51 53 55 
46 47 48 50 51 53 55 46 47 48 50 51 53 55 
65 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTYOF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
GND
OUTIN-
IN+ REF
V+
IN
IN
GND
OUTIN-
IN+ REF
V+
GND
V+
REFIN+
IN- OUT
OUT
OUT
OUT
GND
V+
REFIN+
IN- OUTIN
IN
OUT
V-
V+
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
GND
OUTIN-
IN+ REF
V+
OUT
KEEP THE 5 PIN CONNECTOR FROM D1FAN CONNECTOR
5V DC
GND
518S0769
GND
5V DC
518S0769
56 OF 121
PP5V_S0 43 56 110 117 
PP3V3_S0 56 110 
PP5V_S0 43 56 110 117 
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
PP3V3_S0_LEFT56 110 
PP3V3_S0 56 110 
VOLTAGE=3.3V
PP3V3_S0_LEFT56 110 
60 OF 145
10.0.0
051-00647
dvt-fab10
FAN_LT_TACH
SMC_FAN_1_TACH
SMC_FAN_1_CTL
FAN_RT_TACH
SMC_FAN_0_TACH
FAN_RT_PWM
TP_CARBON_INT1
TP_CARBON_INT2
FAN_LT_PWM
SMC_FAN_0_CTL
CARBON_CAP
CARBON_SDA_R
CARBON_SCL_R
CARBON_DEN
CARBON_SA0
PP3V3_S0_CARBON_R
Fans
BOM_COST_GROUP=FAN
SYNC_MASTER=X363_ZIFENGSHEN SYNC_DATE=04/14/2016
0201
1/20W
MF
5%
0
CARBON_ISOL
R6013
1 2
CARBON
0201
1/20W
MF
5%
0
R6012
1 2
MF5%1/20W 0201
0
CARBON_ISOLR6021
1 2
MF
0
02011/20W5%
CARBON_ISOLR6020
1 2
49 
49 
1/20W
100K
201
MF5%
CARBON
R6011
12
TP-P5
TP6002
1
TP-P5
TP6001
1
1/20W5%
CARBON
CARBON_CS
100K
MF
201
R6010
12
CERM-X5R
20%
6.3V
0402-1
10UF
CARBON
C6002 1
2
CARBON
0.01UF
10%
25V
X5R-CERM
0201
C60011
2
16V
X5R-CERM
10%
CARBON
0201
0.1UF
C60001
2
CARBON
AP6DS2AB
LGA
U6000
14
5
8
12 13
7
6
9
10
11
15
2
3
4
16 1
FF14A-5C-R11DL-B-3H
CRITICAL
F-RT-SM
BOMOPTION=DBG_FAN
J6001
7
6
1
2
3
4
5
F-RT-SM
FF14A-5C-R11DL-B-3H
CRITICAL
BOMOPTION=DBG_FAN
J6000
7
6
1
2
3
4
5
46 
46 
100K
MF
201
5%
1/20W
R6051 1
2
DMN32D2LFB4
DFN1006H4-3
Q6050
3
1
2
47K
201
5%
1/20W
MF
R6055
1 2
201
MF
5%
1/20W
47K
R6050 1
2
46 
46 
DMN32D2LFB4
DFN1006H4-3
Q6000
3
1
2
1/20W
5%
201
MF
100K
R6001 1
2
47K
MF
201
5%
1/20W
R6000 1
2
201
1/20W
47K
MF
5%
R6005
1 2
115 114 43 115 114 43 
115 114 43 115 114 43 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
BI
A
A
GND
RES
RES
VDD_IOVDD
SDA/SDI/SDO
SCL/SPC
SDO/SA0
DEN
CAP
CS
INT1
INT2
RES
RES
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
OUT
G
S
SYM_VER_3
D
IN
OUT
G
S
SYM_VER_3
D
NOTE: If HOLD* is asserted
in normal and Dual-IO modes.
(SPI_IO<1>)
SPI ROM
IO0
IO1
IO3
ROM will ignore SPI cycles
(SWDIO)
(SWCLK)
SPI+SWD SAM Connector
(SPI_IO<0>)CPU Master SPI ROM Slave
Quad-IO Mode (Mode 0 & 3) supported.
in Status Register-2 to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE)
SPI Frequency: 50MHz for CPU, 20MHz for SMC.
IO2
Sam Card ROM Slave
SPI Bus Series Termination (Modified per PDG)
57 OF 121
PP3V3_G3H109 
PP3V3_SUS110 
61 OF 145
10.0.0
051-00647
dvt-fab10
SPI_MISO_RSPI_MISO
SPI_IO2_R
SPI_IO<3>
SMC_TCK
SPI_ALT_IO2_WP_L
SMC_RESET_L
SPI_ALT_CS_L
SPI_ALT_IO0_MOSI
SPI_ALT_IO1_MISO
SPI_MLB_CS_L
SPIROM_USE_MLB
SPI_MLB_IO0_MOSI SPI_ALT_CLK
SMC_TMS
SPIROM_USE_MLB
SPI_IO<2>
SPI_MLB_IO3_HOLD_L
SPI_MLB_IO2_WP_L
SPI_MLB_IO1_MISO
SPI_ALT_IO0_MOSI
SPI_MOSI
SPI_ALT_CS_L
SPI_ALT_CLK
SPI_MLB_CS_L
SPI_CLK_R
SPI_MOSI_R
SPI_IO3_R
SPI_MLB_IO0_MOSI
SPI_ALT_IO3_HOLD_L
SPI_MLB_IO3_HOLD_L
SPI_MLB_IO2_WP_L
SPI_MLBROM_CS_L
SPI_CLK
SPI_CS0_R_L
SPI_MLB_CLK
SPI_MLB_IO1_MISO
SPI_ALT_IO2_WP_L
SPI_MLB_CLK
SPI_CS0_L
SPI_ALT_IO1_MISO
SPI_ALT_IO3_HOLD_L
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
SPI Debug Connector
BOM_COST_GROUP=CPU & CHIPSET
PLACE_NEAR=U6100.6:12MM
5%
MF
22
1/20W
201
R6121
1 2
PLACE_NEAR=U6100.1:12MM
22
201
MF
5%
1/20W
R6120
1 2
13 
5%
MF
22
1/20W
PLACE_NEAR=U6100.2:12MM
201
R6123
1 2
13 
5%
PLACE_NEAR=U1100.AJ26:50MM
MF
1/20W
201
22
R6111
1 2
13 
PLACE_NEAR=U1100.AJ24:50MM
MF
201
22
5%
1/20W
R6110
1 2
10V
X5R-CERM
1.0UF
20%
BYPASS=U6100::3mm
0201-1
C61021
2
5%
0
1/20W
0201
SAMCONN
MF
PLACE_NEAR=J6100.5:6MM
R61251
2
0
SAMCONN
1/20W
5%
0201
MF
PLACE_NEAR=J6100.3:7MM
R61261
2
PLACE_NEAR=J6100.4:5MM
0201
MF
1/20W
SAMCONN
0
5%
R61271
2
SAMCONN
0201
5%
1/20W
0
MF
PLACE_NEAR=J6100.6:7MM
R61281
2
0
5%
0201
1/20W
MF
SAMCONN
PLACE_NEAR=J6100.8:8MM
R61321
2
1/20W
MF
0
0201
5%
SAMCONN
PLACE_NEAR=J6100.10:7MM
R61331
2
22
MF
5%
1/20W
201
PLACE_NEAR=U1100.AK24:50MM
R6119
1 2
201
MF
1/20W
22
5%
PLACE_NEAR=U1100.AM24:50MM
R6118
1 2
WSON
OMIT_TABLE
W25Q64FVZPIG
64MBIT
CRITICAL
U6100
6
1
5
2
4
7
9
8
3
SOT833
74LVC1G99
PLACE_NEAR=U6100.1:12MMCRITICAL
U6101
2
3
5
6
4
1
8
7
10%
0201
0.1UF
X5R-CERM
BYPASS=U6101::3mm
16V
C61011
2 0.1UF
X5R-CERM
16V
10%
0201
BYPASS=U6100::3mm
C6100 1
2
114 76 64 48 29 
CRITICAL
DF40PC-12DP-0.4V-51
M-ST-SM
SAMCONN
J6100
12
34
56
78
910
1112
1314
1516
114 47 46 
114 57 15 
114 47 46 
13 
18 13 
1/20W
MF
201
5%
PLACE_NEAR=U6100.7:12MM
22
R6131
1 2
22
201
MF
1/20W
5%
PLACE_NEAR=U6100.3:12MM
R6130
1 2
201
MF
1/20W
22
5%
PLACE_NEAR=U1100.AH25:50MM
R6113
1 2
18 13 
1/20W
MF
22
5%
201
PLACE_NEAR=U1100.AM23:50MM
R6112
1 2
1/20W
PLACE_NEAR=U6100.5:12MM
MF
22
5%
201
R6122
1 2
114 57 
114 57 
114 57 
114 57 
57 
114 57 15 
57 114 57 
57 
57 
57 
114 57 
114 57 
114 57 
57 
57 
114 57 
57 
57 
57 
57 
114 57 
57 
114 57 
114 57 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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PAGE TITLE
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A
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PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
BI
IN
IN
GND
VCC
DO(IO1)
HOLD*(IO3)
WP*(IO2)
CLK
THRM_PAD
DI(IO0)
CS*
GND
C
OE*
YA
B
D
VCC
OUT OUT
BI
BI
BI
BI
BI
ESD
PCH AUDIO
3-MIC CONNECTOR
LEFT SPEAKER AMPS
RIGHT SPEAKER AMPS
ESD
AUDIO JACK CODEC
APN: 518S0818
58 OF 121
PP1V8_S0 58 60 61 109 
PP1V8_S0 58 60 61 109 
PP1V8_S0 58 60 61 109 
PP1V8_S058 60 61 109 
62 OF 145
10.0.0
051-00647
dvt-fab10
SPKR_ID0
8409_ASP1_SDOUT_R
8409_ASP2_SCLK_R
8409_ASP1_SCLK_R
8409_ASP2_SDOUT_R
8409_ASP2_SCLK
8409_ASP1_SDOUT
HDA_BIT_CLK
AUD_I2C_1B_SDA
AUD_I2C_1B_SCL
AUD_I2C_1A_SCL
AUD_I2C_1A_SDA
AUD_ASP1B_SDOUT
AUD_ASP1B_LRCLK
HDA_SDIN0
AUD_ASP1A_LRCLK
AUD_ASP1A_SDOUT
AUD_ASP2_SDOUT
AUD_ASP1A_SCLK
AUD_ASP2_LRCLK
AUD_ASP1B_SCLK
AUD_ASP2_SCLK
8409_HDA_SDIN0_R
DMIC2_DATA
DMIC2_CLK
DMIC1_DATA
DMIC1_CLK
8409_ASP1_SCLK
8409_ASP1_LRCLK
8409_ASP2_LRCLK_R
8409_VA_PLL
8409_DMIC1_CLK_R
8409_DMIC2_DATA
AUD_SPKRAMP_INT_L
8409_DMIC1_DATA
HDA_RST_L
HDA_SDOUT
HDA_SYNC
8409_ASP2_LRCLK
8409_ASP2_SDOUT
8409_DMIC2_CLK_R
AUD_ASP2_SDIN
8409_ASP1_LRCLK_R
8409_I2C_SDA
8409_I2C_SCL
AUD_CODEC_INT_L
AUD_CODEC_RESET_L
AUD_SPKRAMP_RESET_L
HDA Bridge
BOM_COST_GROUP=AUDIO
SYNC_MASTER=X363_AUDIO SYNC_DATE=01/11/2016
201
MF
1/20W
47K
5%
R62241
2
114 61 
61 59 
61 59 
201
MF
33
5%
PLACE_NEAR=U6200:5MM
1/20W
R6231
1 2
5%
MF
201
1/20W
33
PLACE_NEAR=U6200:5MMR6230
1 2
33
5%
1/20W
MF
201
PLACE_NEAR=U6200:5MMR6229
1 2
PLACE_NEAR=U6200:5MM
MF
33
201
5%
1/20W
R6228
1 2
61 60 
61 60 
47K
5%
1/20W
MF
201
R62911
2
PLACE_NEAR=U6200:5MM
1/20W
5%
0
MF
201
R6285
1 2
1/20W
5%
0
MF
201
PLACE_NEAR=U6200:5MMR6284
1 2
0
PLACE_NEAR=U6200:5MM
5%
MF
1/20W
201
R6283
1 2
1/20W
0
MF
5%
201
PLACE_NEAR=U6200:5MMR6282
1 2
MF
5%
0
201
1/20W
PLACE_NEAR=U6200:5MMR6281
1 2
MF
1/20W
0201
5%
PLACE_NEAR=U6200:5MMR6280
1 2
NOSTUFF
47PF
5%
25V
C0G
0201
C62871
2
47PF
C0G
5%
25V
0201
NOSTUFF
C62861
2
47PF
5%
25V
C0G
0201
C62851
2
NOSTUFF
25V
C0G
5%
0201
47PF
C62831
2
47PF
NOSTUFF
25V
C0G
5%
0201
C62821
2
5%
C0G
25V
27PF
0201
C62811
2
33
MF
201
5%
1/20W
PLACE_NEAR=U6200:5MMR6203
1 2
33
PLACE_NEAR=U6200:10MM
MF
5%
1/20W
201
R6220
1 2 61 
47K
5%
1/20W
MF
201
R62901
2
100PF
NO_STUFF
0201
C0G
5%
25V
C62891
2
NO_STUFF
5%
100PF
C0G
25V
0201
C62881
2
59 
59 
5%
201
1.5K
MF
1/20W
R62271
2
1.5K
1/20W
201
MF
5%
R62261
2
59 
60 
60 
60 
61 
61 
59 
59 
59 
13 
13 
13 
13 
13 
60 
60 
FF14A-6C-R11DL-B-3H
F-RT-SM
J6200
1
2
3
4
5
6
7
8
1/20W
MF
201
5%
33
PLACE_NEAR=U6200:5MMR6206
1 2
33
201
MF
1/20W
5%
PLACE_NEAR=U6200:5MMR6208
1 2 201
0
MF
5%
1/20W
PLACE_NEAR=U6200:5MMR6207
1 2
201
5%
1/20W
MF
0
PLACE_NEAR=U6200:5MMR6205
1 2
U6200.B2:A1:5 MM
CERM
402
10%
10V
0.22UF
C62031
2 25V
0201
X5R
10%
0.1UF
U6200.E2:C3:5 MM
C62041
2
0201
X5R
10%
25V
0.1UF
BYPASS=U6200.C4:C3:5 MM
C62011
2
PLACE_NEAR=U6200:10MM
33
5%
1/20W
MF
201
R6225
1 2
1/20W
5%
MF
201
33
PLACE_NEAR=U6200:10MMR6223
1 2
PLACE_NEAR=U6200:10MM
5%
201
MF
1/20W
33
R6219
1 2
MF
5%
33
201
PLACE_NEAR=U6200:10MM
1/20W
R6221
1 2
10%
1UF
U6200.A6:A5:5 MM
X5R
16V
603
C62001
2
33
1/20W
PLACE_NEAR=U6200:10MM
5%
201
MF
R6222
1 2
33
PLACE_NEAR=U6200:10MM
5%
MF
201
1/20W
R6213
1 2
PLACE_NEAR=U6200:10MM
33
5%
MF
201
1/20W
R6210
1 2
PLACE_NEAR=U6200:10MM
1/20W
MF
5%
33
201
R6211
1 2
WLCSP
CS8409
U6200
D6
B6
C5
B5
C6
E4
F3
F2
E3
F4
B1
E1
D2
D1
C2
A5 A1C3
E5
D5
F5
F6
F1
A4
D4
D3
B4
A3
C1
A2
E6
B3
A6E2 B2 C4
114 
114 
114 
114 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
C
A
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
NC
NC
OUT
BI
IN
OUT
NC
NC
OUT
NC
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
OUT
BI
OUT
NC
NC
NC
VL
_S
P
VL
_H
D
VA
_P
LL
VL
_D
M
ASP1_LRCK/FSYNC
GPIO2/CS2*
GPIO1/CS1*
GPIO0/MISO1
ASP2_LRCK/FSYNC
GPIO3/MISO2
ASP2_SDIN
ASP2_MCLK
ASP2_SCLK
ASP2_SDOUT
ASP1_SCLK
ASP1_MCLK
ASP1_SDIN
ASP1_SDOUT
SPI_SCLK
MOSI
GPIO6/SCL
GPIO7/SDA
GPIO4
GPIO5
G
ND
D
G
ND
_P
LL
G
ND
L
SYNC
BCLK
SDO
SDI
RST*
DMIC2_DATA
DMIC2_CLK
DMIC1_DATA
DMIC1_CLK
(SEE RADAR # 6210118)
R/C6550 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
0x4B
0x4A
1.8V
1.8V
1.8V
GND
0x48 <--
0x49
ADDRESS
1.8V
AD0
GND GND
GND
AD1
AUDIO JACK CODEC I2C ADDRESS
APN:338S00142
<RDAR://PROBLEM/22033298>
59 OF 121
PP3V3_S0110 59 
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.0850
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
PP3V3_S0 59 110 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
PP3V3_S0110 59 
VOLTAGE=1.8V
63 OF 145
10.0.0
051-00647
dvt-fab10
BYPASS=U6360.A2:B2:3 MM
PP1V8_S0_LDO_AUD
C6361
1.0UF
CRITICAL
0201-1
X5R-CERM
20%
10V
1
2
58 
58 
58 
58 
58 
58 
SYNC_DATE=01/25/2016
PLACE_NEAR=U6300:10MM
AUDIO JACK CODEC
AUD_CODEC_RESET_L
AUD_ASP2_SCLK
AUD_CODEC_INT_L
AUD_ASP2_SDIN
AUD_ASP2_SDOUT
AUD_ASP2_LRCLK
GND_AUDIO_CODEC
U6360
1
2 5
XDFN-COMBO
NCP160AMX180
4
3
2
XW6300
SHORT-8L-0.25MM-SM
R6360
100K
1/20W
NOSTUFF1
5%
MF
1
2012
PP3V3_S0_AUD_F
L83_LDO_EN2
2
C6360
CRITICAL
1.0UF
0201-1
10V
20%
X5R-CERM2
1BYPASS=U6360.A1:B2:3 MM
L6360
FERR-22-OHM-1A-0.055OHM
L6361
FERR-470-OHM
0201
1
0201
1
AUD_PWR_EN
BYPASS=U6300.B1:C2:5 MMC6301
2.2UF
X5R-CERM
CRITICAL
10%
1
10V2
0402
21
2
2
R6306
331
R6303
MF
201
1/20W
1%
100K1
R6302
MF
201
1/20W
5%
47K
L83_SDOUT
BYPASS=U6300.E6:F6:5 MM
BYPASS=U6300.G6:F6:5 MM
BYPASS=U6300.D6:F6:5 MM
2
1
PLACE_NEAR=U6300:5mm
XW6301
SHORT-8L-0.25MM-SM
CRITICAL
GND_VCP
2
C6305
4.7UF
C6306
4.7UF
2
C6302
X5R-CERM
2.2UF
1
1
10V
10%
0402
10V
0402
10%
X5R
OMIT_TABLE
OMIT_TABLE
20
R6304
1
21
0402
X5R
10%
10V
5%5%
201
1/20W
MF
C6380
0201
C0G
25V
5%
47PF
NOSTUFF
BYPASS=U6300.G7:F7:5 MM
2
12.2UF
21
X5R-CERM
10%
0402
10V
2.2UF
X5R-CERM
2
0402
10V
10%
1
SYNC_MASTER=X363_AUDIO
C6307CRITICAL
C6308
CRITICAL
BOM_COST_GROUP=AUDIO
1/20W
201
MF
BYPASS=U6300.C1:C2:5 MM
BYPASS=U6300.E7:F7:5 MM
61 
61 
58 
58 
C6310
20%
X5R
10V
0603
10UF
CRITICAL
1
2
AUD_CODEC_WAKE_L
L83_VCP_FILTN
L83_VCP_FILTP
AUD_I2C_1B_SCL
AUD_I2C_1B_SDA
L83_FLYN
L83_FLYC
L83_SDOUT_R
L83_FLYP
A7 D
6
B1
E6
G6
F6
C6
C4
B7
D4
D3
A6
C5
A5
A4
B5
U6300
WLCSP-SKT
CS42L83A
CRITICAL
A3D7
L83_VCP
L83_VL
1
10%
50V
X7R 2
L83_VP
1
2
E5
D5
G5
F5
F1
E2
G2
F2
D1
E1
E4
G3
F4
G4
PLACE_NEAR=U6300:10mm
NOSTUFF
B4
B2
C3
A1
F7
G7
E7
A2
C1 L83_FILTP
D2C2C7 G
1
GND_AUDIO_CODEC
C6305,C6306 CRITICAL
B6
E3
F3
B3
2 CAP,CER,4.7UF,20%,10V,X5R,0402,MURATA
BYPASS=U6300.F3:E3:5 MM
C6303
0.1UF
CRITICAL
603-1
C6304
0402-7
10V
X5R-CERM
10UF
CRITICAL
20%
FERR-22-OHM-1A-0.055OHM
FERR-22-OHM-1A-0.055OHM
FERR-22-OHM-1A-0.055OHM
2
1
L83_HSBIAS_FILT
L83_HSBIAS_FILT_REF
L6300
GND_AUDIO_CODEC
PP1V8_S0_LDO_AUD
2
2
L6301
0201
0201
1
1
2
L6302
0201
1
AUD_HP_SENSE_L
BYPASS=U6300.A3:B3:5 MM
BYPASS=U6300.D7:C7:5 MM
62 
560PF
C0G
25V
0201
5%
C6320201
201
AUD_TIP_SENSE
AUD_HP_SENSE_R
X5R-X7R
NOSTUFF
PLACE_NEAR=U6300:10mm
NOSTUFF
X5R-X7R
PLACE_NEAR=U6300:10mm
AUD_HP_PORT_CH_GND
AUD_RING_SENSE
AUD_HP_PORT_US_GND
16V
16V
10%
10%
1
1
62 
62 
2470PF
2470PF
62 
62 
HS_MIC_N
HS_MIC_P
R6350
C6321
C6322
PP1V8_S0_LDO_AUD
1
2
1
R6300
201
5%
1K
1/20W
MF
R6301
5%
1K
AUD_HP_PORT_L
GND_AUDIO_CODEC
1/20W
2
100K
1
5%
1/20W
2
MF
201
1
10%
10V 2
0201
C6351
X7R-CERM
3300PF
CRITICAL
201
MF
AUD_HP_PORT_R
R6351
1
201
2.2K
1%
MF
1/20W
1
1%
2.2K
201
MF
1/20W
R6352
2
1
5%
25V
2
2C0G
2
C6309CRITICAL
20%
X5R
402
6.3V
4.7UF
1
1/20W
5%
0
MF
R63101
2012
138S0719
PLACE_NEAR=U6300:10mm
C6352
27PF
CRITICAL
0201
62 
62 
NO_XNET_CONNECTION=1
NO_XNET_CONNECTION=1
AUD_HS_MIC_N
AUD_HS_MIC_P62 
62 
59 
117 59 
12 
59 117 
59 
59 
117 
59 
59 117 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
BI
BI
OUT
EPADGND
EN
IN
HS4_REF
HPSENSB
HPOUTB
HPOUTA
HPSENSA
HSIN-
HS_CLAMP1
HSIN+
HS3
HS4
HS_CLAMP2
VD_FILT
-VCP_FILT
+VCP_FILT
FLYC
FLYN
FLYP
VP
ASP_LRCK/FSYNC
VL VA VCP
VL_SEL
RESET*
WAKE*
INT*
DIGLDO_PDN*
GNDCP
GNDHS GNDAGNDD
SPDIF_TX
SWIRE_SEL
SWIRE_SD/ASP_SDIN
ASP_SDOUT
SWIRE_CLK/ASP_SCLK
AD0
AD1
SDA
SCL
FILT_P
HS3_REF
RING_SENSE
TIP_SENSE
HSBIAS_FILT
HSBIAS_FILT_REF
GNDL
OUT
OUT
IN
IN
IN
IN
IN
BI
NC
OUT
OUT
IN
IN
IN
IN
N
C
IN
APN: 353S00604 
0dBFS = 9VPK
2X MONOSPEAKER AMPLIFIER
I2C ADDRESS = 0x32
I2C ADDRESS = 0x31
APN: 518S00521
LEFT SPEAKER CONNECTOR
60 OF 121
PP1V8_S0
58 60 61 109 
PPBUS_G3H 60 61 109 
PP1V8_S0
58 60 61 109 
PPBUS_G3H60 61 109 
PP1V8_S0 58 60 61 109 
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
64 OF 145
10.0.0
051-00647
dvt-fab10
AUD_ASP1A_SCLK
AUD_I2C_1A_SDA
AUD_ASP1A_SCLK
AUD_ASP1A_LRCLK
AUD_ASP1A_LRCLK
AUD_ASP1A_SDOUT
SPKRAMP_TL_SCLK
SPKRAMP_TL_SDIN
SPKRAMP_TL_LRCLK
VREF_AMP_WL
SPKRAMP_WL_SDINAUD_ASP1A_SDOUT
SPKRAMP_TL_OUT_POS
VREF_AMP_TL
AUD_I2C_1A_SCL
SPKRCONN_WL_OUT_NEG
SPKRCONN_WL_OUT_POS
SPKRAMP_WL_SCLK
SPKRAMP_WL_LRCLK
SPKRAMP_TL_OUT_NEG
AUD_SPKRAMP_INT_L
AUD_I2C_1A_SCL
AUD_I2C_1A_SDA
SPKRAMP_WL_OUT_POS
AUD_SPKRAMP_RESET_L
SPKRAMP_WL_OUT_NEG
SPKRCONN_TL_OUT_NEG
SPKRCONN_TL_OUT_POS
SYNC_DATE=01/25/2016SYNC_MASTER=X363_AUDIO
AUDIO Speaker Amps & Conn
BOM_COST_GROUP=AUDIO
78171-0004
M-RT-SM
J6410
5
6
1
2
3
4
60 58 
60 58 
60 58 
1/20W
0
MF
5%
201
PLACE_NEAR=U6450:5MM R6455
1 2
1/20W
0
MF
5%
201
PLACE_NEAR=U6450:5MM R6452
1 2
1/20W
5%
MF
0
201
PLACE_NEAR=U6450:5MM R6453
1 2
60 58 
60 58 
CRITICAL
MAX98706
WLP
U6450
B5
A5
C4 D4
E6
B4
D6
C5
A4
D5
C6
B1
B2
A1
D1
D2
E1
B3 C1 C2 C3 D3
A2 E2 A3 E3
E5
A6
B6
E4
10V
X5R-CERM
1.0UF
20%
0201-1
BYPASS=U6450.A4:B4:5 MM C64551
2
10V
X5R-CERM
1.0UF
20%
0201-1
BYPASS=U6450.E4:C4:5 MM C64501
2
180OHM-3.4A
0806
L6451
1 2
5%
25V
C0G-CERM
220PF
0402
C64561
2 C0G-CERM
220PF
5%
25V
0402
C64571
2
X7R-CERM
0.1UF
16V
10%
0402
BYPASS=U6450.E3:D3:5 MM
C64511
2
10%
16V
0.1UF
X7R-CERM
0402
BYPASS=U6450.A3:B3:5 MM
C64521
2 X5R-CERM
10UF
20%
35V
0603
BYPASS=U6450.E2:C2:10 MM
C64531
2
180OHM-3.4A
0806
L6450
1 2
0603
35V
X5R-CERM
10UF
20%
BYPASS=U6450.A2:C2:10 MM
C64541
2
20%
SM-1
100UF
20V
POLY
C64811
2
20%
100UF
SM-1
POLY
20V
C64801
235VX5R-CERM
20%
10UF
0603
BYPASS=U6400.A2:C2:10 MM
C64041
2
10UF
20%
0603
X5R-CERM
35V
BYPASS=U6400.E2:C2:10 MM
C64031
2
0402
X7R-CERM
BYPASS=U6400.A3:B3:5 MM
16V
10%
0.1UF
C64021
216VX7R-CERM
10%
0402
0.1UF
BYPASS=U6400.E3:D3:5 MM
C64011
2
WLP
CRITICAL
MAX98706
U6400
B5
A5
C4 D4
E6
B4
D6
C5
A4
D5
C6
B1
B2
A1
D1
D2
E1
B3 C1 C2 C3 D3
A2 E2 A3 E3
E5
A6
B6
E4
61 58 
61 58 
100K
MF
5%
201
1/20W
R64011
2
60 
58 
60 
58 
60 
58 
60 58 
60 58 
220PF
C0G-CERM
0402
5%
25V
C64071
2
220PF
0402
C0G-CERM
25V
5%
C64061
2
180OHM-3.4A
0806
L6401
1 2
180OHM-3.4A
0806
L6400
1 2
201
0
1/20W
5%
PLACE_NEAR=U6400:5MM
MF
R6405
1 2
MF
5%
0
201
1/20W
PLACE_NEAR=U6400:5MM R6402
1 2
MF
0
5%
201
1/20W
PLACE_NEAR=U6400:5MM R6403
1 2
BYPASS=U6400.E4:C4:5 MM
1.0UF
X5R-CERM
20%
10V
0201-1
C64001
2
1.0UF
0201-1
10V
BYPASS=U6400.A4:B4:5 MM
X5R-CERM
20%
C64051
2
114 
114 
114 
114 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
BI
DVDD
PVDD
ADDR0
ADDR1
OUTNSNS
OUTN
OUTP
OUTPSNS
DOUT
LRCLK
BCLK
SDA
IRQ*
SCL
VR
EF
C
RESET*
PGNDDGNDAGND
DIN
NC
NC
DVDD
PVDD
ADDR0
ADDR1
OUTNSNS
OUTN
OUTP
OUTPSNS
DOUT
LRCLK
BCLK
SDA
IRQ*
SCL
VR
EF
C
RESET*
PGNDDGNDAGND
DIN
IN
OUT
IN
IN
IN
IN
BI
0dBFS = 9VPK
2X MONO SPEAKER AMPLIFIER
I2C ADDRESS = 0X3A
RIGHT SPEAKER CONNECTOR
APN: 518S0672
APN: 353S00604 
I2C ADDRESS = 0X39
61 OF 121
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
PP1V8_S058 60 61 109 
PP1V8_S0
58 60 61 109 
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
PPBUS_G3H 60 61 109 
PPBUS_G3H 60 61 109 
65 OF 145
10.0.0
051-00647
dvt-fab10
SPKRAMP_WR_OUT_POS
AUD_ASP1B_SDOUT
SPKRAMP_TR_OUT_POS
PP1V8_S0
VREF_AMP_TR
AUD_I2C_1B_SCL
AUD_I2C_1B_SCL
AUD_I2C_1B_SDA
AUD_I2C_1B_SDA
SPKRAMP_R_SDIN
SPKRAMP_R_LRCLK
SPKRAMP_R_SCLK
SPKRAMP_WR_SCLK
AUD_ASP1B_LRCLK
AUD_ASP1B_SCLK
AUD_ASP1B_SCLK
AUD_ASP1B_SDOUT
AUD_ASP1B_LRCLK
SPKRAMP_WR_SDIN
SPKRAMP_WR_LRCLK
AUD_SPKRAMP_INT_L
AUD_SPKRAMP_RESET_L
PP1V8_S0
SPKRAMP_TR_OUT_NEG
SPKRAMP_WR_OUT_NEG
VREF_AMP_WR
SPKRCONN_WR_OUT_POS
SPKRCONN_WR_OUT_NEG
SPKR_ID0
SPKRCONN_TR_OUT_POS
SPKRCONN_TR_OUT_NEG
SYNC_DATE=01/25/2016SYNC_MASTER=X363_AUDIO
BOM_COST_GROUP=AUDIO
AUDIO Speaker Amps & Conn
78171-6006
M-RT-SM
J6500
7
8
1
2
3
4
5
6
114 58 
61 58 
61 58 
61 58 
MF
5%
0
1/20W
PLACE_NEAR=U6550:5MM
201
R6555
1 2
0
5%
MF
1/20W
PLACE_NEAR=U6550:5MM
201
R6553
1 2
MF
1/20W
5%
0
PLACE_NEAR=U6550:5MM
201
R6552
1 2
61 59 58 
61 59 58 
CRITICAL
MAX98706
WLP
U6550
B5
A5
C4 D4
E6
B4
D6
C5
A4
D5
C6
B1
B2
A1
D1
D2
E1
B3 C1 C2 C3 D3
A2 E2 A3 E3
E5
A6
B6
E4
20%
1.0UF
X5R-CERM
10V
BYPASS=U6550.A4:B4:5 MM
0201-1
C65551
2
20%
1.0UF
X5R-CERM
10V
BYPASS=U6550.E4:C4:5 MM
0201-1
C65501
2
180OHM-3.4A
CRITICAL
0806
FL6551
1 2
180OHM-3.4A
CRITICAL
0806
FL6550
1 2
220PF
5%
25V
C0G-CERM
0402
C65561
2
220PF
C0G-CERM
25V
5%
0402
C65571
2
X7R-CERM
0.1UF
10%
16V
BYPASS=U6550.E3:D3:5 MM
0402
C65511
2
10%
16V
X7R-CERM
0.1UF
BYPASS=U6550.A3:B3:5 MM
0402
C65521
2
BYPASS=U6550.A2:C2:10 MM
X5R-CERM
35V
10UF
20%
0603
C65531
2
20%
10UF
35V
X5R-CERM
BYPASS=U6550.E2:C2:10 MM
0603
C65541
2
100UF
20V
POLY
SM-1
20%
C65811
2
POLY
SM-1
20V
100UF
20%
C65801
2
0603
BYPASS=U6500.E2:C2:10 MM
35V
X5R-CERM
10UF
20%
C65041
2X5R-CERM
BYPASS=U6500.A2:C2:10 MM
35V
0603
10UF
20%
C65031
2
BYPASS=U6500.A3:B3:5 MM
0.1UF
X7R-CERM
0402
16V
10%
C65021
216V
0402
10%
0.1UF
X7R-CERM
BYPASS=U6500.E3:D3:5 MM
C65011
2
CRITICAL
WLP
MAX98706
U6500
B5
A5
C4 D4
E6
B4
D6
C5
A4
D5
C6
B1
B2
A1
D1
D2
E1
B3 C1 C2 C3 D3
A2 E2 A3 E3
E5
A6
B6
E4
60 58 
60 58 
61 58 
61 58 
61 58 
61 59 58 
61 59 58 
220PF
25V
0402
C0G-CERM
5%
C65071
2C0G-CERM
25V
5%
0402
220PF
C65061
2
0806
CRITICAL
180OHM-3.4A
FL6501
1 2
CRITICAL
0806
180OHM-3.4A
FL6500
1 2
1/20W
0
5%
MF
201
PLACE_NEAR=U6500:5MM R6505
1 2
PLACE_NEAR=U6500:5MM
5%
201
1/20W
MF
0
R6502
1 2
1/20W
MF
201
5%
0
PLACE_NEAR=U6500:5MM R6503
1 2
10V
X5R-CERM
0201-1
1.0UF
20%
BYPASS=U6500.E4:C4:5 MM C65001
2
BYPASS=U6500.A4:B4:5 MM
X5R-CERM
1.0UF
0201-1
10V
20%
C65051
2
114 109 61 
114 109 61 
114 
114 
114 
114 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
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REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
OUT
IN
IN
IN
IN
BI
NC
DVDD
PVDD
ADDR0
ADDR1
OUTNSNS
OUTN
OUTP
OUTPSNS
DOUT
LRCLK
BCLK
SDA
IRQ*
SCL
VR
EF
C
RESET*
PGNDDGNDAGND
DIN
NC
DVDD
PVDD
ADDR0
ADDR1
OUTNSNS
OUTN
OUTP
OUTPSNS
DOUT
LRCLK
BCLK
SDA
IRQ*
SCL
VR
EF
C
RESET*
PGNDDGNDAGND
DIN
IN
OUT
IN
IN
IN
IN
BI
Audio Jack Flex Connector
(Matching plug APN: 510S0010)
APN: 510S0009
62 OF 121
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.5000
MIN_NECK_WIDTH=0.1000
MIN_LINE_WIDTH=0.2000
66 OF 145
10.0.0
051-00647
dvt-fab10
AUD_CONN_HP_RIGHT
AUD_CONN_RING2_XW
AUD_CONN_SLEEVE_XW
AUD_TIP_SENSE
AUD_HP_SENSE_L
AUD_HS_MIC_N
AUD_HP_PORT_R
AUD_HP_PORT_L
AUD_HS_MIC_P
AUD_HP_SENSE_RAUD_HP_PORT_CH_GND
AUD_HP_PORT_US_GND
AUD_CONN_HP_SENSE_R
AUD_CONN_HP_LEFT
AUD_CONN_HP_RIGHT
AUD_CONN_RING2
AUD_CONN_RING2
AUD_CONN_SLEEVE
AUD_CONN_HP_SENSE_L
AUD_CONN_TIP_SENSE
AUD_CONN_SLEEVE
AUD_CONN_HP_LEFT
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=AUDIO
AUDIO JACK CONNECTOR
F-ST-SM
51138-0274
J6600
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21
22
23
24
1%
1/20W
2K
MF
201
R6600
1 259 
59 
120-OHM-25%-1.3A
0402
CRITICAL
FL6607
1 2
59 
120-OHM-25%-1.3A
0402
CRITICAL
FL6606
1 2
59 
0402
120-OHM-25%-1.3A
CRITICAL
FL6605
1 2
120-OHM-25%-1.3A
CRITICAL
0402
FL6604
1 2
0402
120-OHM-25%-1.3A
CRITICAL
FL6603
1 2
CRITICAL
120-OHM-25%-1.3A
0402
FL6602
1 2
59 
120-OHM-25%-1.3A
0402
CRITICAL
FL6601
1 2
CRITICAL
0402
120-OHM-25%-1.3A
FL6600
1 2
59 
59 
59 
59 114 62 
114 
114 
114 
114 62 
114 62 
114 62 
114 62 
114 62 
114 
114 
114 62 
114 62 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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DRAWING NUMBER SIZE
D
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 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
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2 1
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NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
FROM USB-C SOURCE
BMU POWER FLEX HOTBAR'd TO THE MLB:
C6919 FOR DESENSE
 APN:518S0818
J80 Battery Hotbar Flex Pads 998-03902
 Flex Pad TO MLB 998-03780.
63 OF 121
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.6000
VOLTAGE=13.1V
MIN_LINE_WIDTH=0.4000
MIN_NECK_WIDTH=0.1200
VOLTAGE=3.3V
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
MIN_LINE_WIDTH=0.2000
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=8.6V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=8.6V
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
DIDT=TRUE
PP3V3_G3H 109 
PPBUS_G3H109 
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=8.6V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
69 OF 145
10.0.0
051-00647
dvt-fab10
PPBUS_G3H_R
PP3V3_G3H_REG_R
TP_BMON_IOUT
SYS_DETECT_L
P3V3G3H_FB
PPVBAT_G3H_CONN
P3V3G3H_LX
PPVIN_G3H_P3V3G3H
PM_EN_P3V3_G3H
PPDCIN_G3H_CHGR_R
P3V3G3H_VBST_R
P3V3G3H_FB_R
P3V3G3H_AGND
PM_EN_P3V3_G3H_R
PPDCIN_G3H_CHGR
P3V3G3H_VBST
P3V3G3H_BIAS
P3V3G3H_FB_RC
632-00862 PCBA,FLEX,BMU PWR,X3631 J6950 CRITICAL
SYNC_DATE=11/06/2015
DC-In & Battery Connectors
BOM_COST_GROUP=PLATFORM POWER
SYNC_MASTER=J80_MLB
603-1
X5R
1UF
25V
10%
C6960 1
2
10K
5%
1/16W
MF-LF
402
R69501
2
CRITICAL
SLP1006N3T
RCLAMP3552T
D6950
3
1 2
49 
49 
NP0-C0G
0201
5%
12PF
25V
CRITICAL
C69191
2
0201
MF
1/20W
0.1%
115K
R6910
1 2
201
1.47K
1%
1/20W
MF
R69131
2
10
5%
201
MF
1/20W
R69121
2
805
5%
2.2
MF-LF
1/8W
R6907
1 2
BAT30CWFILM
SOT-323
D6902
1
2
3
10UF
20%
6.3V
CERM-X5R
0402
CRITICAL
C69121
2
+/-0.1PF
5.6PF
25V
C0G
0201
C6911
12
0201
X5R-CERM
16V
10%
0.1UF
C69071
2
CERM-X7R
16V
10%
0.33UF
603
C69101
2 0201
1/20W
47K
MF
0.1%
R69111
2
SM
XW6900
1 2
TDFN
MAX77596
CRITICAL
U6903
5
8
1
10
3
7
9
4
6
2
11
PIYA25201B-SM
CRITICAL
10UH-20%-1.4A-0.399OHM
L6900
1 2
114 
20%
35V
0402
2.2UF
X5R-CERM
C69061
2
F-RT-SM
FF14A-6C-R11DL-B-3H
J6951
1
2
3
4
5
6
7
8
OMIT_TABLE
CRITICAL
HB-SM
PWR-MLB-X363
J6950
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
TP-P5
TP6910 1
MF-LF
5%
0
1/10W
603
R6923
1 2
0
1/16W
5%
MF-LF
402
R6920
1 2
0402
CERM-X5R
10UF
6.3V
20%
CRITICAL
C69161
2
0402
CERM-X5R
10UF
6.3V
20%
CRITICAL
C69171
26.3V
20%
0402
CERM-X5R
10UF
CRITICAL
C69151
2
10UF
0402
CERM-X5R
6.3V
20%
CRITICAL
C69141
2
0402
10UF
6.3V
20%
CERM-X5R
CRITICAL
C69131
2
1/20W
MF
5%
0
0201
R69081
2
1/20W
MF
0
5%
201
R6921
1 2
0.1UF
X5R
402
25V
10%
C6950 1
2
X5R-CERM
35V
2.2UF
0402
20%
C69051
2
114 
114 64 
64 
64 
116 114 64 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
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THE POSESSOR AGREES TO THE FOLLOWING:
36
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DRAWING NUMBER SIZE
D
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 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
BI
BI
EP
AD
AG
ND
PG
ND
EN
MODE
SUP
RESET* BIAS
OUT/FB
LX
BST
NC
OUT
NC
NC
TP
TO/FROM BATTERY
4X D2
(BMON)
(PBUS)
8X B1
(AMON)
FROM USB-C SOURCE
TO SYSTEM
64 OF 121
SMBUS_SMC_5_G3_SCL
SMC_CHGR_INT_L
48 64 
SMC_BC_ACOK
SMC_CHGR_INT_L
SMBUS_SMC_5_G3_SDA
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
PPBUS_G3H 109 116 
PP3V3_G3H109 
70 OF 145
10.0.0
051-00647
dvt-fab10
CHGR_BMON
TBA_GATE_Q3
TBA_CSO_R_P
TBA_PHASE2
SMC_RST_L
TBA_BGATE
TBA_GATE_Q2
TBA_LX2
TBA_CSO_N
TBA_GATE_Q4
TBA_LX1
TBA_GATE_Q1
TBA_CSI_P
TBA_GATE_Q4
SMC_4FINGERS_RST
TBA_LX2
TBA_LX1
TBA_GATE_Q3
TBA_GATE_Q2
TBA_GATE_Q1
TBA_BOOT1_RC
CHGR_AMON
SMC_CBC_ON
PPVIN_G3H_P3V3G3H
TBA_BOOT2
SMC_RESET_L
PPVIN_G3H_P3V3G3H
TBA_COMP
TBA_PHASE1
TBA_CSI_R_P TBA_CSI_R_N
TBA_VDDA
HPWR_EN_L PM_EN_P3V3_G3H
TBA_CSO_P
TBA_CSO_R_N
TBA_VDDP
TBA_AUX_DET
TBA_CSI_N
TBA_BOOT1
PPVBAT_G3H_CHGR_R
TBA_BOOT2_RC
PPVBAT_G3H_CONN
PPDCIN_G3H
PPVBAT_G3H_CHGR_REG
PPDCIN_G3H_CHGR
SYNC_DATE=11/06/2015SYNC_MASTER=J80_MLB
BOM_COST_GROUP=PLATFORM POWER
PBUS Supply & Battery Charger
L7030IND,MLD,2.7UH,16A,14.8MO,10.9x10.0x3.00152S00199 1 CRITICAL
201
1/20W
MF
1%
255K
R70161
2
25V
2.2UF
20%
X5R
0402-1
C70581
2
2.2UF
0402-1
25V
X5R
20%
C70571
2
TP-P5
TP70071
TP-P5
TP70061
TP-P5
TP70051
TP-P5
TP70041
TP-P5
TP70031
TP-P5
TP70021
TP-P5
TP70011
IHLP4040CZ-PIMA103T-SM-COMBO
2.7UH-20%-21.5A-0.0135OHM
BOMOPTION=OMIT_TABLE
CRITICAL
L7030
1 2
CRITICAL
1%
MF
1W
0.005
0612-5
R7060
12
34
114 76 57 48 29 
5%
MF
1/20W
100K
201
R7090
1 2
NO STUFF
10%
CERM-X5R
10.0V
402
0.12UF
C7070 1
2
5%
1/20W
MF
201
100K
R70091
2
10V
X5R-CERM
0201-1
1.0UF
20%
C7080 1
2
1/20W
1%
MF-LF
0201
1.00
R70621
2
1%
1/20W
MF-LF
0201
1.00
R70611
2
0201
1/20W
MF-LF
1%
1.00
R70221
2
1/20W
MF-LF
1.00
1%
0201
R70211
2
1206
CRITICAL
12AMP-32V
F7001
1 2
CRITICAL
1206
12AMP-32V
F7000
1 2
CRITICAL
16V
POLY-TANT
CASE-D2E-SM
68UF
20%
C70561
2
CRITICAL
16V
POLY-TANT
CASE-D2E-SM
68UF
20%
C70521
2CASE-B1-2-SM
POLY-TANT
35V-0.09OHM
6.8UF
CRITICAL
20%
C70431
2
CRITICAL
6.8UF
35V-0.09OHM
CASE-B1-2-SM
POLY-TANT
20%
C70421
2
0306
CRITICAL
0.5W
MF
0.5%
0.01
R7020
12
34
0.1UF
PLACE_NEAR=Q7065.5:2MM
25V
10%
X5R
0201
C70601
2
0201
X7R
1000PF
25V
10%
C7064
1 2
2.2UF
25V
0402-1
X5R
20%
C7069 1
2
0402-1
2.2UF
25V
X5R
20%
C70551
2
35V
0402
X5R-CERM
2.2UF
PLACE_NEAR=U7000.A5:2MM
20%
C7081 1
2
CRITICAL
35V-0.09OHM
6.8UF
CASE-B1-2-SM
POLY-TANT
20%
C70241
2
6.8UF
CASE-B1-2-SM
CRITICAL
35V-0.09OHM
20%
POLY-TANT
C70291
2
0.47UF
PLACE_NEAR=U7000.A4:1MM
CERM-X5R-1
4V
201
20%
C7020
12
CERM-X5R-1
0.47UF
4V
PLACE_NEAR=U7000.C5:1MM
201
20%
C7023
12
1/20W
MF
201
5%
4.7
R7075
1 2
114 50 
114 50 
BOMOPTION=OMIT_TABLE
WCSP-1
ISL9239
U7000
C2
E3
D4
D3
F3
B3
C4
F1
C1
H2G4
E5
C5
D5
B4
A4
F2
H1
E1
D1
A1
G3
H3
G1
B1
E4
F4
A5
B5
A3
E2
H5
G5
B2
C3
A2 D2
F5
H4
G2
16V
POLY-TANT
CASE-D2E-SM
68UF
20%
CRITICAL
C70511
2
48 
48 
46 
64 48 
49 
49 
63 
10.0V
CERM-X5R
402
10%
0.12UF
C70711
2
X5R-CERM
0603
25V
10UF
20%
C7077 1
2
0402
X6S-CERM
2.2UF
25V
20%
C70751
2
0.01UF
X5R-CERM
0201
NO STUFF
25V
10%
C7016 1
2
750K
1/20W
MF
1%
201R70151
2
0402-1
2.2UF
25V
X5R
20%
C70531
2
4700PF
CER-X5R
25V
10%
0201
C70631
2
CER-X7R
0.047UF
0402
50V
10%
C7061 1
2
0402
50V
0.047UF
10%
CER-X7R
C70621
2
25V
2.2UF
0402-1
X5R
20%
C7066 1
2
0201
X5R
25V
0.1UF
10%
C7067 1
2
0201
25V
0.01UF
10%
X5R-CERM
C7068 1
2
SO-8
SI7137DP
CRITICAL
Q7065
5
4
1
2
3402
5%
1/16W
MF-LF
0
R70401
2
0.1UF
25V
10%
0402
X7R-CERM
C7040 1
2
402
5%
0
1/16W
MF-LF
R70301
2
0.1UF
25V
10%
X7R-CERM
0402
C70301
2
CRITICAL
16V
POLY-TANT
CASE-D2E-SM
68UF
20%
C70501
2
0201
X7R
25V
10%
1000PF
C70541
2
35V
0402
X5R-CERM
2.2UF
20%
C70351
235V-0.09OHM
CASE-B1-2-SM
CRITICAL
6.8UF
POLY-TANT
20%
C70251
2
CRITICAL
CASE-B1-2-SM
35V-0.09OHM
6.8UF
POLY-TANT
20%
C70261
2
6.8UF
35V-0.09OHM
CASE-B1-2-SM
CRITICAL
POLY-TANT
20%
C70271
2 35V-0.09OHM
CRITICAL
6.8UF
CASE-B1-2-SM
POLY-TANT
20%
C70281
2
0402
35V
X5R-CERM
2.2UF
20%
C70321
2
2.2UF
20%
X5R-CERM
PLACE_NEAR=Q7030.2:1MM
0402
35V
C70331
2
PLACE_NEAR=Q7030.1:3mm
2.2UF
0402
35V
20%
X5R-CERM
C70341
2
0.047UF
50V
0402
CER-X7R
10%
C70221
2CER-X7R
50V
0.047UF
0402
10%
C7021 1
2
FD
MD
88
00
DF
N
Q
70
40
12313
12114
789105614
DF
N
FD
MD
88
00
Q
70
30
1 2 3 13
12 11 4
7 8 9 10 5 6 14
114 64 
64 
114 64 
114 64 
64 
64 
64 
64 
63 
64 63 
114 
114 
114 63 
116 114 50 29 
114 
116 114 63 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
TP
TP
TP
TP
TP
TP
TP
NC
OUT
OUT
OUT
SGATE
PG
ND
AG
ND
VD
DP
VD
DA
BMON
AMON
AUX_OK
MPM_OK
CBC_ON
IRQ*
VBAT
EN_VR1
SMC_RST*
BGATE
CSON
CSOP
BOOT2
LX2
GATE_Q3
GATE_Q2
LX1
BOOT1
GATE_Q1
CELL
MPM_DET
AGATE
AUX_DET
MPM_PBUS
CSIP
VR1_3P3
SDA
SCL
SMC_RST_IN
HPWR_EN*
COMP
P_IN
GATE_Q4
PBUS
CSIN
IN
OUT
OUT
OUT
BI
IN
OUT
S
SYM-VER-2
D
G
S1
/D
2
D1S2
G
1
G
1R
G
2
S1
/D
2
D1 S2
G
1
G
1R
G
2
CPU VCC Core
CPU VCC GT + GTx Merged
CPU VCC SA
65 OF 121
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=12.6V
ALL_SYS_PWRGD
VOLTAGE=5V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
CPUVR_PGOOD 73 
PP5V_S4 110 
PP5V_S0 66 67 110 
PPBUS_HS_CPU109 
PP1V0_S3 110 
71 OF 145
10.0.0
051-00647
dvt-fab10
PPVIN_S0_CPUVR_VIN
NTC_A_CPUCORE_R
CPUSA_ISUMP
CPUCORE_VIDSCLK_R
CPU_PROCHOT_L
COMP_A_CPUCORE_L
SA_ISUMN_R
CPUSA_ISUMN
COMP_B_CPUGT
CPUGT_ISUMN
CPUGT_PWM1
COMP_C_CPUSA
RTN_C_CPUSA
COMP_B_CPUGT
IMON_B_CPUGT
IMON_B_CPUGT
NTC_A_CPUCORE
NTC_B_CPUGT
CPU_VR_EN_R
IMON_A_CPUCORE
COMP_A_CPUCORE
CPUCORE_ISEN2
PROG2_CPUCOREVR
IMON_C_CPUSA
CPU_VCCSASENSE_N RTN_C_CPUSA
FB_C_CPUSA
CPU_VCCGTSENSE_P
RTN_B_CPUGT
CPU_VIDSCLK
CPUCORE_VIDALERT_R_L
IMON_C_CPUSA
CPUGT_ISEN1
CPUCORE_PROCHOT_R_L
CPUCORE_FCCM
PP5V_COREVR_VCC
FB_C_CPUSA_RC
FB_SA_R
CPUCORE_ISEN3
NTC_A_CPUCORE
GT_ISUMN_R
CPUGT_ISEN2
FB_B_CPUGT
FB_B_CPUGT_RC
FB_GT_R
CPU_VCCGTSENSE_N
CPUCORE_PWM1
CPUCORE_ISUMN
CPUCORE_ISEN1
CPUCORE_ISUMP
CPUCORE_ISUMN_R
CPUCORE_ISEN2
CORE_ISUMN_R
IMON_A_CPUCORE
FB_A_CPUCORE_RC
CPUCORE_PSYS
PROG5_CPUCOREVR
PROG4_CPUCOREVR
CPU_VCCSENSE_P
RTN_A_CPUCORE
CPUCORE_VIDSOUT_R
FB_B_CPUGT
RTN_B_CPUGT
CPU_VIDSOUT
PROG4_CPUCOREVR
COMP_C_CPUSA
FB_C_CPUSA
CPUGT_ISEN2
CPUGT_ISEN1
CPUSA_ISUMP
COMP_B_CPUGT_L
COMP_C_CPUSA_L
CPUCORE_ISEN3
CPUSA_PWM
PROG1_CPUCOREVR
CPUGT_FCCM
PROG3_CPUCOREVR
PROG5_CPUCOREVR
CPUCORE_PWM2
CPUCORE_ISEN1
CPUGT_ISUMN_R
CPUGT_ISUMP
FB_A_CORE_R
FB_C_SA_R
PROG3_CPUCOREVR
PROG1_CPUCOREVR
CPU_VCCSENSE_N
PROG2_CPUCOREVR
CPUGT_PWM2
FB_B_GT_R
CPUCORE_ISUMN_R
CPUCORE_PWM3
CPUGT_ISUMP
RTN_A_CPUCORE
CPUSA_ISUMN_R
NTC_B_CPUGT
CPUSA_FCCM
CPUCORE_ISUMP
COMP_A_CPUCORE
CPU_VCCSASENSE_P
FB_A_CPUCORE
FB_A_CPUCORE
FB_CORE_R
CPUGT_ISUMN_R
CPUSA_ISUMN_R
CPU_VIDALERT_L
NTC_B_CPUGT_R
CORE & SA IMVP IC
BOM_COST_GROUP=CPU & CHIPSET
SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN SYNC_DATE=12/10/2015
10V
X7R-CERM
0.01UF
10%
0201
C7182 1
2
50V
CER-C0G
0201
150PF
5%
C7190
12
1%
201
MF
1/20W
100K
R7190
12
1/20W
201
MF
1%
499
R7180
12
201
560
1/20W
1%
MF
R7175
1 2
201
1/20W
1%
2.49K
MF
R7173
12
10V
X7R-CERM
0.01UF
10%
0201
C71521
2
3300PF
10V
10%
0201
X7R-CERM
C7150
1 2
1/20W
1%
100K
MF
201
R7160
1 2
201
MF
1K
1%
1/20W
R7151
1 2
1/20W
1%
432
MF
201
R7150
12
201
560
MF
1%
1/20W
R7145
1 2
MF
1%
1/20W
3.01K
201
R7143
1 2
1/20W
1%
365
MF
201
R7154
1 2
10V
10%
0.01UF
X7R-CERM
0201
C71491
2
10%
10V
X7R-CERM
3300PF
0201
C7155
1 2
MF
100K
1%
1/20W
201
R7194
1 2
1/20W
1%
1K
MF
201
R7155
1 2
1%
2.61K
MF
201
1/20W
R7147
1 2
201
560
MF
1%
1/20W
R7149
1 2
220KOHM-3%
0201
R7124
1
2
201
MF
1/20W
1%
14K
R7121
1 2
68 65 
68 65 
0.01UF
10%
X7R-CERM
10V
0201
C7153 1
2
0.01UF
10V
X7R-CERM
0201
10%
C7154 1
2
25V
X7R-CERM
201
220PF
10%
C7151 1
2
68 
68 65 
820PF
X7R-CERM
25V
10%
0201
C71431
2
1%
201
MF
1K
1/20W
R7144
12
10%
3300PF
X7R-CERM
10V
0201
C7144
12MF
0
1/20W
5%
201
R7142
1 2
SM
XW7140
1 2
10%
330PF
16V
X7R
0201
C71421
2
330PF
X7R
16V
10%
0201
C7141 1
2
9 8 
8 
201
2.7K
1/20W
1%
MF
R7191
12
50V
CER-C0G
0201
150PF
5%
C7192
12
6800PF
10V
10%
X7R-CERM
0201
C7191
12
201
1%
1/20W
MF
4.64K
R7161
12
X7R-CERM
10V
10%
0201
6800PF
C7161
12
68PF
5%
25V
C0G
0201
C7162
12
50V
CER-C0G
0201
5%
150PF
C7160
12
8 
9 8 
66 65 
66 
66 65 
66 65 
66 65 
0.01UF
10V
X7R-CERM
10%
0201
C71591
2
10%
10V
X7R-CERM
0201
6800PF
C7194
1 2
25V
5%
56PF
NP0-C0G
0201
C7193
1 2
2.87K
201
1/20W
MF
1%
R7193
1 2
50V
CER-C0G
0201
150PF
5%
C7195
1 2
1/20W
0
MF
201
5%
R7146
12
470PF
16V
X5R-X7R-CERM
10%
0201
C7147
1 2
330PF
X7R
16V
10%
0201
C71451
2
330PF
10%
16V
X7R
0201
C7146 1
2
SM
XW7141
12
1/20W
1K
201
MF
1%
R7148
1 2
10%
X7R-CERM
680PF
25V
0201
C7148 1
2
X7R-CERM
10%
10V
0.01UF
0201
C71581
2X7R-CERM
10%
0.01UF
10V
0201
C71571
2
25V
201
10%
X7R-CERM
220PF
C71561
2
66 
66 
66 
66 
66 65 
66 65 
66 65 
66 65 
68 65 
68 65 
68 65 
68 
68 
68 
SVID_PU:CORE
1/20W
MF
1%
45.3
201
R71101
2
100
1/20W
1%
201
MF
SVID_PU:CORE
R71091
2
201
100
MF
5%
1/20W
R7102
1 2
9 8 
8 
820PF
X7R-CERM
25V
10%
0201
C71731
2
201
MF
1/20W
1%
1K
R7174
12
12.1K
1/20W
MF
1%
201
NOSTUFF
R71071
2
1/20W
MF
1%
201
1K
R7181
1 2
3300PF
10V
10%
X7R-CERM
0201
C7180
1 2
1%
201
MF
1/20W
14K
R7120
1 2
220KOHM-3%
0201
R7123
1
2
201
1%
MF
1/20W
110K
R71111
2
71.5K
1/20W
MF
1%
201
R71121
2 201
1/20W
MF
1%
16.9K
R71131
2
MF
201
182K
1/20W
1%
R71141
2 201
MF
1/20W
121K
1%
R71151
2
67 65 
67 
67 65 
0
MF
201
5%
1/20W
R7172
1 2
10%
16V
X7R
330PF
0201
C71721
2
SM
XW7170
1 2
10%
330PF
16V
X7R
0201
C7171 1
2
10%
2200PF
X7R-CERM
10V
0201
C7174
12
X7R-CERM
10%
25V
201
220PF
C7181 1
2
8 
8 
8 
1/20W
5%
MF
201
10
R7104
1 2
MF
1/20W
201
0
5%
R7105
1 2
201
49.9
1%
1/20W
MF
R7106
1 2
1%
12.1K
MF
1/20W
201
R71081
2
73 
201
0
1/20W
5%
MF
R7103
1 2
47 46 6 
1UF
0402
X6S-CERM
10V
10%
C71001
225V
10%
X7R
0402
0.22UF
C71011
2
201
5%
10
1/20W
MF
R7101
1 2
1/20W
5%
1
MF
201
R7100
1 2
67 
67 
10V
10%
X7R
201
4700PF
C71081
2
LLP
ISL95828HRTZ
U7100
44
164
29
175
30
2411
34
142
28
219
2210
23
208
33
197
32
153
40
39
38
37
36
1
2512
2613
27
186
31 45
43
49
4241
48
46
4735
65 
65 
65 
65 
65 55 
65 55 
65 
65 
65 55 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 55 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 
6565 
65 
65 
65 
65 
65 
65 
65 
65 
65 
65 
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
IN
IN
BI
IN
IN
IN
OUT
OUT
OUT
PWM3_A
PROG4
PROG3
PROG5
PROG2
PROG1
IMON_C
TH
RM
_P
AD
PSYS
RTN_C
FB_C
COMP_C
ISUMN_C
ISUMP_C
FCCM_C
PWM_C
NTC_B
IMON_B
RTN_B
FB_B
COMP_B
ISEN2_B
ISEN1_B
ISUMN_B
ISUMP_B
PWM2_B
PWM1_B
FCCM_B
SCLK
SDA
ALERT*
VR_ENABLE
VR_READY
VR_HOT*
NTC_A
IMON_A
RTN_A
FB_A
COMP_A
ISEN3_A
ISEN1_A
ISEN2_A
ISUMP_A
ISUMN_A
PWM1_A
PWM2_A
FCCM_A
VI
N
VC
C
CPU VCC Phase 1
ICCMAX = 68A
Vout = 0.55 - 1.5V
F = 750kHz
CPU VCC Phase 2
CPU VCC Phase 3
6X 2.2UF 0402
THESE TWO CAPS ARE FOR EMC
7x 33uF B3
THESE TWO CAPS ARE FOR EMC
66 OF 121
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
VOLTAGE=1.15V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
DIDT=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
SWITCH_NODE=TRUE
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
SWITCH_NODE=TRUE
PPBUS_HS_CPU66 109 
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
PP5V_S065 66 67 
110 
MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.1200
VOLTAGE=1.5V
PP5V_S065 66 67 
110 
PP5V_S065 66 67 
110 
DIDT=TRUE
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
PPVCC_S0_CPU 109 
MIN_LINE_WIDTH=0.2000
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
PPBUS_HS_CPU66 109 
PPBUS_HS_CPU66 109 
DIDT=TRUE
MIN_NECK_WIDTH=0.1200
MIN_LINE_WIDTH=0.2000
72 OF 145
10.0.0
051-00647
dvt-fab10
PPVCC_CPU_PH3
CPUCORE_ISNS1_P
CPUCORE_ISNS2_N
CPUCORE_ISUMP
CPUCORE_ISNS1_N
CPUCORE_ISNS3_P
CPUCORE_ISUMN
CPUCORE_BP3
CPUCORE_SW3_SNUB
CPUCORE_ISNS3_N
CPUCORE_ISEN3
CPUCORE_ISNS1_N
CPUCORE_ISNS2_N
CPUCORE_ISNS3_N
CPUCORE_SW2_SNUB
PVCCCORE_PH2_AGND
CPUCORE_ISNS3_N
CPUCORE_BP2
PVCCCORE_PH1_AGND
PVCCCORE_PH3_AGND
PPVCC_CPU_PH2
CPUCORE_ISNS2_P
CPUCORE_ISNS2_N
CPUCORE_ISUMN
CPUCORE_SW2
CPUCORE_PWM2
PVCCCORE_PH2_AGND
CPUCORE_BOOT2
PVCCCORE_PH3_VCC
CPUCORE_SW3
CPUCORE_FCCM
CPUCORE_PWM3
PVCCCORE_PH3_AGND
CPUCORE_PHASE3
CPUCORE_BOOT3
CPUCORE_FCCM
CPUCORE_PHASE2
CPUCORE_ISUMP
CPUCORE_ISEN2
CPUCORE_ISUMN
PVCCCORE_PH1_VCC
CPUCORE_FCCM
CPUCORE_PWM1
PVCCCORE_PH1_AGND
CPUCORE_PHASE1
CPUCORE_ISUMP
PPVCC_CPU_PH1CPUCORE_SW1
CPUCORE_ISEN1
CPUCORE_SW1_SNUB
CPUCORE_ISNS1_N
CPUCORE_BOOT1
PVCCCORE_PH2_VCC
CPUCORE_BP1
SYNC_DATE=09/03/2015SYNC_MASTER=J80_DTUZMAN_MLB_BAFFIN
BOM_COST_GROUP=CPU & CHIPSET
CORE IMVP POWER BLOCK
IC,SIC635,DRMOS,IMVP-8,40A,PQFN31,5X5 U7210,U7220,U72303353S00497 CRITICAL
PILA63T-SM
0.2UH-20%-28A-0.0011OHM
CRITICAL
L7211
1 2
PILA63T-SM
0.2UH-20%-28A-0.0011OHM
CRITICAL
L7221
1 2
0.2UH-20%-28A-0.0011OHM
PILA63T-SM
CRITICAL
L7231
1 2
65 
66 65 
1/16W
1
5%
402
MF-LF
R7236
1 2
PLACE_NEAR=U7230.32:2MM
SM
XW7230
12
PQFN-COMBO-THICKSTNCL
CRITICAL
FDMF5808A
OMIT_TABLE
U7230
4 32
5
2
6
27
3330
31
12 28
7
29
1
16
24
3
8
9
X6S-CERM
0402
20%
25V
2.2UF
C7237 1
2
0.22UF
X7R
25V
0402
10%
C7239 1
2
402
1/16W
MF-LF
0
5%
R7239 1
2
NOSTUFF
50V
0402
10%
X7R-CERM
0.001UF
C72381
2
5%
2.2
NOSTUFF
603
1/10W
MF-LF
R72381
2
2.2UF
20%
0402
X6S-CERM
25V
C72361
2
NO_XNET_CONNECTION
MF
1%
1K
1/20W
201
R7232 1
2
0612-1
1%
1W
MF
0.00075
CRITICAL
R7230
12
34
NO_XNET_CONNECTION
200K
1%
MF
201
1/20W
R72331
2
NO_XNET_CONNECTION
MF
1/20W
1%
2.2
201
R72311
2
66 51 
51 
66 65 
65 
MF
1/20W
201
1%
200K
NO_XNET_CONNECTION
R7235
12
200K
201
MF
1%
1/20W NO_XNET_CONNECTION
R7234
12
66 65 
200K
1%
201
1/20W
MF
NO_XNET_CONNECTION
R7225
12
200K
1%
201
1/20W
MF
NO_XNET_CONNECTION
R7215
12
33UF
20%
TANT-POLY
CASE-B3
16V
C72591
2
10%
50V
0.001UF
0402
X7R-CERM
C72931
2
0.001UF
0402
10%
50V
X7R-CERM
C72921
220%
2.2UF
25V
X6S-CERM
0402
C7299 1
2
20%
2.2UF
25V
X6S-CERM
0402
C7275 1
225VX6S-CERM
20%
2.2UF
0402
C7274 1
2
2.2UF
0402
X6S-CERM
25V
20%
C7273 1
225V
20%
X6S-CERM
0402
2.2UF
C7272 1
2
0402
20%
25V
2.2UF
X6S-CERM
C7271 1
2
0.001UF
0402
10%
X7R-CERM
50V
C72911
2
0.001UF
10%
0402
X7R-CERM
50V
C72901
2
33UF
16V
TANT-POLY
20%
CASE-B3
C72581
2
CASE-B3
TANT-POLY
16V
20%
33UF
CRITICAL
C72571
216VTANT-POLY
20%
33UF
CASE-B3
CRITICAL
C72561
2
33UF
CASE-B3
20%
16V
TANT-POLY
CRITICAL
C72551
2
33UF
20%
CASE-B3
16V
TANT-POLY
CRITICAL
C72541
2
CASE-B3
20%
16V
TANT-POLY
33UF
CRITICAL
C72531
2
20%
16V
CASE-B3
TANT-POLY
33UF
CRITICAL
C72521
216V
20%
CASE-B3
33UF
TANT-POLY
CRITICAL
C72511
2
PQFN-COMBO-THICKSTNCL
FDMF5808A
OMIT_TABLE
CRITICAL
U7220
4 32
5
2
6
27
3330
31
12 28
7
29
1
16
24
3
8
9
PQFN-COMBO-THICKSTNCL
FDMF5808A
OMIT_TABLE
CRITICAL
U7210
4 32
5
2
6
27
3330
31
12 28
7
29
1
16
24
3
8
9 5%1/10W
603
MF-LF
NOSTUFF
2.2
R72181
2
0.22UF
X7R
25V
0402
10%
C7219 1
2
X6S-CERM
0402
25V
20%
2.2UF
C72161
2
1/20W
1%
MF
201
200K
NO_XNET_CONNECTION
R7224
12
NO_XNET_CONNECTION
200K
1/20W
201
MF
1%
R72231
2
2.2
5%
NOSTUFF
MF-LF
1/10W
603
R72281
2
10%
25V
X7R
0.22UF
0402
C7229 1
2
5%
MF-LF
1/16W
402
0
R7229 1
2
MF-LF
402
5%
1
1/16W
R7226
1 2
2.2UF
25V
20%
0402
X6S-CERM
C7227 1
2
X6S-CERM
0402
25V
20%
2.2UF
C72261
2
SM
PLACE_NEAR=U7220.32:2MM
XW7220
12
402
5%
1/16W
MF-LF
1
R7216
1 2
SM
PLACE_NEAR=U7210.32:2MM
XW7210
12
20%
2.2UF
X6S-CERM
0402
25V
C7217 1
2
NO_XNET_CONNECTION
1/20W
1K
1%
MF
201
R7222 1
2
66 65 
65 
NO_XNET_CONNECTION
2.2
1%
1/20W
201
MF
R72211
2 66 65 
1%
NO_XNET_CONNECTION
200K
1/20W
MF
201
R7214
12
NO_XNET_CONNECTION
1/20W
MF
1%
201
2.2
R72111
2
0.00075
1%
MF
CRITICAL
1W
0612-1
R7210
12
34
CRITICAL
1%
0.00075
1W
MF
0612-1
R7220
1 2
3 4
66 51 
51 
51 
66 51 
402
5%
MF-LF
1/16W
0
R7219 1
2
65 
66 65 
65 
66 65 
0.001UF
X7R-CERM
10%
0402
50V
NOSTUFF
C72281
2
1% NO_XNET_CONNECTION
200K
201
1/20W
MF
R72131
2
NO_XNET_CONNECTION
1%
MF
1/20W
201
1K
R7212 1
2
66 65 
66 65 
65 
0.001UF
0402
50V
10%
NOSTUFF
X7R-CERM
C72181
2
66 51 
66 51 
66 51 
66 51 
66 51 
66 
66 51 
66 
66 
66 
66 
66 
CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION
 II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
THE POSESSOR AGREES TO THE FOLLOWING:
36
BRANCH
REVISION
DRAWING NUMBER SIZE
D
R
 IV ALL RIGHTS RESERVED
SHEET
PAGE TITLE
C
A
D
2 1
PAGE
NOTICE OF PROPRIETARY PROPERTY:
A
B
C
345678
D
B
8 7 5 4 2 1
PROPRIETARY PROPERTY OF APPLE INC.
THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NC
NC
NC
NC
NC
NC
NC
NC
NC
IN
IN
SW
VC
C
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AG
ND
AG
ND
PG
ND
PG
ND
PHASE
BOOT
PV
CC
NCNC
NC
OUT
OUT
OUT
OUT
OUT
SW
VC
C
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AG
ND
AG
ND
PG
ND
PG
ND
PHASE
BOOT
PV
CC
NC
SW
VC
C
SW
GL1
GL0
NC
GH
FCCM
PWM
VIN
VIN
AG
ND
AG
ND
PG
ND
PG
ND
PHASE
BOOT
PV
CC
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
NC
NC
IN
IN
NC
NC
OUT
OUT
OUT
3X 33UF B3
CPU VCCSA
2X 2.2UF 0402
F = 750kHz
Vout = 0.55 - 1.15V
ICCMAX = 11.1A
67 OF 121
MIN_LINE_WIDTH=0.2000