Circuit Cellar No 323 June 2017

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Q&A: Outside-the-Box Engineering Hands-Free, RPi-Based Monitor | 
The JEADI ARM Pt. 3 Automatic Control Pt. 2 | Hybrid Cooling 101 | 
Power Analysis Attacks | Vintage Programming Languages | 
LoRa Wireless Communication The Future of Embedded FPGAs 
COMMUNICATIONS
JUNE 2017 
ISSUE 323CIRCU
IT CELLAR | ISSU
E 323 | JU
NE 2017
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CIRCUIT CELLAR • JUNE 2017 #3232
Issue 323 June 2017 | ISSN 1528-0608
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THE TEAM
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EDITOR-IN-CHIEF
C. J. Abate 
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ADVERTISING COORDINATOR
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Game Changers: 3-D Printers, Embedded FPGAs, & More
If you’re interested in 3-D printing, you’ve come to the right place. This 
issue includes a “special focus” section dedicated to the subject. In an essay 
titled “A Dynamic Overview of Key 3-D Printing Features,” Alexandrea Mellen and 
Ashley Mellen cover the history of commercialized 3-D printing technology and 
also discuss the current state of the industry (p. 38). On page 42, we present 
interviews with two 3-D printing 
innovators—Nicolas Roux (Founder/
CEO of Zimple) and Jeff Moe (Founder/
CEO of Aleph Objects). 
The rest of the issue comprises 
articles on a variety of interesting 
subjects, from power analysis attacks 
to vintage programming languages. 
Below are short article previews.
Starting on page 12, Cyrus Moradi 
presents a Raspberry Pi-based 
autonomous monitoring system. You 
can apply Cyrus’s techniques to build a monitoring system for a variety of other 
applications.
In the third article in the series titled “JEADI ARM Project,” Abdul Rafay, 
Michael Smith, and Jason Long detail the required connections for the boards to 
add a JEADI output interface (p. 18). They also cover the project’s software.
Last month, George Novacek introduced the basic principles of automatic 
control, including a simple closed-loop control system, common control laws, 
and proportional system shortcomings. This time he tackles frequency domain 
analysis (p. 52). 
Turn to page 56 for Ayse Coskun’s thoughts on high-performance chips and 
the potential of hybrid cooling. She posits that that hybrid and heterogeneous 
cooling methods can substantially improve power efficiency.
System and data security are serious concerns for hardware engineers 
and embedded software developers alike. In “Breaking a Password with Power 
Analysis Attacks,” Colin O’Flynn addresses power analysis attacks and how they 
can be used to recover passwords (p. 60).
Like many of you, Robert Lacoste has a passion for retro electronics and 
technology. This month he offers an interesting overview of several vintage 
programming languages (p. 64). You might even want to use one for an upcoming 
project!
On page 70, Jeff Bachiochi kicks off a new series on long-range, low-power 
wireless communications. He introduces LoRa technology and describes its 
advantages over other options. 
Geoff Tate (CEO/Cofounder of Flex Logix Technologies) closes this issue with an 
essay on the future of embedded FPGAs (p. 80). He argues that you can’t afford 
to not take advantage of embedded FPGA technology.
C. J. Abate
Innovative 3-D printing technology 
COLUMNISTS 
Jeff Bachiochi (From the Bench), Ayse K. Coskun (Green Computing), 
Bob Japenga (Embedded in Thin Slices), Robert Lacoste (The Darker Side), 
Ed Nisley (Above the Ground Plane), George Novacek (The Consummate 
Engineer), and Colin O’Flynn (Embedded Systems Essentials)
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CIRCUIT CELLAR • JUNE 2017 #3234
CONTENTS JUNE 2017 • ISSUE 323
COMMUNICATIONS
 INDUSTRY & ENTERPRISE
06 : PRODUCT NEWS
11 : CLIENT PROFILE
Newhaven Display International, Inc. (Elgin, IL)
 FEATURES
12 : Hands-Free, RPi-Based Monitoring System
By Cyrus Moradi
How to build and program a handy monitoring system 
around a Raspberry Pi
18 : The JEADI ARM Project (Part 3) 
Connections and Software
By Abdul Rafay, Michael Smith, and Jason Long
The required connections and software to complete the 
JEADI ARM project
26 : FROM THE ARCHIVES
FPGA Embedded Microcontroller Environment 
By John Clayton
An in-depth look at a “slightly unusual” approach to 
designing with an FPGA
 CC COMMUNITY
32 : QUESTIONS & ANSWERS
Creativity Lives Here
An Interview with Jean Noel Lefebvre
By Wisse Hettinga
A chat with Jean Noel Lefebvre, who launched Ootsidebox 
at the YouFactory fab lab in Lyon, France
35 : EDITORS' PICKS
Communications 
Several of the Circuit Cellar team’s favorite articles on 
communications-related topicsRASPBERRY PI-BASED MONITORING SYSTEM
JEADI ARM PROJECT
Hard coded
test path
Activate
L
F
R
B
End
User commands
ARM
Microprocessor
LEFT
FORW
RIGHT
BACK
Car
interface
L
F
R
B
Virtual
Car
Direction
LEDs
4
JEADI
RC CAR
circuitcellar.com 5
CONTENTS
 3-D PRINTING
38 : A Dynamic Overview of Key 3-D Printing 
Features
By Ashley Mellen and Alexandrea Mellen
The six fundamental 3-D printing processes that 
dominate the modern market
42 : Advances in 3-D Printing and Related 
Technologies
Q&As with Industry Innovators 
Nicolas Roux (Founder/CEO of Zimple) and Jeff Moe 
(Founder/CEO of Aleph Objects) talk about innovation 
and the future of 3-D printing
48 : Resources for Cutting-Edge 3-D Printing and 
Related Technologies
 COLUMNS
52 : THE CONSUMMATE ENGINEER
Automatic Control (Part 2)
Frequency Domain Analysis
By George Novacek
A peek under the hood of control theory with a focus on 
frequency domain analysis
56 : GREEN COMPUTING
On the Potential of Hybrid Cooling 
By Ayse K. Coskun
How hybrid and heterogeneous cooling methods can 
substantially improve power efficiency
60 : EMBEDDED SYSTEMS ESSENTIALS
Breaking a Password with Power Analysis Attacks
By Colin O’Flynn
Use a power analysis attack to break a real system 
64 : THE DARKER SIDE
Vintage Programming Language
By Robert Lacoste
A few of the many old-school programming languages 
that you might find interesting (and perhaps useful) today
70 : FROM THE BENCH
Long-Range, Low-Power Wireless 
Communications (Part 1)
Trading Throughput for Distance
By Jeff Bachiochi
LoRa technology and its advantages over other options
 TESTS & CHALLENGES
76 : CROSSWORD
77 : TEST YOUR EQ
 TECH THE FUTURE
80 : The Future of Embedded FPGAs
Changing the Way Chips are Designed
By Geoff Tate
How embedded FPGA technology is revolutionizing 
chip design
VINTAGE PROGRAMMING LANGUAGES
@editor_cc
@circuitcellar circuitcellar
EXCITING ADVANCES IN 3-D PRINTING TECHNOLOGY
CIRCUIT CELLAR • JUNE 2017 #3236
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Radar Module for Makers
OmniPreSense Corp.’s recently unveiled radar module 
is capable of detecting objects 5 to 10 m away and giving 
electronic systems enhanced information about the world 
around them. Intended for the “maker” community, the $169 
OPS241-A module is capable of making any Android phone 
supporting USB On-the-Go (OTG) into a radar gun.
The 53 mm × 59 mm OSP241-A short-range radar is capable 
of reporting motion, speed, and direction of objects detected 
in its wide field of view. You can plug it into a Raspberry 
Pi’s USB port to enable a variety of useful applications. An 
API provides direct control of the OPS241-A and allows for 
changes to reported units (e.g., meters/second and miles/
hour), transmitted power, and other settings. Compared to 
PIR or ultrasonic sensors, the OPS241-A provides increased 
range, a wider coverage area, and immunity to noise and 
light, while providing enhanced information about the 
detected object. 
Potential applications range from security motion 
detection to a radar gun. You can plug the OPS241-A directly 
into an Android phone or tablet running USB OTG and terminal 
program to turn them into a radar gun. When mounted on a 
drone, the OPS241-A can detect objects 5 to 10 m away for 
collision avoidance.
OmniPreSense Corp. | omnipresense.com
New MEMS Accelerometers for Industrial Condition Monitoring Apps
Analog Devices’s new ADXL1001 and ADXL1002 high-
frequency, low-noise MEMS accelerometers are designed 
for industrial condition-monitoring applications. The 
accelerometers deliver the high-resolution vibration 
measurements needed for the early detection of machine 
failure (e.g., bearing faults).
The ADXL1001 and ADXL1002’s benefits, features, and 
specs:
• Deliver ultra-low noise density over an extended 
bandwidth with high-g range.
• Available in two models with full-scale ranges of ±100 
g (ADXL1001) and ±50 g (ADXL1002).
• Typical noise density for the ADXL1002 is 25 μg/√Hz, 
with a sensitivity of 40 mV/g, and 30 μg/√Hz for 
ADXL1001 with sensitivity 20 mV/g.
• Operate on single voltage supply from 3. to 5.25 V
• Electrostatic self-test
• Over range indicator
• Rated for operation over a –40°C to 125°C temperature 
range.
The accelerometers cost $29.61 each in 1,000-unit 
quantities.
Analog Devices | www.analog.com
Essential new product announcements and industry-related news are 
posted regularly at CircuitCellar.com.
http://www.analog.com
www.omnipresense.com
www.circuitcellar.com
circuitcellar.com 7
IND
U
STRY &
 ENTERPRISE
PRODUCT NEWS
Fifth-Generation Quasi-Resonant Flyback Controller and Integrated Power IC
Infineon Technologies recently announced the fifth 
generation of its stand-alone quasi-resonant flyback controller 
and integrated power IC CoolSET family. This generation 
offers more efficiency, faster startup, and improved overall 
performance. The new ICs are especially designed for AC/DC 
switch mode power supplies in a wide variety of applications.
The latest 700- and 800-V CoolMOS P7 families are 
integrated with a fifth-generation controller in a single 
package. The cascode configuration for the high-voltage 
MOSFET in combination with the internal current regulator 
provides fast startup performance. Light load performance is 
optimized through an Active Burst Mode (ABM) with selectable 
entry/exit thresholds.
Furthermore, the device incorporates new algorithms that 
minimize the switching frequency spread between different 
line conditions. It also simplifies EMI filter design. Device 
protection includes input over-voltage protection, brown in/
out, pin short to ground, and over-temperature protection 
with hysteresis. All protection features are implemented with 
auto-restart to minimize any interruption to operation.
The complete fifth generation quasi-resonant controller 
and CoolSET product portfolio will be available starting in 
May 2017. The controller comes in an SMD package (DSO-8). 
The CoolSET comes in both SMD (DSO-12) and through-hole 
(DIP-7) packages.
Infineon Technologies | www.infineon.com
New Development Tool for Bluetooth 5
Nordic Semiconductor’s Bluetooth 5 developer solution for 
its nRF52840 SoC comprises the Nordic S140 v5.0 multi-role, 
concurrent protocol stack that brings Bluetooth 5’s long range 
and high throughput modes for immediate use to developers 
on the Nordic nRF52840 SoC. The Nordic nRF5 SDK offers 
application examples that implement this new long-range, 
high-throughput functionality.The existing Nordic nRF52832 
SoC is also complemented with a Bluetooth 5 protocol stack.
Bluetooth 5’s high throughput mode offers not only 
new use cases for wearables and other applications, but 
also significantly improves user experience with Bluetooth 
products. Time on air is reduced and thus leads to faster more 
robust communication as well as reduced 
overall power consumption. In addition, with 
2 Mbps, the prospect of audio over Bluetooth 
low energy is possible.
The new Preview Development Kit 
(nRF52840-PDK) is a versatile, single-board 
development tool for Bluetooth 5, Bluetooth 
low energy, ANT, 802.15.4m, and 2.4-GHz 
proprietary applications using the nRF52840 
SoC. The kit is hardware compatible with the 
Arduino Uno Revision 3 standard, making 
it possible to use third-party-compatible 
shields. An NFC antenna can be connected 
to enable NFC tag functionality. The kit gives 
access to all I/O and interfaces via connectors 
and has four LEDs and four buttons which are 
user-programmable.
Nordic Semiconductor | 
www.nordicsemi.com
http://www.infineon.com
http://www.nordicsemi.com
CIRCUIT CELLAR • JUNE 2017 #3238
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New Thermal Imaging Solution for Benchtop Electronics Testing
FLIR Systems recently launched the FLIR ETS320 thermal 
imaging solution for benchtop electronics testing. Well 
suited for testing and analyzing the thermal characteristics 
of electronic components and printed circuit boards (PCBs), 
the battery-powered FLIR ETS320 comprises a high-
sensitivity thermal camera and an adjustable, hands-free 
table stand. With more than 76,000 points of temperature 
measurement, the rechargeable FLIR ETS320 enables you 
to monitor power consumption, detect hot spots, 
and identify potential points of failure during 
product development. The highly accurate camera 
can visualize small temperature differences so 
you can evaluate thermal performance, ensure 
environmental compatibility, and troubleshoot 
problems.
The FLIR ETS320 ships fully assembled and 
ready to connect to a PC running FLIR Tools 
software for detailed data analysis, recording, 
and reporting. The integrated test stand and 
sliding mount design offer flexibility when imaging 
electronic components of various sizes.
The FLIR ETS320 costs $2499 and is available 
through established FLIR distribution partners.
FLIR Systems | www.flir.com
Handy Four-Channel, 
High-Resolution 
Oscilloscope
The TiePie engineering recently 
introduced a new four-channel, high-
resolution, USB 3.0 oscilloscope. 
Featuring TiePie engineering’s 
SafeGround technology, the 
Handyscope HS6 DIFF is available in 
models with sampling rates from 50 
MSps up to 1 GSps. SafeGround enables 
you to use the oscilloscope inputs both 
as single ended and as differential. 
When SafeGround is active and you 
accidentally create a short circuit, 
SafeGround disconnects the ground of 
the input channel without damaging 
the oscilloscope or PC.
The Handyscope HS6 DIFF’s 
features, benefits, and specs:
• 1 GSps sampling and a flexible 
resolution of 8 to 16 bit
• Four input channels with up to 250-MHz analog 
bandwidth
• Highly accurate 1 ppm time base
• DC accuracy of 0.25 % and 0.1 % typical
• 200-MSps USB streaming data logger
• Up to 256 mega-sample memory per channel
• SureConnect connection test on all channels
• Spectrum analyzer with 32 million bins
TiePie | www.tiepie.com
Essential new product announcements and industry-related news are 
posted regularly at CircuitCellar.com.
http://www.flir.com
http://www.tiepie.com
www.circuitcellar.com
circuitcellar.com 9
IND
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 ENTERPRISE
PRODUCT NEWS
vSound Violin Digital Processor
Saelig Company recently introduce the Cambrionix 
ThunderSync16, which provides 16 USB2.0 ports and a 
Thunderbolt host connection capable of transfer speeds of up 
to 20 Gbps to allow large data transfer in the shortest possible 
time. For data syncing requirements, the Thunderbolt’s data 
transfer speed delivers a greatly increased data transfer 
rate between a host Thunderbolt connection and 16 attached 
devices than a USB2.0 connection.
The ThunderSync 16’s features, specs, and benefits:
• Speeds up situations needing large data transfer (e.g., 
video file uploading or operating system updates) 
when the data is required to be loaded in the fastest 
possible time.
• Supports universal, intelligent charging of USB ports 
at up to 2.4 A simultaneously.
• It can be daisy-chained via the dual Thunderbolt 
ports.
• Allows for the charging of multiple device types 
simultaneously (e.g., mobile phones, MP3 players, 
e-readers, etc.)
• Preprogrammed Very Intelligent Charging protocol 
ensures the correct charging profile is used for the 
specific product, maintaining battery performance 
and extending battery life
• Operates with the complementary Cambrionix 
LiveView app
• Supplied software displays the charging status in 
detail.
• An API is also provided for software automation 
scripting, essential for software QA and mobile phone 
remarketing companies.
The ThunderSync 16 is well suited for industrial, defense, 
security, software QA, and wearable camera applications 
requiring large-scale charging and data transfer. It is powered 
by an internal universal power supply, and is Intel Certified, 
CE Marked, UL Listed, and EMC FCC tested
Saelig Company | www.saelig.com
TeraFire Hard Cryptographic 
Microprocessor
Microsemi Corp. recently added Athena’s TeraFire 
cryptographic microprocessor to its new PolarFire field 
programmable gate array (FPGA) “S class” family. The 
TeraFire hard core provides Microsemi customers access to 
advanced security capabilities with high performance and low 
power consumption.
Features, benefits, and specs:
• Supports additional algorithms and key sizes commonly 
used in commercial Internet communications 
protocols such as TLS, IPSec, MACSec and KeySec.
• The Athena TeraFire EXP-5200B DPA-resistant 
cryptographic microprocessor capable of nearly 200 
MHz operation.
• Enables high-speed DPA-resistant cryptographic 
protocols at speeds well over 100 Mbps
• Integrated true random number generator for 
generating keys on-chip and for protecting 
cryptographic protocols
• The TeraFire crypto microprocessor is extensible with 
additional object code licensed from Athena or with 
accelerators attached via the PolarFire FPGA fabric
Microsemi’s PolarFire “S class” FPGAs with Athena’s 
TeraFire cryptographic microprocessor will be available in Q2 
2017. A soft version of the core is available for Microsemi’s 
SmartFusion2 SoC FPGAs.
Microsemi | www.microsemi.com
http://www.saelig.com
http://www.microsemi.com
CIRCUIT CELLAR • JUNE 2017 #32310
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PRODUCT NEWS
Radar Module for Makers
Linear Technology recently announced H-grade versions of 
the LT8304/-1 monolithic flyback regulators with guaranteed 
operation for junction temperatures as high as 150°C. 
By sampling the isolated output voltage directly from the 
primary-side flyback waveform, it requires no opto-coupler 
or third winding for regulation.
The LT8304H/-1’s features, specs, and benefits:
• VIN Range from 3 to 100 V
• Up to 24 W of output power
• LT8304-1 Capable of output voltages up to 1 kV
• Onboard 2-A, 150-V integrated DMOS power switch
• Off-the-shelf power transformers
• No opto-coupler or transformer third winding required 
for voltage feedback
• 116-µA Quiescent current
• Boundary mode operation
• Accurate input enable & undervoltage lockout with 
hysteresis
• Output diode temperature compensation
• H Grades: –40°C to 150°C operating junction 
temperature
Linear Technology | www.linear.com
Expanded Low-Power, Open-Frame AC-DC Power Supply Series
CUI recently added four low-power, open-frame AC-DC 
power supply series to its VOF product family. The VOF 6B, 
VOF 10B, VOF 15B, and VOF 20B series are 6-, 10-, 15-, and 
20-W power additions to CUI’s general-purpose AC-DC power 
supplyportfolio that currently ranges from 6 to 300 W. Well 
suited for space-constrained, low-power ITE, industrial, 
and consumer applications, the new models are housed in 
compact, board-mount packages measuring as small as 
1.913″ × 0.917″ × 0.638″ (48.6 × 23.3 × 16.2 mm). They 
feature industry-standard pinouts, 4-kVAC isolation, and no-
load power consumption less than 100 mW.
The 6-to-20-W modules feature a wide universal input 
voltage range of 85 to 264 VAC with single output voltages 
of 5, 9, 12, 15, 24, and 48 VDC, depending on the series. 
Operating temperatures at full load range from –25° to 
50°C, derating to 50% load at 70°C. All of the models carry 
UL/cUL and TUV 60950-1 safety certifications and meet EN 
55032 Class B and FCC Class B limits for radiated emissions. 
Protections for short circuit, over current, and over voltage 
come standard. The series also carry a minimum MTBF of 
300,000 h at 115 VAC at 25°C ambient, calculated per MIL 
HDBK 217F.
Prices for the VOF 6B, VOF 10B, VOF 15B, and VOF 20B 
series start at $7.57 per unit in 100-piece quantities.
CUI, Inc. | www.cui.com
Essential new product announcements and industry-related news are 
posted regularly at CircuitCellar.com.
http://www.linear.com
http://www.cui.com
www.circuitcellar.com
circuitcellar.com 11
CLIENT PROFILE
IND
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 ENTERPRISE
Newhaven Display 
International, Inc.
Elgin, IL, USA
www.newhavendisplay.com
About Newhaven Display
Since 2001, Newhaven Display has been providing the 
worldwide marketplace with cost-effective, high-quality dis-
plays, including OLEDs, LCDs, and VFDs. In addition to its vast 
standard part offerings, Newhaven Display develops custom 
display designs for all industries. It prides itself on first-rate 
customer support, design services, and development assis-
tance.
At its Elgin, IL headquarters, Newhaven Display performs 
product quality inspections, stock, design, develop, manu-
facture, and assemble our display products. All of its part-
nered production centers are state-of-the-art facilities with 
extensive experience in display development. Newhaven Dis-
play works closely with its production centers to ensure its 
products meet all requirements of proper design and quality 
standards.
Why Should CC Readers Be Interested?
Newhaven Display offers a variety of high-quality TFT dis-
plays. Ranging from 1.8” to 7.0”, these TFTs come ready with 
the option of capacitive or resistive touch and are available 
as standard, Premium (MVA), or Sunlight Readable displays. 
When wider viewing areas 
are needed, the Premium 
TFTs have up to 75° view 
from all sides, whereas the 
Sunlight Readable TFTs are 
the ideal option for outdoor 
applications.
To help with developing 
with these TFTs, Newhaven 
Display also has plug-and-play BeagleBone and Arduino de-
velopment boards that make prototyping a breeze. Developed 
and designed by Newhaven Display’s engineers in Elgin, IL, 
these boards are perfect for any level of engineer looking to 
get started with TFT development. For high-quality, brilliant 
TFT displays and development assistance, turn to Newhaven 
Display.
Circuit Cellar prides itself on presenting readers with information 
about innovative companies, organizations, products, and servi-
ces relating to embedded technologies. This space is where Circuit 
Cellar enables clients to present readers with useful information, 
special deals, and more.
http://www.newhavendisplay.com
www.circuitcellar.com/subscription
CIRCUIT CELLAR • JUNE 2017 #32312
FE
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Cyrus developed a Raspberry Pi-based, 
autonomous monitoring system. After 
presenting the hardware and the code, he covers 
the system’s performance and areas for development.
By Cyrus Moradi
Hands-Free, RPi-Based 
Monitoring System
Maintaining a home garden can provide you with inexpensive fresh herbs and 
vegetables that might not be readily available 
in grocery stores. But for some of you, 
watering a home garden or providing it with 
adequate sunlight may be difficult or hard 
to remember. Implementing an automated 
monitoring system can help reduce gardening 
errors, schedule watering, and improve 
resource allocation techniques.
I recently built a Raspberry Pi-based 
system for monitoring my garden’s growth 
and well-being (see Photo 1). Specifically, 
the Raspberry Pi controls both watering 
and lighting. I specify the time of day and 
frequency at which water should be pumped 
to plants based on the soil’s moisture. The 
system’s photo sensor informs the Raspberry 
Pi to illuminate the plants with high-powered 
LEDs when light is required. Naturally, I can 
adjust the lighting and moisture sensitivity 
settings according to my preferences. 
The system’s Raspberry Pi notifies me of 
important changes via SMS texting.
HARDWARE OVERVIEW
The system’s hardware comprises two 
subsystems: lighting and watering (see 
Figure 1 and Figure 2). Each subsystem 
has its own sensing mechanism. Three 3-W 
LEDs serve as the system’s primary light 
source. The white LEDs—which I chose for 
their natural-looking white color—possess a 
rather strong intensity for their reasonable 
price. The wavelength temperature of the 
white LEDs ran between 6000 and 6500 
K at roughly 500 nm, whereas the sun’s 
temperature resides around 6000 K and 483 
nm.[1] The LEDs consumed 3 W of power. As 
you can likely tell, the LEDs consumed a lot of 
power and dissipated even more heat. Adding 
a voltage divider with a potentiometer would 
remedy the high-power consumption, help 
reduce heat dissipated, and allow the user to 
control brightness settings on the LEDs.
We wanted the smart garden’s artificial 
lighting to closely resemble natural sun light; 
this way, our plants. Although our prototype 
used a constant LED intensity, the LED’s 
intensities can be changed with a voltage 
divider and accompanying potentiometer. A 
switched mode power supply (SMPS) can help 
drastically reduce power consumption by the 
relay module while running the relay at the 
relay’s “hold voltage”, the lowest possible 
voltage that the relay still switches. Another 
circuitcellar.com 13
FEATU
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option is to throw in a series resistor to reduce 
power supplied (and ultimately dissipated) to 
the relay board. 
Number 8 screws were used in the 
prototype as heatsinks, as the LEDs produce 
a huge amount of excess heat. An aluminum 
heatsink would greatly improve the current 
design, avoiding any possibility of a garden 
fire. The LEDs were controlled by relay 
switches. Our lights were mounted on tall but 
skinny metal legs with hot glue. These “legs” 
stood above the plant, but with the wiring 
safely distant from the water dispenser and 
plant pot to avoid any undesirable catastrophe.
The light sensor consists primarily of a 
photo resistor. As the light intensity grows, 
the photo resistor’s value drops causing the 
Raspberry Pi to read a change in state from 
FIGURE 1
The integrated hardware for the entire 
garden system
PHOTO 1
The first smart garden prototype
CIRCUIT CELLAR • JUNE 2017 #32314
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low to high. (If the GPIO is set up to active high, 
pull-down.) As expected, the photo sensor 
responded very well to changes in lighting. In 
very dim to dark settings, the sensor did not 
conduct, whereas in less dim to light settings, 
the sensor outputted a high signal. However, 
one could easily insert a voltage divider or 
low-gain amplifier to either lower or raise 
the turn-on threshold. This alters the default 
sensitivity with a hardware hack. As before, in 
our case, the lower resistor value was chosen 
in order to match the input voltage levels of the 
Raspberry Pi. This was then calibrated using 
different light intensities. Our field testing 
found that the light sensor would turn off in a 
dark setting (e.g., covering the photo resistor 
with my hand or turning the light switch off) 
and turned on in less dim to lighter settings 
(e.g., when I held my hand roughly a foot over 
the sensor in a well-litroom). Knowing the 
analog value of the photo sensor is valuable 
for gardeners wanting extra sensitivity for 
their plants. Although the Raspberry Pi’s 
GPIO pins operate only in the digital realm, 
it is possible to use an RC charging circuit to 
find the timing constant and, thus, a rough 
estimate of the analog voltage.
Just as a plant can have too little water, 
it can also have too much water. In order 
to provide water to the plants we needed 
a system by which the Raspberry Pi could 
electronically control the water flow. We 
originally considered using a plastic solenoid 
valve that used stored gravitational potential 
energy in order to dispense the water. This 
system required over 7’ of head pressure 
for the water to clear the valve. We realized 
that this was unrealistic for a home garden 
and looked for a more suitable option. We 
decided to use a CPU water cooling pump to 
inject the water into the plant pot. The relay 
switch circuit used for lighting also controls 
the switching mechanism for the water 
dispensing.
Initially, we planned on creating soil 
moisture sensors using graphite pencils and 
an analog-to-digital converter. However, 
we found that it was easier and relatively 
inexpensive (not to mention more professional 
looking) to buy soil moisture sensors with 
built-in Schmitt triggers. The sensors had 
two prongs with plastic encasings that we 
simply inserted into the soil. These made 
the moisture sensor calibration very easy. 
The sensor also proved to be reliable in our 
prototype. We didn’t attempt any calibration 
methods as the sensors clearly distinguished 
between dry and damp or wet soil. 
One problem users might have is that 
the sensors conducted in both moderately 
damp or very wet soil equally well. For plants 
needing lots of water, this may be a problem. 
This issue can be remedied by adding multiple 
moisture sensors with the potentiometers on 
the accompanying Schmitt triggers calibrated 
to trigger at different moisture levels. This 
way the user can specify which setting best 
matches the desired moisture values of the 
plant by simply selecting which GPIO pin to 
use. Otherwise, the user can manually alter 
the potentiometer setting using a single 
sensor.
SOFTWARE OVERVIEW
The Raspberry Pi garden application 
ran Raspbian 4.10.1, unchanged, in a Linux 
FIGURE 2
Take a look at the Sain Smart four-
channel relay module. I use only two 
channels to control the three LED 
lighting and water pump. Note the 
switches on the right half of the relay 
module. Channel/Relay 1 is used to 
control the lighting, whereas Channel/
Relay 2 controls the pump.
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CIRCUIT CELLAR • JUNE 2017 #32316
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environment. I used Python 3 and its basic 
libraries such as GPIO and OS. I edited the 
code using gedit and nano, but any editor 
works. Two Python scripts light.py and 
moist.py control the lighting and watering 
operations while the bash script, garden.sh, 
allows the user to run the garden application 
easily. The software used the Twilio API and 
various modules that I’ll cover below.
We initially wanted to use callbacks to 
control the LED lighting and event detection to 
toggle the LEDs. However, because our design 
did not require any real-time time constraints, 
we chose to implement a program that polled 
our sensors. Specifically, the light sensor was 
polled if the following conditions were met: 
the time of day had to be between 8 AM and 
7 PM to mimic real-world daylight hours. The 
time settings used the “datetime” Python 
module that uses Network Time Protocol 
(NTP) queries from global NTP servers for 
accurate time readings. The time was set 
to the current Eastern Standard Time. If 
the gardener does not have network access 
or desires a clock that runs independent of 
the Raspberry Pi’s power state, a stand-
alone, real-time clock module like the Maxim 
Integrated DS1307 would be a great time 
source. Note that a network connection is 
needed to run the Twilio SMS notifications. 
Although we only used hour, the user may set 
conditions with minute or second for more 
precise specifications using the datetime 
module. The start and end times along with 
light on/off times can be set by parameters 
defined in the bash script, garden.sh. The 
user simply inserts the parameters belonging 
to their respective python script that wish 
to change within garden.sh. This saves the 
user time from digging into the code and 
modifying variables.
The watering system pumps water from 
the reservoir into the plant pot for a set period 
of time during daylight hours. While we chose 
daylight hours during our initial testing, we 
recognize that watering during nighttime 
hours would reduce evaporation of water. 
Regardless, the time conditions show that it 
is possible to constrain run time to specific 
times of day. The current configuration in the 
bash script has a pump run time of 5 seconds. 
It is important to be aware of the pump’s 
high pump rate (4L/min). A long run time can 
cause your garden to become a swamp! Like 
lighting, the begin/end time and running time 
settings can be altered to best fit the specific 
plant’s needs within the bash script. 
The Raspberry Pi updates the user on its 
current status through SMS texting. Twilio 
offers a free and easy-to-use API that allows 
the Raspberry Pi to send texts to the user’s 
cell phone, notifying whether the lighting was 
on or the pump running. 
We began by creating a Twilio account, 
following a guide by a hacker who used a 
Raspberry Pi to send him SMS texts from his 
fish.[2] It involves the standard registration 
process such as giving your email, etc. After 
choosing our favorite area code for your 
Raspberry Pi, we received a phone number, 
account ID (for the REST API), and AuthToken. 
Next, Twilio was installed onto the 
Raspberry Pi:
sudo pip install twilio
Now, Twilio can be run on any Python 
program on the Raspberry Pi. We imported 
the TwilioRestClient library to our programs 
light.py and moist.py:
from twilio.rest import TwilioRestClient
 
circuitcellar.com/ccmaterials
REFERENCES
[1] T. Ahmed, “Wavelength 
of the Sun’s Peak Radiation 
Output,” in G. Elert, The 
Physics Factbook, 2002, 
http://hypertextbook.com/
facts/2002/TahirAhmed.
shtml.
[2] L. Orsini, “My Fish Just 
Sent Me A Text Message,” 
ReadWrite.com, 2014, http://
readwrite.com/2014/04/23/
raspberry-pi-connected-
home-fish-text-message-
twilio/.
RESOURCES
Adafruit Industries, Rapberry 
Pi Model 2,” 2014, https://
cdn-shop.adafruit.com/pdfs/
raspberrypi2modelb.pdf.
T. Ahmed, “Wavelength of the 
Sun’s Peak Radiation Output,” 
in G. Elert, The Physics 
Factbook, 2002, http://
hypertextbook.com/facts/2002/TahirAhmed.
shtml.
Lady Ada, “Adding a Real Time Clock to a 
Raspberry Pi,” Adafruit Industries, 2016, 
https://cdn-learn.adafruit.com/downloads/pdf/
adding-a-real-time-clock-to-raspberry-pi.pdf.
Python Software Foundation, “Datetime—Basic 
Date and Time Types,” https://docs.python.
org/2/library/datetime.html.
Stevenvh, “What Are Some Ways to Use 
Relays More Efficiently?,” StackExchange.com, 
2012, https://electronics.stackexchange.com/
questions/34561/what-are-some-ways-to-use-
relays-more-efficiently.
SOURCES
Raspberry Pi and Raspbian OS
Raspberry Pi Foundation | www.raspberrypi.orgFour-channel 5-V relay module
Sain Smart | http://www.sainsmart.com
DC30A DC5V/DC12V Brushless DC water 
pump
Shenzhen Zhongke Century Technology Co. | 
www.minibrushlessdcpump.com
SUNKEE Soil hygrometer detection module
Watt Converter | www.wattconverter.com/
detail/B00AYCNEKW
Programmable SMS API
Twilio | www.twilio.com/sms
http://www.raspberrypi.org
http://www.sainsmart.com
http://www.minibrushlessdcpump.com
http://www.wattconverter.com/
http://www.twilio.com/sms
www.circuitcellar.com/ccmaterials
http://hypertextbook.com/facts/2002/TahirAhmed. shtml
http://readwrite.com/2014/04/23/raspberry-pi-connected-home-fish-text-message-twilio
https://cdn-shop.adafruit.com/pdfs/raspberrypi2modelb.pdf
http://hypertextbook.com/facts/2002/TahirAhmed. shtml
https://cdn-learn.adafruit.com/downloads/pdf/adding-a-real-time-clock-to-raspberry-pi.pdf
https://docs.python.org/2/library/datetime.html
https://electronics.stackexchange.com/questions/34561/what-are-some-ways-to-use-relays-more-efficiently
circuitcellar.com 17
FEATU
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ABOUT THE AUTHOR 
Cyrus Moradi earned a BS in Electrical and Computer Engineering at Cornell 
University. He is a software engineer at MITRE Corp. in Bedford, MA.
The Twilio API client is then defined:
client = TwilioRestClient(account = 
accountID, token = tokenID)
accountID and tokenID are the account 
number and authorization identification 
supplied on your Twilio account from earlier.
To send an SMS message to your phone, 
I inserted:
client.messages.create(to = user_num, 
from_ = RPI_num, body = ‘msg’)
user_num is the gardener’s cellphone 
number (including region [+1] and area code). 
RPI_num is the Raspberry Pi’s number supplied 
by Twilio, and ‘msg’ is the notification method 
sent. This means that as long as the Raspberry 
Pi has a Twilio account, the user can update 
the code with the desired receiving phone’s 
number. These arguments are passed in 
the shell script, garden.sh. The arguments 
passed include: the user’s phone number; 
the Raspberry Pi’s number; Twilio account 
and token IDs; and separate run times and 
begin/end times for the pump and LEDs. In 
the future, I plan on adding a message option 
for both python scripts, light.py and moist.py.
RESULTS & FUTURE WORK
The current home garden prototype meets 
expectations without any issue. I thoroughly 
tested the design to confirm that the basic 
tasks operations worked (e.g., lighting and 
water dispensing). Next, we confirmed that 
the sensing hardware functioned normally 
followed ensuring that program did not violate 
any of the timing conditions. The Twilio SMS 
texting program worked well; it delivered 
results as expected. 
I envision more features in future 
iterations. I initially planned to control water 
supply through SMS text reception; however, 
I learned that port forwarding (using the local 
flask server on the Internet) was not permitted 
by the Cornell University network. Otherwise, 
a user could use the platform ngrok to run the 
flask server from his or her network. 
A difficulty I encountered was an issue 
with our original RT Preempt kernel patch of 
Raspbian. An error developed (possibly self-
made by changing a conf. file) that prevented 
me from accessing the Internet. Using the 
base version of Raspbian 4.10.1, I was able 
to achieve normal functionality. Besides these 
errors, the project worked well from the 
software side. Notification updates from the 
Raspberry Pi arrived accurately and timely. 
The time of day conditions from the date time 
library were correct.
The relay board adequately powered 
both the LED lights and the water pump. 
The photosensor was able to differentiate 
darkness from lit environments, but the 
moisture sensor was unable to differentiate 
from soil that was heavily saturated and 
slightly saturated water. This ended up not 
being a huge issue, but the gardener using 
this smart garden prototype should be wary 
that incorrect water doses can harm a plant.
My first autonomous indoor garden was a 
success! While I could not send texts from my 
mobile phone to the Raspberry Pi, the other 
systems in the project functioned as intended. 
The water pump moved a more than sufficient 
amount of water to the plant and the soil 
sensor was able to determine when the plant 
was watered adequately. The photosensor was 
able to determine if the plant was receiving 
sunlight and the lights were able to illuminate 
the plant container. The lights produced too 
much waste heat, which caused the heatsink 
adhesive to burn off which may be avoided 
if thermal adhesive is used. The system was 
also able to inform the user when subsystems 
were being activated. I found this to be very 
resourceful for the user. A user can know how 
frequently the plant is actually being watered 
as well as the amount of light the plant is 
actually receiving as opposed to its intended 
amount. Another improvement to the system 
could be the hosting of a website on the user’s 
local network that indicates water and light 
levels through time. Also, the use of an analog-
to-digital converter to get better information 
about the current light and moisture levels 
would be helpful. Finally, a compact camera 
that would be used for updating the user on 
plant growth progress through SMS texting or 
email would be a useful addition.
I am satisfied with the prototype’s results. 
You could grow food year round in your home 
with tis sort of system. You can capitalize on 
the use of efficient scheduling and resource 
allocation techniques, which make it an 
affordable and effective method for low-
volume farming. I hope to inspire a new 
generation of farmers that don’t have to 
break a sweat as long as the AC is running. 
Author’s Note: Alex Jaus was my partner 
for this project. He graduated from Cornell 
University in 2016 and currently works as a 
software engineer at Green Hills Software 
in Santa Barbara, CA.
CIRCUIT CELLAR • JUNE 2017 #32318
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S In the final article of this series, Abul, 
Michael, and Jason cover the required 
connections and configuration for the 
boards to add a JEADI output interface 
to provide four new output lines to drive 
an actual RC car through its remote 
controller. They also cover the software-
related aspects of the project.
By Abdul Rafay, Michael Smith, and 
Jason Long
The JEADI ARM Project (Part 3)
This series of introductory articles on embedded systems development discusses 
the essential details of the JEADI-ARM 
project. Our goal was to provide Just Enough 
Additional Development Interfaces to extend 
the capabilities of low-cost ARM development 
boards. As detailed in the first two articles 
in this series, we want to have sufficient 
additional hardware interfaces to control a 
radio-controlled (RC) car through user button 
input and to configure outputs to send signals 
to activate a remote controller (see Figure 1). 
In Part 1, we discussed setting up the 
development environment and tested it by 
developing the traditional “Hello World” 
program on two demonstration boards, 
an STMicroelectronics STM32F4 Cortex-4 
Discovery and an EiE Cortex-3 Razor. We 
developed a coding style that allowed us to 
hide how different ARM cores are interfaced 
to the on-board buttons and LED peripherals 
that the manufacturers had made available on 
the different evaluation boards. We provided 
code for a virtual car interface where the car 
directions LEFT, RIGHT, FORWard, and BACK 
were shown using the on-board LEDs in Part 
2. The car path could be controlled by a fixed 
path stored in an array. We then developed 
JEADI input interfaces (red boxes in Photo 1 
and Photo 2) to extend the input capabilities 
of each board. This allowed us to control the 
virtual car through a custom path controlled 
by commands from a six-button user interface. 
In this article, we’ll discuss the required 
connections and configuration for the two 
boards to add a JEADI output interface to 
provide four new output lines to drive an 
actual RCcar through its remote controller. 
In the next section, we’ll show how to drive 
the actual RC car by modifying the main.c 
code from Part 2 and I/O functions for the 
OUTPUT_RC output configuration of the two 
boards. We’ll finish by discussing the circuit 
modifications needed to make the remote 
Connections and Software
Hard coded
test path
Activate
L
F
R
B
End
User commands
ARM
Microprocessor
LEFT
FORW
RIGHT
BACK
Car
interface
L
F
R
B
Virtual
Car
Direction
LEDs
4
JEADI
RC CARFIGURE 1
Here’s an overview of the JEADI 
project, which provides Just Enough 
Additional Development Interfaces 
to allow a low-cost ARM board to 
manipulate an RC car.
circuitcellar.com 19
FEATU
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controller interface with the boards. 
If you don’t want to write all the code by 
hand, you can refer to the project’s github 
download links listed at the end of article 
(STM32F4_RC0 and ATSAM3U_RC0 for the STM 
and Razor boards, respectively).
JEADI FOR RC—SOFTWARE
We can remove all the new RC car code 
from Listing 1 by setting the define OUTPUT_RC 
to 0. This gives us back the same functionality 
as in Part 2. We first initialize the LED and 
button interfaces before driving the virtual 
car interface using DriveCar() with directional 
commands either derived from a predefined 
array in DriveCar_FixedPath() or by button 
commands from our new JEADI input interface 
in DriveCar_ButtonPath().
Depending on the input configuration 
selected, commands are read either from an 
array using the ReadFixedPath() or by reading 
the user input buttons until an END_COMMAND 
or End button press is intercepted. If the 
BUTTON_PATH define is 1, the user input pattern 
is converted to the virtual car LED interface 
bit pattern using the ProcessInputVirtual() 
function. The command is echoed to the output 
interface using the DriveCar() when the 
Activate button is pressed and then released. 
Having the echo occurring on the falling edge 
of the Activate signal avoids multiple command 
being sent with a single press.
Setting the OUTPUT_RC define to 1 brings 
in the new code to control the RC car. The 
InitRCOutput() function is used for initializing 
the output RC interface. For debugging 
purposes, the direction commands from 
the fixed array or JEADI button interface 
are sent to the virtual car LED interface, 
DriveCar(), before activating the real car using 
DriverCarRC(). We use the ProcessInputRC() 
function to take into account that the signals 
must be sent to different I/O pins to control the 
virtual and real car interfaces. 
JEADI FOR RC—FIRMWARE
Using the same approach as we took in 
Part 2, we have defined a series of macros to 
allow us to use equivalent code to control the 
JEADI interface on the Discovery board (see 
Listing 2) and the EiE board (see Listing 3). 
The use of these processor-dependent macros 
means that we can use a common hardware 
interface for both boards in Listing 4. 
To take account of the different processor 
and board layouts, we made the JEADI output 
interface from the breakout pins E8, E10, E12, 
and E14 on the Discovery board (see Photo 3) 
and from pins A9, A10, A15, and A16, which 
come out of the extender board pins on the 
Razor board (see Photo 4). ProcessInputRC(), 
DriveCarRC(), and WriteCommandRC() in 
PHOTO 2
Portions of the EiE Razor board with an additional input interface (a) and on-board LEDs (b) and buttons 
marked
PHOTO 1
This is the STM32F407 Discovery with additional input interface and on-board LEDs and button marked.
a)
b)
CIRCUIT CELLAR • JUNE 2017 #32320
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LISTING 2
STM32F4 “IO_functions_RCCAR.h” header entries for the RC car project
//Common main.c for the RC car project
#include <stdio.h>
#include “IO_functions_RCCAR.h”
#define FIXED_PATH 1
#define BUTTON_PATH 0
#define OUTPUT_RC 1 // ** NEW CODE
int main(void){
 //Initialize IO Interfaces
 InitLED();
 InitButtons();
#if OUTPUT_RC //** NEW CODE 
 InitRCOutput(); 
#endif
#if FIXED_PATH
 DriveCar_FixedPath(); 
#elif BUTTON_PATH
 DriveCar_ButtonPath();
#endif
}
void DriveCar_FixedPath(void){
 //Get command
 int command = ReadFixedPath();
 while(command != END_COMMAND){
 if(ReadActivateButton()){
 //Wait for button release
 while(ReadActivateButton() != 0); 
 //Drive virtual car
 DriveCar(command); 
#if OUTPUT_RC // ** NEW CODE
 //Convert direction for RC interface
 int commandRC 
 = ProcessInputRC(command);
 //Drive RC car
 DriveCarRC(commandRC); 
#endif
 //Get next command
 command = ReadFixedPath();
 }
 WaitSometime(SAMPLE_DELAY);
 }
}
void DriveCar_ButtonPath(void){
 while(!ReadEndButton()){
 //Convert button press into a command
 int button = ReadDirectionButtons();
 command = ProcessInput(button)
 if(ReadActivateButton()){
 //Wait for button release
 while(ReadActivateButton() != 0); 
 //Drive virtual car
 DriveCarVirtual(command); 
#if OUTPUT_RC // ** NEW CODE
 //Convert direction for RC interface
 int commandRC 
 = ProcessInputRC(command);
 //Drive RC car
 DriveCarRC(commandRC); 
#endif
 }
 WaitSometime(SAMPLE_DELAY);
 }
}
LISTING 1
Common main.c code with functionality to drive the car through the RC output interface
#ifndef IO_FUNCTION_RCCAR_H
#define IO_FUNCTIONS_RCCAR_H
#include “IO_functions_BUTTON_PATH.h”
#define RC_PORT E
#define OUTPUT1_PIN 8
#define OUTPUT2_PIN 10
#define OUTPUT3_PIN 12
#define OUTPUT4_PIN 14
#define RC_LEFT (1<<OUTPUT3_PIN)
#define RC_FORW (1<<OUTPUT2_PIN)
#define RC_RIGHT (1<<OUTPUT4_PIN)
#define RC_BACK (1<<OUTPUT1_PIN)
#define RC_COAST 0x0
#define ENABLE_OPENDRAIN(PORT,PIN)\
 ENABLE_OPENDRAIN_FME(PORT,PIN)
#define ENABLE_OPENDRAIN_FME(PORT,PIN)\
 GPIO##PORT->OTYPER |= (1<<PIN) 
#endif
LISTING 3
ATSAM3U “IO_functions_RCCAR.h” header entries for the RC car project
#ifndef IO_FUNCTION_RCCAR_H
#define IO_FUNCTIONS_RCCAR_H
#include “IO_functions_BUTTON_PATH.h”
#define RC_PORT A
#define OUTPUT1_PIN 9
#define OUTPUT2_PIN 10
#define OUTPUT3_PIN 16
#define OUTPUT4_PIN 15
#define RC_LEFT (1<<OUTPUT3_PIN)
#define RC_FORW (1<<OUTPUT2_PIN)
#define RC_RIGHT (1<<OUTPUT4_PIN)
#define RC_BACK (1<<OUTPUT1_PIN)
#define RC_COAST 0x0
#define ENABLE_OPENDRAIN(PORT,PIN)\ 
 ENABLE_OPENDRAIN_FME(PORT,PIN)
#define ENABLE_OPENDRAIN_FME(PORT,PIN)\
 AT91C_BASE_PIO##PORT->PIO_MDER |= (1<<PIN)
#endif
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From the deserts of Africa to the Canadian tundra,
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places on Earth.
The TS-7680 is designed to provide extreme 
performance for applications which demand
high reliability, fast boot-up/startup, and
connectivity at low cost and low power.
Powered by a 454 MHz ARM CPU the TS-7680
offers a great balance between industrial
features and high end capabilities. 
BUILT FOR EXTREMES
Single Board Computer
Qty 100
Low Power Industrial 
Single Board Computer with 
WiFi and Bluetooth
$159
TS-7680
From the deserts of Africa to the Canadian tundra,
no terrain is too demanding for our boards. 
Deployed in �eet management, pipeline monitoring,
and industrial controls, our single board computers
are working in some of the most demanding
places on Earth.
The TS-7680 is designed to provide extreme 
performance for applications which demand
high reliability, fast boot-up/startup, and
connectivity at low cost and low power.
Powered by a 454 MHz ARM CPU the TS-7680
offers a great balance between industrial
features and high end capabilities. 
www.embeddedarm.com
CIRCUIT CELLAR • JUNE2017 #32322
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Listing 4 have a lot in common with ProcessInput(), 
DriveCar(), and WriteCommand(), which we developed in Part 
2 to control the virtual car. ProcessInputRC() rearranges the 
bits in the button command to the required configuration 
to drive the Discovery board’s PORT-E and the EiE board’s 
PORT-A. Function DriveCarRC() outputs this bit pattern to the 
required port using WriteCommandRC() and it inserts a wait 
to allow the car to physically respond before turning off the 
drive signals. The new initialization routine, InitRCOutput(), 
makes use of the ENABLEPORT() and SETPINOUTPUT() macros 
from Parts 1 and 2 to perform most of the configuration of 
JEADI output interface pins to control the RC car. We’ll explain 
the new macro, ENABLE_OPENDRAIN(), in more detail in the 
next section.
OUTPUT INTERFACE DETAILS
Let’s look at some details of the hardware-specific include 
files for each board (see Listing 3 and Listing 4). Port and pin 
definitions are followed by the output bit patterns to drive the 
RC interface. 
Note that the output pin signals are written in the following 
form:
OUTPUTREGISTER(RC_PORT) = ~command;
The use of the inversion operator ~ is required due to active 
LISTING 4
Common I/O functions to drive the virtual car interface using a fixed test pattern in 
the RC car project
//Common IO_functions.c for the RC car project
#include “IO_functions_RCCAR.h”
void InitRCOutput(void){
 //Enable RC Port pins
 ENABLEPORT(RC_PORT,OUTPUT1_PIN);
 ENABLEPORT(RC_PORT,OUTPUT2_PIN);
 ENABLEPORT(RC_PORT,OUTPUT3_PIN);
 ENABLEPORT(RC_PORT,OUTPUT4_PIN);
 //Set pin mode to output
 SETPINOUTPUT(RC_PORT,OUTPUT1_PIN);
 SETPINOUTPUT(RC_PORT,OUTPUT2_PIN);
 SETPINOUTPUT(RC_PORT,OUTPUT3_PIN);
 SETPINOUTPUT(RC_PORT,OUTPUT4_PIN);
 //Enable open-drain
 ENABLE_OPENDRAIN(RC_PORT,OUTPUT1_PIN);
 ENABLE_OPENDRAIN(RC_PORT,OUTPUT2_PIN);
 ENABLE_OPENDRAIN(RC_PORT,OUTPUT3_PIN);
 ENABLE_OPENDRAIN(RC_PORT,OUTPUT4_PIN);
 //Pull output high (off) to stop
 // Car starting incorrectly on power up
 WriteCommandRC(RC_COAST);
}
unsigned int ProcessInputRC( 
 unsigned int command){ 
 unsigned int controlRC = 0;
 switch(command & (RIGHT | LEFT)){
 case RIGHT:
 controlRC = RC_RIGHT; break;
 case LEFT: 
 controlRC = RC_LEFT; break; 
 }
 switch(command & (FORW | BACK)){
 case FORW:
 return controlRC | RC_FORW;
 case BACK:
 return controlRC | RC_BACK;
 default:
 return controlRC | RC_COAST; 
 }
}
void DriveCarRC(unsigned int command){
 WriteCommandRC(command);
 WaitSometime(DELAY);
 WriteCommandRC(RC_COAST);
}
void WriteCommandRC(unsigned int command){
 OUTPUTREGISTER(RC_PORT) = ~command;
}
PHOTO 3
Here is the STM32F407 Discovery with additional connections for the input (Part 2) and 
output interfaces. 
circuitcellar.com 23
FEATU
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low nature of the output. This means that a 
very important part of the InitRCOutput() 
initialization function is the line 
OUTPUTREGISTER(RC_PORT) = RC_COAST. This 
sets the JEADI output interface to RC_COAST to 
deactivate the signals to the RC car at start-
up. If this is not done, the car will be sent 
commands to simultaneously go FORWard, 
BACK, LEFT, and RIGHT, which is probably 
not good for the controller or the car! This 
also means that the connected controller 
must be powered up only after powering up 
the evaluation board. The ENABLE_OPENDRAIN 
macro writes the STM32F4’s Output Type 
Register, GPIOx_OTYPER, and ATSAM3U’s 
Multi-driver Enable Register, PIO_MDER, to 
enable open drain outputs. 
ARM BOARD HARDWARE 
CONFIGURATION 
In Part 2, we gave guidelines to extend 
the input interface for user commands. In 
this section, we’ll describe how to extend 
the boards’ I/O capabilities by extending the 
output interface for the remote controller.
For output pins, we need to know how 
the external component will be driven: active 
high or active low, in push-pull or open-drain 
configuration, etc. As the name suggests, 
active-high components require a logic 1 to 
be turned on while active-low are activated 
on logic 0. For example, as we mentioned in 
Part 2, an LED connected with a pull-down 
resistor is active-high, while one connected 
with a pull-up resistor will be active-low.
Figure 2 shows output pins with transistors 
configured for push-pull and open drain 
operations. A CMOS push-pull driver has the 
ability to both source and sink current as 
the PMOS device turns on when the input is 
low and the NMOS device turns on when the 
input is high. In open-drain mode, only the 
NMOS is active and the driver output can only 
sink current. Its two states are low and high 
impedance (behaves like open circuit). When 
the input is high, the NMOS is active and the 
output is set to 0 V, When the input is low, the 
NMOS is off and the output is high-impedance. 
Typically, we use an external pull-up resistor 
to limit the current on any open-drain outputs. 
OUTPUT INTERFACE 
CONFIGURATION
To proceed with JEADI output interface 
pin configuration, we need to know how the 
external component (in our example, the RC 
controller interface button) will be driven: 
active high or active low, in push-pull or open-
drain configuration, etc. So, let’s have a look at 
our remote controller circuit. We used a New 
Bright RC car (see Photo 5). The direction is 
controlled by two rocker switches that push 
FIGURE 2
Equivalent internal circuit 
representations for open-drain and 
push-pull output pin configurations
PHOTO 5
New Bright RC car and controller (Source: www.newbright.com)
PHOTO 4
This is the Razor with additional 
connections for the input (Part 2) and 
output interfaces.
http://www.newbright.com
CIRCUIT CELLAR • JUNE 2017 #32324
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on an internal button. Removing a couple of 
screws from the controller allows inspection 
of the remote controller circuit (see Photo 6). 
Connecting a multimeter at the various solder 
connections while the controller internal 
buttons are being pushed revealed that these 
buttons on the circuit board are connected 
to the ground. Thus, we can assume that the 
push button is connected to an internal pull-up 
resistor in the transmitter IC (see Figure 3) and 
configure the ARM JEADI interface to handle 
that situation. 
In principle, all you need to do is enable 
the processor to trigger a signal equivalent 
to a button push, and then directly connect 
the JEADI output pins configured in open-
drain mode directly to the switch pins of 
the transmitter IC. However, doing a direct 
connection is potentially hazardous to the 
processor. If the user does not configure the 
output in open-drain mode correctly, then 
accidently pressing a controller button will 
short the processor output to ground. This 
will cause a high current drain from the ARM 
output, potentially burning it out. We have 
avoided this problem by adding a protective 
PHOTO 6
Additional components added to the 
circuit of the remote controller for 
interfacing with the microprocessor
 
circuitcellar.com/ccmaterials
RESOURCES
Atmel Corp., “SAM3U Series: Atmel | SMART ARM-Based 
Flash MCU,” 2015, www.atmel.com/images/atmel-6430-32-
bit-cortex-m3-microcontroller-sam3u4-sam3u2-sam3u1_
datasheet.pdf. 
EiE, Razor Firmware, http://embeddedinembedded.com/
low-level-firmware/led-basic-operation.
———, Razor Schematics, http://embeddedinembedded.
com/wp-content/uploads/2016/04/2014-08-29-MPGL1-
EHDW-03-Schematics.pdf.
JEADI Project Files, https://github.com/SMILE-Projects/
SMILE_Projects. 
STMicroelectronics, “RM0090 Reference Manual,” DocID018909, Rev 
13, www.st.com/resource/en/reference_manual/DM00031020.pdf.
———, “UM1472 User Manuel: Discovery Kit with STM32F407VG MCU,” 
DocID022256, Rev 6, 2016, www.st.com/resource/en/user_manual/
dm00039084.pdf.
 
SOURCES
ATSAM3U Microcontroller
Atmel | www.atmel.com
EiE Razor
Embedded in Embedded | http://embeddedinembedded.com
STM32F4 DiscoverySTMicroelectronics | www.st.com
http://www.st.com/resource/en/reference_manual/DM00031020.pdf
http://www.atmel.com
http://embeddedinembedded.com
http://www.st.com
www.circuitcellar.com/ccmaterials
www.atmel.com/images/atmel-6430-32-bit-cortex-m3-microcontroller-sam3u4-sam3u2-sam3u1_ datasheet.pdf
http://embeddedinembedded.com/low-level-firmware/led-basic-operation
http://embeddedinembedded.com/wp-content/uploads/2016/04/2014-08-29-MPGL1-EHDW-03-Schematics.pdf
https://github.com/SMILE-Projects/
SMILE_Projects
www.st.com/resource/en/user_manual/dm00039084.pdf
circuitcellar.com 25
FEATU
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FIGURE 3
These are the connections between the microprocessor and the remote controller. The diode protects the 
microprocessor I/O if the interface is incorrectly configured.
ABOUT THE AUTHORS 
Abdul Rafay (abdul.rafay1@.ucalgary.ca) is a 
graduate student in the Department of ECE 
at the University of Calgary. He joined aca-
demia in May 2016 after working for four 
years in embedded systems and FPGA-based 
digital design and verification.
Mike Smith (Mike.Smith@ucalgary.ca) is a 
professor of Computer Engineering at the 
University of Calgary. Mike’s main interests 
are in developing new biomedical engineer-
ing algorithms and moving them onto multi-
core and multiple-processor embedded sys-
tems in a systematic and reliable fashion. 
Jason Long (jason.long@engenuics.com) 
graduated from the Department of ECE at 
the University of Calgary in 2002 and now 
runs an embedded systems design and 
training company. He has run the Embed-
ded in Embedded (EiE) program for 15 years. 
diode between the JEADI interface and the 
controller.
The ground connection and four direction 
signals are connected to the jumper cable with 
connectors on both ends and taken out of a 
slit at the rear of the New Bright RC controller 
casing. A similar procedure will be needed 
for cars from other manufacturers. We leave 
it as an exercise for the reader to modify 
the project to send pulse-width-modulated 
signals to an RC helicopter control module!
CONCLUSION
As we walked through this series of articles 
for programming embedded ARM boards 
typically found in the academia, we setup the 
build environment, demonstrated hardware 
interfacing and developed a modular code 
structure using macros that allowed us to 
hide the architectural specifics of different 
evaluation boards while maintaining 
portability. We discussed how to extend the 
default capabilities of ARM boards by 
providing example of microprocessor control 
of a radio-controlled car. Starting with a 
virtual car interface to validate the algorithm, 
we moved on to driving the real RC car 
interface, providing the essential code and 
steps to add additional input and output 
interface along the way. In future, we are 
planning another series of articles where we 
are going to add a simple operating system to 
the boards. This will allow multitasking and 
give us more flexible control of the system, to 
enable us to develop more complex and more 
interesting applications. 
Authors' Note: We'd like to thank Warren 
Flaman for his assistance with this project. 
Warren is a technician with the Department 
of ECE at the University of Calgary. He has 
been responsible for the design of custom 
hardware for most of Dr. Smith’s hands-on 
interfacing laboratories.
advertisement_codecoverage_layout2017.indd 1 11.04.2017 08:32:56
mailto:abdul.rafay1@.ucalgary.ca
mailto:Mike.Smith@ucalgary.ca
mailto:jason.long@engenuics.com
www.lauterbach.com/1659
CIRCUIT CELLAR • JUNE 2017 #32326
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S If you want to set up a simple 
custom microcontroller development 
environment, this article is for you. As 
you’ll see, all you need to get started 
with FPGA-based embedded design 
is a PC, some HDL coding/synthesis 
tools, and an FPGA board.
By John Clayton
Editor's Note: 
This article first appeared in 
Circuit Cellar 235, 2010. 
FPGA Embedded Microcontroller 
Environment
Field programmable arrays (FPGAs) have become packed with logic gates, and many 
types also include features such as embedded 
block RAMs, hardware multipliers, and PLLs. 
Some throw in SERDES, memory interfaces, 
or Ethernet MAC functions—all the essential 
items needed for putting together really fancy 
“systems on a chip.” The FPGA offers these 
capabilities at an affordable price point, which 
adds excitement for the designer and begs 
the question: How can you take advantage of 
all that capability? Perhaps best of all, with 
FPGAs, there is no real penalty for trying 
out a design. If it’s faulty, you can easily 
modify it. In this sense, the FPGA becomes 
like a quick-turnaround personal foundry, a 
veritable playground for experimentation and 
innovation. In this article, I’ll share some advice 
on setting up a simple custom microcontroller 
development environment. Along the way, I’ll 
also present some ideas for an “easygoing” 
approach to design and development. 
THE INGREDIENTS
All you need to get started with embedded 
design using FPGAs is a PC, some HDL coding/
synthesis tools, and a suitable FPGA board to 
download to. Several suppliers have parts that 
are suitable for developing a small custom 
microcontroller environment. Obviously, the 
larger FPGAs will allow instantiating more logic 
(Multicore anyone?) and hardwired multipliers 
will often aid in the pursuit of higher execution 
speeds. The board design I used is also 
given out free, and there’s a user’s manual 
describing the board. One word of warning 
though: There’s no schematic. It’s basically an 
FPGA breakout board, with the download cable 
built right in.
In this article, I’ll first describe the rationale 
behind my slightly unusual approach to FPGA 
design. Then I’ll explain how I built up a system 
of building blocks that eventually became the 
trusted foundation on which I built and refined 
an embedded Microchip Technology PIC16F84-
compatible embedded microcontroller. The 
complete code for the design is provided in 
Verilog, and you can use many of the same 
blocks to build your own designs. (The code is 
posted on the Circuit Cellar FTP site.) If VHDL is 
the preferred language, I’ll leave the translation 
as an exercise for you. I use both languages, 
and because VHDL is “strongly typed,” I 
believe that Verilog is more appropriate for the 
“easygoing” experimenter. If translation is to 
be performed from one language to the other, 
I recommend doing it the old-fashioned way—
by hand. I don’t currently know of any really 
good, automated, free tools for the purpose.
DESIGNERS COME FIRST
One principle that I think is self-evident—
but which is quite often sacrificed in industry 
for the sake of cost reduction or basic 
economy—is this: The designer/developer is a 
respectable person, and some effort should be 
expended to make life easier for that person. 
Now, back in the good old times (Like the late 
1970s?), there were these simple monitor 
programs that developers used on SBCs. 
They were extremely low-level programs 
like Motorola’s MIKBUG or the firmware for 
Steve Ciarcia’s Z-80 Applications Processor 
(ZAP). These monitor programs filled a very 
important function by providing the ability to 
reset, read, modify, write, and single-step or 
begin code execution at a given point. Now, 
within an FPGA, you can create state machines 
that provide many of these basic functions in 
hardware, without making any demands on 
the target processor at all. As you may have 
guessed, the “monitor hardware” will have a 
circuitcellar.com 27
FEATU
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super-short learning curve, which is really not 
a bad deal. Once it has met its purpose, it can 
be cut out of the design completely, if desired.
IP CORES
This article focuses on producing complex 
FPGA designs from basic building blocks that 
were written from scratch. This presents a 
paradox of sorts. How do I effectively share 
what I’ve already built up, while at the same 
time encourage the sort of deep learning 
that comes from building a setof code 
modules from scratch? In essence, what I’ve 
decided is that most designers want to build 
a particular new function, and would rather 
not have to “reinvent the wheel” for all the 
surrounding support logic needed to exercise 
the experimental new module.
Enter the firmware-based design and 
debugging environment built around a 
homemade IP core called “rs232_syscon” (see 
Photo 1). It works through a serial port, with 
no software needed, and it allows you to enter 
and read back parallel data from registers 
and memory, as well as initiate a Reset 
command. With user-defined register fields for 
“go,” “single_step,” and for setting hardware 
breakpoints, there is really no limit to what the 
digital or DSP designer can define, debug, and 
use with such a system. Although it is tedious 
to hand-enter large amounts of data through 
the “hyperterm”-driven interface, scripts can 
be easily run from the PC that help alleviate the 
drudgery. After all, if it’s no fun, why pursue it 
as a hobby or otherwise?
SIMULATION OR NOT?
With the rs232_syscon core, and some 
ready-made parameterized and configurable 
register blocks up the designer’s sleeve, a 
“Module Under Test” can be run through its 
paces using the actual target FPGA instead 
of a simulator. Figure 1 shows the concept I 
used. I will not deny that simulations work like 
a charm. But I will say that it takes time to put 
together a really good simulation test bench. It 
takes more time to carefully run and analyze 
the simulation both pre- and post-synthesis. 
And in the end, there may well be some 
sort of real-world gotchas that just weren’t 
covered by the simulation. For example, will 
a frequency-doubling PLL correctly lock? Very 
few simulations will give good satisfaction on 
this type of question. Personally, I want to 
know about those real-world gotchas as early 
as possible, so I’m suggesting you get the code 
compiled and the bitstream loaded into the 
FPGA and start debugging ASAP.
DEVELOPMENT MODULES
As I previously stated, there are two major 
components which work together in this 
firmware-based development environment: 
the rs232_syscon, which is the “system 
controller,” and the register blocks, which 
form the boundary between the development 
environment and the new logic or IP core 
under test.
Describing the rs232_syscon module 
is easy because its purpose is to provide 
the world’s simplest command line. There 
are three commands: read, write, and 
initialize. The syntax is parameterized, so it 
FPGA
PC
Serial
Tristate bus
reg_8 reg_8 reg_8
Developing module
or function under test
RS232_syscon
FIGURE 1
A “module under test” can be run through its paces using the actual target FPGA instead of a simulator. This 
is the concept I used.
PHOTO 1
This is an example of a screenshot 
of rs232_syscon in action, set up for 
16-bit address with 8-bit data and 
quantity fields. If the quantity is 
omitted, the previous value is used.
CIRCUIT CELLAR • JUNE 2017 #32328
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scales according to the way the module is 
instantiated (see Table 1).
The UART function is designed with 
simplicity in mind—a simple TX, RX, and GND 
interface, without double buffering or flow 
control of any kind. I trust I haven’t offended 
anyone by also conveniently leaving out the 
parity bit and fixing the UART transfer size at 
8 bits. After all, its just for simple debugging.
I am particularly proud of the automatic 
data rate generator inside this module because 
it synchronizes to whatever data rate it sees 
from the host terminal—even nonstandard 
speeds. It does this by checking the received 
intervals of each character, filtering out and 
rejecting the characters that do not match what 
it is looking for, which happens to be an “enter” 
character (technically, the carriage return, 
0x0D). If the relative sizes of the intervals 
within the received candidate character match 
those of an enter character (which are known a 
priori), the module decides that the candidate 
character must be an “enter” character, so 
it sets its divider to the count derived from 
measuring the intervals, and implements the 
new baud rate automatically. If the target 
system uses a programmable system clock 
generator, the user can adjust system clock 
frequencies under register control, and the 
board’s UART still easily adjusts to the new 
baud rates “on the fly.” This is excellent for 
the human user, who can see a prompt after 
simply pressing Enter a time or two. Now that 
I think of it, wouldn’t it be a fun feature to 
add an automatic TX/RX swapping function for 
those times when the lines end up connected 
backwards? It might save some head 
scratching. But I digress.
The other part of the support environment 
is the register block. For the most “easygoing” 
environment, I’ve chosen to embrace the use 
of internal tristate gates. Some have preached 
against the use of internal tristates, citing 
inherent difficulties in formal verification 
methods, test coverage, and lack of ability to 
completely avoid glitches or bus contention. The 
debugging environment described here uses 
them for one simple reason: they can make 
life easier. With internal tristates, I can run 
a single bidirectional data bus out to register 
blocks, and they all get an address and respond 
to commands quite well. They’re easily scalable 
in number. When you think about it, without the 
tristate bus, each new block of registers would 
require a separate new input on a data read 
multiplexer, which can become cumbersome as 
it doesn’t change its number of ports quite so 
easily as this tristate bus. Most systems need 
several registers to control a given function, 
so why not group them together? I put them 
into sets of eight. If I want another set of eight 
registers, I just “plop” down another instance 
of the “reg_8pack” module. (I suppose there 
could have been a register six-pack, which 
sounds nice, but of course, being greedy for 
more registers, in the end I yielded to the fact 
that eight is a power of two.) The register block 
gets three address lines, the data bus, read/
write line and a decoded “register block select” 
line. From continual use and tweaking, many 
features have been added to the basic register 
block. For example, the current register block 
is fully parameterized as to data bus width, 
individual register widths (1 bit minimum), 
default contents of the registers at reset, and 
whether each register is R/W or read only. 
There is even a provision for setting or clearing 
the register bits under control of the logic within 
the fabric of the FPGA. This can come in quite 
handy when single-stepping a microcontroller 
or implementing a hardware breakpoint.
BREAKING THE MOLD
So, now that I’ve established some useful 
building blocks for a basic development 
environment, what about this fabled 
microcontroller design I’ve been dreaming 
of? I’ll describe something I figured out while 
implementing the “risc16f84” instruction 
execution engine. I’m giving it that funny name 
this time to highlight the fact it’s not a fully 
featured PIC16F84 microcontroller. Its design 
has been modified so that it’s missing some 
things which are in the standard PIC16F84 
RS232_syscon Syntax
All parameters are in hexadecimal.
Command Parameter 1 Parameter 2 Parameter 3 Comments
r aaaa qq Read starting from address aaaa, 
quantity qq items
w aaaa dd qq Write starting at address aaaa, 
data dd, quantity qq times
I Initialize, issues a reset pulse
TABLE 1
The unit is parameterized, so that 
the width of the data bus determines 
the width of the dd field. Likewise, 
the address bus can be scaled to any 
width. Even the quantity field can be 
enlarged if desired. Output formatting 
for reads is automatic.
ABOUT THE AUTHOR 
John Clayton (morianton@gmail.com) holds a BSEE from Brigham Young 
University and an MSEE degree from The University of Texas, Austin. After 
working for 12 years as a DSP programmer and board designer, he is nowa principal design engineer at Orbital Sciences Corporation in Chandler, AZ. 
mailto:morianton@gmail.com
circuitcellar.com 29
FEATU
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microcontroller, and it’s got some extra growth 
as well. When working to approximate the 
performance of an existing processor design, 
you can choose which level of compatibility is 
preserved. 
One, choose a design that is completely bit-
accurate and cycle-accurate in every way. It’s 
a lot of work, and less fun in my opinion.
Two, choose a design that’s the same as the 
first, but throw out JTAG debugging. After all, 
you can load code in different ways.
Three, choose a design similar to the first 
two, but also throw out cycle accuracy. You 
really just want it to function correctly. After 
all, what are a few cycles between friends?
Four, choose a design that’s instruction set-
compatible, but not code-library-compatible. 
In other words, eliminate the package-
constrained ports and begin to set up I/O for 
the microcontroller the way you really want it. 
After all, it’s inside an FPGA now so you needn’t 
be limited to ports A, B, and C. Add a few 
new ports into the memory map. Obviously, 
this choice may require custom SW coding or 
modifying existing code libraries somewhat.
Five, you have control of the CPU instruction 
superset. Consider adding new instructions.
And six, add tightly coupled hardware 
accelerators to take workload off of the 
processor. After all, you can completely halt 
and restart the processor on a cycle-by-cycle 
basis if desired.
This list should inspire some creative ideas 
and help you “think outside the box.” As you’ll 
see, I chose to work at level four from the 
aforementioned list. Also, you can pipeline the 
design, or not, to whatever level you choose.
DEBUGGING ENVIRONMENT
Initially, I was stumped when my UART 
wasn’t responding properly. So, I borrowed a 
logic analyzer and saw what was happening. 
As luck would have it, the problem wasn’t 
immediately obvious. So, I recompiled the 
code, this time adding a “debug port,” which 
would show the shift register contents and 
finite state machine state. This quickly led to 
the “ah-ha” moment, and the problems were 
fixed in the code.
Hopefully, with the building block provided 
in this article, you will not be constrained to 
work at such a low level as this. But I can’t 
guarantee it, and you may need a logic 
analyzer, or even (gasp) a simulation or two.
Once the design environment is working, 
many problems can be attacked by looking at 
register contents and reasoning about what the 
unit under test/development is actually doing. 
I was able to develop several different cores 
by using the rs232_syscon core, and these are 
all posted at www.opencores.org. Some of the 
older projects will have earlier versions of the 
support environment which don’t include some 
of the features now present.
LCD PANEL
One of the fun dreams I realized with my 
completed RISC PIC16F84 core was to hook it 
up to an old VGA resolution LCD flat panel from 
a laptop. I purchased a broken laptop on the 
Internet that would only put up error codes on 
the screen. This was what I wanted because 
I knew I could use the FPGA to scope out the 
signals present at the LCD interface. I made 
sure it was an older, parallel direct drive type 
of display, not one of the newer high-speed 
serial LVDS types—although now that I think of 
it, some FPGAs will support LVDS. But there I 
go digressing again. My FPGA breakout board 
did not contain external RAM. Rather than add 
some, I decided to use the internal block RAMs 
as a rudimentary display buffer. Because of the 
limited amount of memory, I ended up with 
“fat” 5 × 5 pixel color blocks in a 128 × 96 
array, supporting eight colors.
I was able to write a colored-rectangle 
“screen saver” program for the RISC PIC16F84 
processor in C and load it via the rs232_syscon 
module. Then I began speed-testing the 
processor core. I enjoyed watching the screen 
updates vary in speed as I adjusted the clock, 
all the while keeping an eye on my interrupt-
serviced LED display which would change at a 
constant rate because I had a fixed-frequency 
interrupt request generator set up.
A fun variation on the full-size LCD panel 
project is to grab an old cell phone and use 
the FPGA to explore the interface to its little 
display. Sometimes cell phone displays can be 
purchased with datasheets as well. 
PHOTO 2
a—This is the FPGA breakout board. 
There is a ribbon cable connection to 
the WIZnet board. The USB is only for 
power. The interface to rs232_syscon 
is via a nine-pin D-shell connector. 
b—This view from the back shows 
the Xilinx FPGA configuration PROM 
and an on-board parallel cable 
implementation.
a) b)
http://www.opencores.org
CIRCUIT CELLAR • JUNE 2017 #32330
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WILL ANY BOARD DO?
The FPGA board used for the coding 
described in this article was home-made, and 
the design files for that board are provided 
freely to anyone who wishes to use or modify 
it. One day I heard my spouse very clearly 
utter the nonsense word “Pondooker” and I 
thought it was a cute name for the board, 
plus it fit into a neat five-letter, consonants-
only naming scheme: PNDKR. As I mentioned 
earlier, PNDKR is really a simple board—more 
of an “FPGA breakout board,” than anything 
else. Other than RS-232-level translators, the 
board just has a bunch of I/O headers. So I 
would say that any FPGA board with a suitable 
number of available I/O pins can work. One can 
even go onto an online auction and purchase 
an FPGA board pulled from some product. A 
board schematic is not always required. As 
long as you can configure the FPGA device, 
provide it power, reset and clock, and obtain 
access to an appropriate number of I/O pins, 
those are the main requirements.
One factor which militates in favor of 
finding a commercially produced board 
instead of making one is the growing number 
of FPGAs that are housed in fine-pitch BGA 
packages. These can be difficult to work with 
by hand. Unless the BGA balls are brought out 
to headers or vias, the FPGA cannot easily be 
“probed” on an oscilloscope or logic analyzer. 
Nevertheless, one company, SchmartBoard, 
provides a 400-pin board that purportedly 
allows hand soldering at a 1.0-mm pitch for 
those who wish to try their hand.
AUDIO OVER ETHERNET
During the 2007 WIZnet iEthernet 
Design Contest, I was tantalized by the 
possibility of interfacing an FPGA board with 
WIZnet’s WIZ810MJ board for easy Ethernet 
connectivity. I found that the embedded RISC 
PIC16F84 microcontroller interfaced with the 
WIZnet IC quite easily. The connections were 
provided by an IDC cable (see Photo 2). You 
can review my flexible audio transmission over 
Ethernet (FATE) project at www.circuitcellar.
com/Wiznet/winners/001103.html. The design 
sets up a simple dedicated wired Ethernet 
network. You can then use the network to 
coordinate the distribution of high-quality 
audio signals throughout a building and the 
area around it. 
AFFORDABLE FUN
I currently write VHDL code for various 
aerospace-related FPGA applications. As 
you can imagine, the test requirements 
for these applications are rigorous. If you 
will pardon the pun, the exclusive use of 
hardware testing in lieu of simulation for 
aerospace circuit development and debug 
“will not fly.” Therefore, I was pleased to 
embark on a course of writing test benches 
and using simulations to create and debug 
new designs. This effort has resulted in 
the realization that within a test bench, a 
simulation can support a system controller 
that generates the same bus cycles as the 
hardware-based “rs232_syscon” module—
effectively using text input and output files 
to deliver commands to the system under 
test—and record the responses from the 
system. This approach has the advantage 
that a particular set of “syscon” commands 
can be used (with very little modification) 
during both the simulation and hardware 
checkout phases of design and test.I have not gone to the trouble to make the 
output identical between the two modules, 
but it could be done easily. The input is mostly 
identical. The only modification is the addition 
of a simulation delay value per command line 
for sim_syscon. The VHDL source code for this 
module and example I/O text files have been 
included with the other (Verilog) source files 
posted on the Circuit Cellar FTP site. A recent 
translation of rs232_syscon into VHDL is now 
available. If anyone translates “sim_syscon” 
into Verilog, I’d be pleased to receive a copy.
Also note that in sim_syscon the “w” 
command (write) has been renamed as 
“f” (fill) so that the write command can be 
revamped to handle multiple data items on a 
single command line. This should be a useful 
modification if you want to use the interface 
for loading processor code or large volumes 
of data to the target system. The number of 
command lines needed can be reduced by 
more than an order of magnitude.
While it is difficult for an FPGA to compete 
directly with ASICs on fundamental clock 
speed, power per MIPS, analog capability, or 
low cost in volume of millions of units, I like to 
think they get closer than anything else can at 
fairly low cost. And besides, I probably won’t 
be selling millions of units any time soon. But 
I should be having fun along the way? 
 
circuitcellar.com/ccmaterials
PROJECT FILES
To download the code, go to 
ftp://ftp.circuitcellar.com/
pub/Circuit_Cellar/2010/235.
RESOURCE
PNDKR User’s manual and files, www.
opencores.org.
SOURCES
PIC16F84 Microcontroller
Microchip Technology, Inc. | www.microchip.
com
XC2S200E Spartan-IIE FPGA
Xilinx, Inc. | www.xilinx.com
http://www.xilinx.com
www.circuitcellar.com/Wiznet/winners/001103.html
www.circuitcellar.com/ccmaterials
ftp://ftp.circuitcellar.com/pub/Circuit_Cellar/2010/235
www.opencores.org
www.microchip.com
such as this book, 
designing a microprocessor 
 can be easy. 
Okay, maybe not easy, but certainly 
less complicated. Monte Dalrymple 
has taken his years of experience 
designing embedded architecture 
and microprocessors and compiled 
his knowledge into one comprehensive 
guide to processor design in the 
real world. 
cc-webshop.com
Microprocessor Design Using 
Verilog HDL will provide you 
with information about: 
• Verilog HDL Review
• Verilog Coding Style
• Design Work
• Microarchitecture
• Writing in Verilog
• Debugging, Verification, 
and Testing
• Post Simulation and more!
Verilog HDL
With the right tools
Monte demonstrates 
how Verilog hardware 
description language 
(HDL) enables you to 
depict, simulate, and 
synthesize an electronic 
design so you 
can reduce your workload 
and increase productivity.
www.cc-webshop.com
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Creativity Lives Here
An Interview with Jean Noel Lefebvre
Jean Noel Lefebvre is an electronics engineer with a strong interest in how 
people interact with the electronic systems. 
A true outside-the-box thinker, started his 
company, Ootsidebox (www.ootsidebox.fr), 
right in the middle of the YouFactory fab lab 
in Lyon, France. He knows where creativity 
lives and is willing to show it to you. Meet 
Jean Noel Lefebvre.
HETTINGA: Why do you have your office in 
the middle of the fab lab?
LEFEBVRE: The fab lab here is a wonderful 
place where people can come to do some 
3-D printing, laser cutting, or to work with 
electronics. But perhaps more importantly, it 
is a place where you can meet other people, 
where you can learn new skills and find new 
ideas and inspiration.
HETTINGA: That is important for you—
the interaction between technology and 
others?
LEFEBVRE: Yes, that has always been part 
of my projects. My first invention was the 
Ootside box. It was a touch application and it 
allowed you to control a computer or a system 
just by pointing or with gestures. We tried 
raising enough funds on Indigogo to continue 
developing it, but unfortunately, we did not 
reach our targets. After that, I decided to 
name my company after this project. Through 
this project, I also discovered the Arduino 
ecosystem and the enormously inspiring 
world of makers and fab labs. I always was 
interested in electronics, but when you are 
very young, you have no idea what you are 
doing and all my radios and sound equipment 
failed. That is what I learn here—how to help 
people, sometimes young people, understand 
how electronics works.
HETTINGA: And what do they need to learn?
LEFEBVRE: Good soldering! If you learn 
good soldering, you are already halfway to a 
successful project. I sometimes do soldering 
classes in schools. I bring some easy soldering 
projects and some equipment, and it is very 
rewarding to see how the kids are able to 
Jean Noel Lefebvre (Founder, Ootsidebox)
With the proliferation of affordable 'Net-connected technologies during the last decade, the nontechnical 
members of society have come to realize that electrical engineering is an exceedingly creative endeavor. 
Outside-the-box innovators like Jean Noel Lefebvre are literally reinventing how we interact with the world 
around us.
By Wisse Hettinga
Video: Interview with 
Jean Noel Lefebvre 
(https://youtu.be/iTD02dvU2x4)
http://www.ootsidebox.fr
https://youtu.be/iTD02dvU2x4
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make their first electronic project.
HETTINGA: You are a big fan of Arduino.
LEFEBVRE: Indeed. The Arduino platform 
and ecosystem is important because of its 
low threshold to the world of electronics. 
Arduino is even so important and valuable 
that I decided to make a real gold version, the 
Golduino. I have it here, and it is still work in 
progress, but for people who want to have 
something special and valuable, it will be a 
great thing to have or to give to others.
HETTINGA: Again, I see you have a special 
take on electronics. And again, this refers 
to a special interaction between people 
and electronics.
LEFEBVRE: I feel that is very important. 
The world of technology can make people 
alone and isolated with very little room for 
emotions. Take the IoT developments as an 
example. You can see it as a world of sensors, 
actuators, and huge amounts of data. You can 
easily get lost. To find a response to that, I 
am doing a special project called "Color the 
World." It will be a Wi-Fi-connected lamp that 
will take the color of everything you hold in 
front of it. In the back, there will be a world 
map where you can "share" you color with 
others and color the world. On Earth Day you 
can all decide to color the world green, make 
your part of the world yellow if the sun shines, 
or blue if the world is "blue."
HETTINGA: And you found a way to keep 
playing your old EP records?
LEFEBVRE: Ha, yes. If you are like me, you 
will still have your old EP vinyl records, but 
no easy way to play them anymore. With 
my Floating Disc Player, you will be able to 
use the cover of the EP to play your favorite 
music again. Inside the EP cover, there is an 
RFID tag, and the moment you insert the EP 
The Airbar interface provides 
infrared touch anywhere
Playing old tunes with the Floating 
Disc Player
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in the player, it will recognize the song in 
the playlist and start the music. It is a great 
player for home parties!
HETTINGA: What more are you working on?
LEFEBVRE: Again, it is interaction, I am 
afraid. I am making an interface for the 
Airbar. The Airbar is an infrared sensor bar 
that originally was developed to turn your 
laptop screen into a touch screen. With my 
interface, it will be possible to turn everything 
like desks, whiteboards, displays, and 
windows into interactive areas. You can draw 
a piano keyboard on a piece of paper, launch 
the application, and you can start playing 
by just touching the paper. The resolution 
is good enough to recognize your writing on 
plain paper, turn that into a digital pattern,and display that in an application.
HETTINGA: This will all be available for 
others?
LEFEBVRE: Yes, it will be available on my 
website www.ootsidebox.fr. It will be all open 
source, so everyone who is interested can 
continue developing the product.
HETTINGA: You know where creativity 
lives?
LEFEBVRE: Yes, that’s easy. It lives where 
open-minded people come together and want 
to share their ideas with others. That is why 
fab labs, tech shops, and makerspaces are 
important—open places where people can 
walk in, have a coffee and a chat, and go away 
with new ideas. 
Color the IoT world 
http://www.ootsidebox.fr
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Short-Range IR Communications System
Progressive Reflective Transmission Solution
By Robert N. Capper, Jr. (Circuit Cellar 179, 2005)
Robert’s PIC-based IR transmission system is perfect for 
short-range communication. It’s a reflective system, so you 
can place the various components wherever you’d like. 
“With IR technology, addressing is implicit. If it’s in the 
local space, it’s part of the system. If it’s in the next room, 
it doesn’t (for all intents and purposes) exist. The reduced 
complexity of transmission (compared to 
spread spectrum) can enable battery life 
expectancy that you can measure in years. 
But where’s the complexity? The penalty is 
in the receiver.
My remote wireless IR door switch 
system uses non-line-of-sight diffuse 
Reflective mode of transmission. It 
generally operates without special 
consideration for the placement of the 
components as long as they can see into 
a common reflective space. The system, which also works in 
a direct line-of-sight configuration, can achieve distances of 
better than 70′. This places constraints on the receiver, which, 
for a variety of reasons, must be powered by the AC mains. 
So, the trade-off is a simple transmitting device that has a 
long battery life but a moderately complex receiver that must 
be line powered …
When working on an IR signaling application, you must 
address three critical topics: the signal-to-noise ratio, the 
signal-to-noise ratio, and the signal-to-noise ratio. If you solve 
this problem at the outset, you’ll have done most of the hard 
conceptual work. Optical output power is the most important 
part of this solution. This is, of course, a solution with an 
easy answer and hard limits. Your first objective should be 
to get as much free optical power as possible. Well, OK, it 
isn’t really free, but picking the most 
efficient IR LED for the application will 
go a long way toward easing subsequent 
demands on the battery. Unfortunately, 
I’ve found that choosing the optimum 
IR LED isn’t always simple. Datasheets 
from different manufactures don’t always 
list specifications in ways that make 
comparisons easy. But beyond that, even 
comparing the devices available from one 
manufacturer doesn’t result in expected 
performance differences.
A number of issues may contradict simple intuition. Of 
course, total power output is a prime consideration, but you 
may not be able to read that directly, given the manufacturer’s 
specifications. Even knowing this, there’s no direct correlation 
between the total output power and performance in this 
application.”
These articles and others on topics relating to Communications are available 
at www.cc-webshop.com. 
Embedded System Communication
A Control Platform for Ethernet-Enabled Systems
By Francis Fernandes, Rajendra Gad, Vinaya Gad, Shane Lobo, Gourish Naik, and Jivan Parab (Circuit Cellar 255, 2011)
Many of today’s industrial and consumer electronic 
applications have hefty data transmission needs and 
requirements. This means engineers must incorporate 
efficient embedded technologies that can communicate 
effectively with each other. You can customize this SoC control 
platform for any Ethernet-enabled 
design on your workbench. 
“This article presents a system-
on-chip (SoC) developed using an 
Altera Nios II softcore processor, a 
general embedded system platform 
for Ethernet-enabled appliance 
control. The embedded system is 
implemented on Altera’s Cyclone-
II FPGA. The designed platform 
is flexible and versatile and can 
be customized for any Ethernet-
enabled appliance or smart 
appliance. The client-side frontend 
interface is .NET-based for a rich 
and user-friendly design.
The .NET framework is used by the remote client to connect 
to the server which uses a Nios II processor. The platform can 
also be used to implement TCP/IP control for complex control 
systems. The design uses the lightweight Internet protocol 
(lwIP) stacks module of Micriμm’s 
μC/OS real-time kernel as a design 
handshake over the session layer of 
the OSI model.
The nearby figure represents the 
client-server system configuration 
over an Ethernet network. The 
client has a .NET frontend interface 
for user-friendly purposes and 
the server is running socket 
programming at the backend using 
an lwIP TCP/IP stack over the Nios 
II softcore processor on a Cyclone-
II FPGA. LwIP is a lightweight 
implementation of the TCP/IP 
protocol suite.”
Communications
http://www.cc-webshop.com
CIRCUIT CELLAR • JUNE 2017 #32336
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Communications
Microprocessor Communications
By Stuart Ball (Circuit Cellar 102–103, 1999)
Communication is tricky when you have several processors 
involved. In this two-part series, Stuart looks at ways to get 
the messages between processors on a single backplane. He 
writes:
“Although most embedded applications can be handled 
with a single processor, every now and then, you find a job 
requiring a system with two or more processors. Nearly 
every multiprocessor design needs a way for the processors 
to communicate. In this series, I look at the different methods 
for communicating between processors and the various 
tradeoffs involved.
To start off, I’ll look at useful approaches when two 
processors share the same PC board or backplane. Let’s say 
the processor communicates with a higher-level system, like 
a PC, and distributes commands to a lower-level processor 
that controls a DC motor. 
CPU 1 talks to the host system, and CPU 2 controls a DC 
motor, under the control of CPU 1. CPU 2 senses the motor 
position via a shaft encoder and gets other sensor inputs 
as well. In a typical real-world scenario, you might find this 
arrangement if CPU 1 needs to execute slow, complex tasks 
in response to the host, and CPU 2 has to execute fast, simple 
tasks to control the motor speed or position. You may find 
CPU 1 controlling multiple processors like CPU 2.
Clearly, CPU 1 must communicate with CPU 2 to get 
this job done. This requires commands like turn motor on, 
turn motor off, set motor speed to x, and start motor when 
sensor y goes active. The nearby figure shows one method of 
communicating between processors. The circuit is an 8-bit 
register written by CPU 1 and read by CPU 2. The register is 
a 74xx374 (xx = LS, HC, ACT, etc.), but this scheme can be 
implemented in programmable logic or with any register that 
has tristate outputs.
The D inputs to the register connect to the data bus of CPU 
1 (or to the lower 8 bits if CPU 1 is a 16- or 32-bit processor). 
The clock input (pin 11) connects to a write strobe from CPU 
1. The write strobe is the same type you’d use to clock data 
into any register or a peripheral IC, and it goes low when CPU 
1 writes to the specific address where the communication 
register is located.
The register’s Q outputs connect to CPU 2’s data bus. 
When CPU 2 wants to read the register, it generates a low-
going read strobe (a decoded address strobe) at the register’s 
Output Enable (pin 1) This strobe enables the tristate outputs, 
so CPU 2 to read the register data.”
Flexible USB-CAN Bridge 
By Craig Beiferman (Circuit Cellar 157, 2003)
When Craig decided that he needed a cost-effective, 
efficient way to control several microcontroller circuits from 
one computer, he used a PIC microto design a USB-CAN 
distributed motion controller. He writes:
“Do you want the capability to control numerous 
microcontroller circuits from your computer? With this handy 
project, now you ‘CAN.’ In conjunction 
with fellow designer Dale Herman, I built 
an inexpensive circuit that allows a PC’s 
universal serial bus (USB) to interface to 
a controller area network (CAN) bus.
When it comes to communication 
between multiple microcontrollers, I 
cannot think of a nicer interface than the 
CAN bus. You may be asking yourself, 
why? What’s wrong with RS-232, RS-485, 
SPI, or I2C? The simple reason is that 
if you really need full processor power, 
nothing will slow you down like constant 
interrupts for every byte received, not 
to mention the fact that the additional 
software overhead of packet decoding and 
checksum checking, ACK NAK schemes, 
and so on eat processor bandwidth. The 
CAN link-layer hardware handles many of 
these issues in the background.
OK, so what’s the best choice for 
communicating with a PC? Unfortunately, 
the PC does not come standard with a 
CAN bus, and some manufacturers are starting to phase out 
parallel and RS-232 ports (particularly on laptops). However, 
on the PC side, USB has been growing in popularity, and for 
good reason: its simple plug-and-play and high speed make 
for a great bus.
At first, I was worried about how long it would take me 
to develop drivers for a USB interface. I’m certainly not a 
USB expert. That’s when I stumbled 
across Future Technology Devices 
International’s (FTDI) FT245BM chip, 
which is a cost-effective device for 
quickly interfacing a microcontroller to 
the USB bus with little knowledge of the 
USB specification. The FT245BM allows 
a transfer speed of up to 1 MBps, and 
its 384-byte transmit and 128-byte 
receive FIFO buffers allow for high data 
throughput. A parallel microcontroller 
interface allows for the quick transfer 
of data. But what about the drivers? No 
problem. To my relief, I found out that 
FTDI supplies free Windows drivers 
and example schematics. With my fear 
subsided, I pressed on looking for an 
appropriate microcontroller. I chose the 
40-MHz PIC18F258 microcontroller from 
Microchip because of its built-in CAN 
2.0B controller, which can communicate 
at up to 1 Mbps.”
circuitcellar.com 37
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Mic Check
A Communication System for Cyclists
By Ed Nisley (Circuit Cellar 133, 2001)
It’s all about communication. Back in 2001 before cell 
phones were ubiquitous, Ed designed a way to remain in 
contact with fellow bicyclists while on the move. In this article, 
he explains how he uses an electret microphone hooked into 
his helmet to chat with cycling companions. He writes:
“I thought I should review the most basic input device 
in common use: the microphone. In this day and age, this 
means an electret microphone. Along the way, I’ll look at 
some issues in practical applications. Rest assured, you will 
not find the ultimate secret of high-fidelity reproduction 
revealed in this article …
The circuit connects an electret mic to my ICOM Z1A 
handheld amateur radio. It also incorporates the earbud 
audio output and push-to-talk control functions, so the circuit 
(see the nearby figure) has a few more bits and pieces than 
you might expect. In addition, it must work in an RF-rich 
environment because the Z1A transmits 5 W in the 2-m or 
70-cm band through a nearby antenna when you’re talking 
through the mic!
The specs for the Z1A’s external mic signal assume a 
dynamic microphone, which produces a higher 
audio output at a lower impedance than an 
electret element. Although the mic jack includes 
a separate 3.3-VDC supply, you can’t simply wire 
up an electret mic and expect to get decent 
results. An electret’s audio output is too low and 
its impedance is too high. I’ve tried it; it doesn’t 
work.
Unfortunately, you can’t simply wire up an op-
amp and get decent results either, because RF on 
the mic input overwhelms the few millivolts of 
audio. At best, the audio sounds distorted and, at 
worst, you don’t hear anything at all.
The circuit (see nearby figure) uses ferrite 
beads on the mic and power leads, as well as 
the amplified audio output to the Z1A. These 
beads, often referred to as ‘black magic,’ act as 
a relatively high resistance at RF frequencies and 
form an effective filter when used outboard of a 
low RF impedance.”
These articles and others on topics relating to Communications are available 
at www.cc-webshop.com. 
Selecting the Best CAN Controller
By Olaf Pfeiffer (Circuit Cellar 143, 2002)
Selecting the right CAN controller for an application can 
be a daunting task. Fortunately, Olaf has some great advice 
for minimizing cost and maximizing performance. He writes:
“Traditionally, CAN was used in automotive applications. 
Today, CAN is one of the best choices for embedded networking 
applications that need to communicate between several 
embedded 8-bit and 16-bit microcontrollers. The biggest 
current growth sectors are embedded machine control 
applications such as home appliances, industrial machines, 
and other machinery containing multiple microcontrollers 
that need to communicate with each other.
A big advantage of CAN compared to other network 
solutions is the price/performance ratio. When it comes to 
price, CAN is the most affordable network, next to a regular 
serial channel. It costs about $3 to CAN-enable an existing 
microcontroller design. When you break it down, replacing an 
8-bit or 16-bit microcontroller with one that features a CAN 
interface costs about $1. An additional $1 is needed for the 
transceiver (line driver for twisted pair) and another $1 for 
connectors and additional PCB area.
Replacing a microcontroller with one that features a 
CAN interface seems easy, because about 20 different 
semiconductor manufacturers produce microcontrollers with 
one or multiple on-chip CAN interfaces. However, there are 
major dissimilarities in the CAN controllers available that can 
make a big difference when it comes to performance. The 
difference can be that with one device, the communication 
overhead uses all of the available MCU performance, whereas 
on another device the same communication task can be 
performed with a minimum of MCU execution time.
This article will point out some of the major differences 
between CAN controllers available and explain how the 
differences can affect your application.”
http://www.cc-webshop.com
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CIRCUIT CELLAR • JUNE 2017 #32338
A Dynamic Overview of Key 3-D 
Printing Features
Commercialized 3-D printing technology has come a long way during the last 30 years. We've 
witnessed significant advances in printing speed, printing resolution, material quality, printing 
software, and more. With easy access to 3-D printers, it's an exciting time for everyone interested 
in rapid prototyping and product modeling.
By Ashley Mellen & Alexandrea Mellen
Three-dimensional (3-D) printing technologies made their 
commercialized debut with 3D Systems 
stereolithography in 1987. Though the 
technology faced technical, chemical, 
and financial complications, it launched 
years of additive manufacturing 
research into multiple industries. This 
led to what is expected to be $27 billion 
in 3-D printing spending by 2019. As 
the industry has developed, so have the 
printers. 3-D printing companies have 
advanced and diverged significantly to 
feature new processes and cutting-edge 
hardware and software features. 
INDUSTRIAL VS CONSUMER
In the 1980s, 3-D printing research was 
more commonly and technically known 
as additive manufacturing research. 
Additive manufacturing encompassed all 
uses of processes designed to create 3-D 
parts by layering material. Over the last 
30 years, the terminology has matured. 
While the same core concept applies, a 
distinction has been made to separate 
industrial and hobbyist use. Additive 
manufacturingis associated with scaled, 
industrial applications, and 3-D printing 
is associated with rapid prototyping and 
consumer use. 
TYPES
Six fundamental 3-D printing 
processes dominate the modern 
market: fused deposition modeling, 
stereolithography, material jetting, 
binder jetting, selective laser sintering, 
and directed energy deposition. Let's 
review each one.
Fused deposition modeling, used by 
Stratasys, is the most common hobbyist 
3-D printing technology. A thermoplastic 
is forced through a heated extruder 
head, where it becomes molten and is 
fed onto the product in a single, two-
dimensional layer. The head moves two-
dimensionally during each build of a 
single layer, and it then moves vertically 
between layers to make space for the 
next layer. 
Stereolithography, a process used by 
Formlabs, utilizes photo-polymerization. 
An ultraviolet laser is focused onto a 
vat of photopolymer resin, where it 
draws each layer of the part. The resin 
Ashley Mellen is an organic chemist employed as a production manager at the Mellen Company, Inc. She 
earned her Master’s degree in chemistry at Boston University with a focus on organic polymer chemistry. 
Her Master’s thesis was the study of eco-friendly photosensitive resins for 3-D printing under Dr. Mark 
Grinstaff. Aside from work for her degree, Ashley has worked with several extrusion, stereolithography, and 
binder jetting printers over the past six years.
Alexandrea Mellen is a computer engineer specializing in mobile app development and information security. 
She has presented her research at Black Hat, the largest information security conference in the world, and 
MIT. Alexandrea has spent a great deal of time mentoring startups in the Boston community as a partner 
at the Dorm Room Fund and as a mentor for multiple universities, including Hult Business School. She also 
worked as an engineering consultant for startups around Boston before founding her own startup, Terrapin. 
She has over five years of experience in 3-D printing working for multiple companies.
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solidifies where the laser is drawn due to its 
photosensitive nature, and then the process 
is repeated with a new layer until the part is 
completed. 
Material jetting, also used by Stratasys, 
sprays liquid photopolymer in layers, which 
are subsequently cured with ultraviolet light. 
Each layer is added and cured, then the 
process repeats until the part is formed. 
Binder jetting, used by ExOne, shoots 
liquid binding material across a powder bed 
in layers. The powder and binding material 
combine, then another layer of powder is 
spread across the bed and the process is 
repeated until the part is complete. 
In selective laser sintering, a high-
powered laser is used to fuse plastic, metal, 
ceramic, or glass powders layer by layer to 
form an object. 3D Systems sells SLS printers, 
among others. 
During directed energy deposition, 
electron beams are focused on a metal 
powder to fuse the metal together in layers 
until the part is complete. This is used in large 
scale applications such as the repair of fighter 
jet wings. 
SOFTWARE
3-D printing software differs drastically 
based on a familiar debate: the power of 
open source. Open-source software can be 
incredibly helpful for users who wish to own 
and operate different 3-D printers with the 
same software, while still having a large 
number of features and a reliable product. 
Some open-source software, such as Cura, 
makes it simple for a beginner to set up a 
print on almost any 3-D printer, while also 
having over 200 features for experienced 
users. The main drawback of this kind of 
software is that it requires either an SD card 
or a USB connection from the printer to the 
computer. As a solution to this problem, 
companies like AstroPrint sell a software 
and hardware product combination. Their 
hardware, AstroBox, connects to a 3-D 
printer through the normal cable connection, 
but instead of connecting to the computer, it 
enables the user to print wirelessly from any 
web-enabled device. For tinkerers, a company 
called OctoPrint supplies solely the software, 
and encourages the user to set up the system 
with a Raspberry Pi. 
Software also exists that is specific to a 
single type of printer, which, though limiting, 
enables the software to work seamlessly and 
have hardware-reliant features. NVBots has 
developed the NVCloud, which can only be 
used on an NVBots printer, but is optimized 
for the printer and includes hardware-specific 
features. For example, the user can queue 
multiple print jobs at a time because of the 
printers automated part removal hardware. 
This software feature would be useless 
without the company-specific hardware.
SPEED & RESOLUTION
Printing speed and resolution are uniquely 
linked qualities in 3-D printers. Often, an 
increase in speed results in a decrease in 
resolution, and vice versa. Speed of the print 
can be improved by printing thicker layers, 
but layer thickness is the main quality that 
determines resolution. Frequently, a trade-
off is made depending on the use case of the 
printer. For example, if the printers main use 
is for first draft prints, the user may value 
speed over precise, high resolution parts. 
Equally, if the printers main use is for final 
drafts with a complicated series of parts, the 
user may value precision over speed. 
Many printers allow the user to vary the 
resolution of the print through the printer 
software and hardware. The Taz6 by Lulzbot 
has a maximum speed of 7.9" per second, 
but can vary resolution from 0.002" to 0.2" 
through the Cura software. The Ultimaker 2+ 
is actually capable of ranging the speed from 
1.18" to 11.8" per second, with a resolution 
range of 0.002" to 0.023", because of their 
unique hardware. Swappable print nozzles 
enable the printer to adjust the resolution of 
the print so drastically.
Another simpler factor that affect the print 
speed is the design of the part. If a part has 
a hollow center or thin interior supports, it 
will take much less time than a solid print. 
Additionally, parts that are shorter and wider 
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typically print faster than taller and thinner 
parts due to a combination of print head 
acceleration over time and decreased layers.
TINKERING
One of the simple pleasures of 3-D printing 
is how it enables tinkerers. Open-source 
hardware and user upgrades create unique, 
custom 3-D printers completely characteristic 
to the user. 
Open-source hardware is a highly unique 
feature to the 3-D printing industry, as users 
can print backup parts for their machine. For 
example, Lulzbot printers are largely made 
up of parts that are created through 3-D 
printing. Lulzbot provides the printer owner 
the files needed to print their own copies of 
parts so they can print backup copies in case 
of failure. 
Equally exciting, some 3-D printers are 
designed to be taken apart and upgraded. 
Users can buy separate parts to upgrade 
their 3-D printer after purchase. For example, 
Lulzbot sells interchangeable parts to upgrade 
the printer in various ways, such as to add 
a dual head for dual extrusion. On a more 
delicious note, some companies sell upgrades 
that can be used to 3-D print food! 3Drag’s 
printer can be converted from a plastic 
printer to a chocolate printer with a syringe 
needle attachment. 
AUTOMATIC BED LEVELING
Automatic bed leveling, while it sounds 
trivial, is one of the most consequential 
features a 3-D printer can have. In order 
for the print to adhere to the bed properly, 
it must be level and a particular distance 
from the bed. If it is not, the part will not 
adhere to the bed properly, and most times, 
the print will fail. For SLS printers, it is 
important that the bed is level so the laser 
can be calibrated properly to polymerize 
the appropriate amount of material.For 
extrusion printers, it is critical that the 
bed be at the appropriate distance, as the 
moving print head can jam if the bed is too 
close, or fail to stick if the bed is too far 
away. 
When automatic bed leveling is not 
available, the user must level the bed 
manually. Depending on the printer, the user 
might have to calibrate it by hand, or there 
may be some level of assistance provided 
by the printer. For example, the Ultimaker 
2+ has assisted leveling and comes with 
a calibration card. The Zortrax M200 has 
assisted leveling with precise instructions on 
exactly how many turns are needed to level 
the machine. Unfortunately, leveling the bed 
manually can be a frustrating and time-
consuming process, even with assistance. 
Typically, it involves turning screws at three 
or more different locations around the print 
bed until the bed is level.
Alternatively, some printers use a 
combination of dedicated hardware and 
software to automatically level the bed. This 
saves the end user time and a good deal 
of frustration. The Lulzbot Taz6 uses metal 
tabs at the four corners of the build plate to 
calibrate the bed. The print nozzle contacts 
the metal tabs to complete a circuit, which 
is then used to determine the distance 
from the nozzle to the bed. This process is 
repeated for each corner to determine and 
alter the bed height until it is level. The 
Prusa i3 MK2 uses a process called Mesh 
Bed Leveling. This leveling system uses nine 
calibration points combined with custom 
software to create a model of the print bed. 
It uses this model to adapt to a slanted bed 
and any imperfections in the bed itself, since 
even a flat print bed is never perfectly flat. 
Printing speed and resolution are uniquely linked qualities in 3-D printers. 
Often, an increase in speed results in a decrease in resolution, and vice versa. 
Speed of the print can be improved by printing thicker layers, but layer thick-
ness is the main quality that determines resolution.
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COST
3-D printers differ significantly in price 
point. This variation is often due to the scale 
at which they are used: consumer, prosumer, 
professional, and subscription. 
Consumer printers, such as the Prusa i3 
MK2 or Maker Select, are less than $1,000 
and are reliable, but do not necessarily have 
the quality required for product resale. They 
do not typically include product support, but 
instead rely solely on community resources. 
Prosumer printers such as the Taz6 or 
Form2 have a broader price range, from 
$1,000 to approximately $5,000. Though they 
are less financially accessible than consumer 
3-D printers, they are generally more reliable 
and produce higher quality prints. They also 
often have more features, yet still retain 
many of the community resources available 
to the consumer printers. 
Professional 3-D printers, such as the 
uPrint SE Pro, are any printers that cost a 
flat rate of more than $5,000. These printers 
are usually custom-made for specific types of 
additive manufacturing, and have larger print 
beds and more reliable printing; though they 
are rarely open source. 
Subscription-based printers typically 
offer services and vary greatly in pricing. 
Subscription services include warrantees, 
printer support, or even cloud services. For 
instance, NVBots offers a yearly subscription 
service for access to the printer, customer 
service, a library of 3-D models, and a cloud 
resource to monitor and print remotely. 
ADVANCES TO COME
Commercialized 3-D printing technologies 
have come a long way since the 1980s. The 
field is constantly improving, and different 
companies are releasing new, exciting features 
regularly. Whether in a large or a small system, 
the technology that goes into 3-D printers is 
advancing quickly, enabling the production of 
prototypes and models with greater accuracy 
and repeatability than ever before. 
Innovative Holding Solutions
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make annotations throughout each issue.
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We've recently seen a lot of innovation in the 3-D printing industry. Numerous companies are now manufacturing 
affordable desktop 3-D printers. Other companies have begun supplying handy printing-related services 
(e.g., online modeling), printing components, and interesting accessories (e.g., air filtration systems for 3-D 
printers). It's clear that 3-D printers are poised to become essential tools in every engineering workspace, 
university electroncis lab, makerspace, and industrial design facility.
By C. J. Abate
Nicolas Roux 
Founder/CEO | Zimple
www.zimple3d.com 
 
C. J.: Tell us about your background and 
technical interests.
NICOLAS: I am an embedded system 
engineer, with a background in electronics 
and mechanics. I fell in love with 3-D printing 
four years ago, and then I started to make 
some personal projects (RC cars, lights, toys). 
My cofounder, Antoine, is a data scientist 
student passionate by the internet. 
C. J.: How did you get started with 3-D 
printing? A school project? A personal 
project?
NICOLAS: I started to work with 3-D printers 
four years ago, with a Prusa i3. Since my 
childhood, I have always loved making things. 
I have tried all the construction games! After 
my preparatory class, which is a two-year 
intensive program preparing you to pass 
the competitive examination for engineering 
school, I bought my first 3-D printer in order 
to restart making things, with my own ideas 
and designs. Being able to design, print, and 
try something I’ve got in my mind is a huge 
pleasure for me. Since I’ve tried it four years 
ago, I never stopped to make things! 
C. J.: Your company Zimple's focus is "3-D 
printing without toxic emissions." What led 
you to this mission?
NICOLAS: After using a lot of different 3-D 
printers, I found that all of them have some 
problems regarding their use. So with Zimple, 
we want to share the solutions I found to 
counter the problem I’ve been facing with 
my 3-D printers. The fumes released by 3-D 
printers was the biggest problem for me. It 
really smells bad and gives me headache. 
After looking into research on the subject, I 
realized that this issue was really important 
and theses fumes were very harmful. So, tired 
of keeping my window open with my printer 
nearby, I decided to develop a solution. I 
had the idea of this solution: "hoovering" 
the particles directly at the nozzle, because 
I found it more elegant, less expensive, and 
more scalable on my different printers than 
building an enclosure. 
C. J.: It seems logical that the air around a 
working 3-D printer isn't as clean as the air 
in an empty room. But is there hard data on 
the negative effects of exposure to printer-
related toxins? 
NICOLAS: Many studies about the emissions 
when processing thermoplastic are available 
on the Internet. The results are unambiguous: 
Advances in 3-D Printing and 
Related Technologies
Q&As with Industry Innovators
http://www.zimple3d.com
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they are very toxic and released in huge 
amounts. After talking with many people 
around the 3-D printing industry and the 
thermoplastic ecosystem, we realized that 
this problem is known by every professional. 
They are all aware of the fumes released by 
the fusion of thermoplastic, and so they use 
big and powerful exhausting systems when 
melting plastic. Desktop 3-D printing is a 
very new technology. It’s the first time that a 
real manufacturing machine can be placed in 
a living room, on a desktop near an engineer, 
or in a schoolroom. And this is the problem: 
people tend to forget that 3-D printers are real 
manufacturing boxes and not computers. The 
technology will reach the point where everyone 
will be able to use it as we use photocopiers, 
but even photocopiers have a particle filter 
inside it. It’s just a question of time before all 
3-D printers will have a built-in filter.
C. J.: Tell us how you came to develop 
Zimpure, which is a compact air filtering 
system. In terms of engineering, what 
were the biggest problems associated with 
designing the system?
NICOLAS: With Zimpure we wanted to develop 
an efficient and compact filtering system. The 
two main challenges in terms of engineering 
were: First, to find a way to exhaust all the 
gases and particles, without using a huge and 
loud exhausting fan. Then, to use the filter that 
will be able to filter all the nanoparticles and 
gases released. Testing these two points isn’t 
easy, because you can’t see the particles. Even 
if the ABS smell disappeared when we were 
turning on Zimpure, we wanted to know how 
efficient it was on both issues: nanoparticles 
and gases. To do so, we’ve collaborated 
with a laboratory (CEA) in the Laboratory of 
Climate and Environment Science department 
(LSCE). They kindly provide us the measuring 
instruments we need to conduct our tests. 
After testing our prototype, we improved it to 
reach our goal: a 99% particle filtration ratio 
and more than 90% for the gases. We are now 
proud of, and confident in, our product, and 
we rely on it every day in our office and home. 
C. J.: Give us an overview of Zimpure. Tell 
us more about what it does and its benefits.
NICOLAS: So Zimpure is a very compact (160 
× 120 × 124 mm) and silent (around 50 dB, a 
bit less than some printers). And it's a really 
efficient exhausting and filtering system. (It 
filters 99% of the particles and more than 
90% of the gases released while printing.) It 
is also a very affordable product. We sold it 
Zimpure Delta
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for $108 (€99) on Kickstarter. The final price 
is $162.80 (€149). The enclosure or cover we 
can buy costs between $273 and $327. That’s 
not possible for many of us. That’s why we 
choose to make Zimpure more affordable.
C. J.: Compatibility with the many 3-D 
printers on the market could be a problem. 
How are you dealing with compatibility?
NICOLAS: Our Zimpure is the same for all the 
3-D printers. The only change concerns the 
suction head, because printers don’t have 
exactly the same extruders. That’s why the 
users will print themselves their suction head, 
depending on their printer. Being able to ask 
our customers to print a custom part gives 
our project an affordable cost. It also connects 
us to our community in a very pleasant way. 
We can talk about the emission issues and 
compatibility design. We love it! Community is 
the strength of 3-D printing. We are designing 
and testing suction heads for a lot of 3-D 
printers. The final user will be able to download 
his own suction head on our website. He will 
just have to print it and Zimpure will be ready 
to clean! Many 3-D printer users are designers 
or engineers, so we think they will probably 
adapt or even improve our suction heads for 
their specific needs. We will share some CAD 
files in order to make them easier to modify. 
C. J.: You exceeded your Kickstarter goal in 
April 2017. What are your plans now?
NICOLAS: We are currently running our 
production—a batch of 500 Zimpures. When 
it is, done we will go in different fab labs and 
resellers to test new suction heads on other 
3-D printers and to present our product. We 
will send all the Zimpure units before the end 
of June 2017 for sure. Some backers will even 
receive it by the end of May. 
C. J.: Any new products in the pipeline?
NICOLAS: Zimpure is going to evolve this year, 
and two other products are coming. 
C. J.: Where do you see the 3-D printing 
industry going in the next five to 10 years?
NICOLAS: 3-D printing is going to be more 
and more used by everyone in society. 
Personal 3-D printers will maybe take longer 
to come up, but we think everyone will be able 
to access them and more and more products 
using the technology will appear. 3-D printing 
is a disruptive technology that enables us to 
mass produce custom products. It will be 
used more and more for production purposes 
and not only prototyping. 
Jeff Moe 
Founder/CEO | Aleph Objects
www.alephobjects.com
 
C. J.: When did you first become interested 
in 3-D printing?
JEFF: I became interested in 3-D printing 
when I learned about the RepRap project that 
started at the University of Bath, in England, 
and quickly spread into a global collaborative 
movement. RepRap hardware development 
worked similarly to Free Software 
development, with individuals around the 
world building and modifying 3-D printers 
and sharing what they learned.
C. J.: What was your first 3-D printing 
project?
JEFF: In 2010, I ordered an open-source 
hardware ShaperCube kit from RepRap Source 
out of Germany. There was an enormous 
number of parts, and it was a challenge to 
assemble, but it worked more or less.
C. J.: What about the most recent object you 
printed for yourself (not work related)?
http://www.alephobjects.com
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JEFF: Given that I own a 3-D printer 
manufacturing company, I don’t print a whole 
lot of things that aren’t work related in some 
way. But recently, I did design and print a 
mount for a webcam at my house. 
C. J.: Tell us about Aleph Objects. Why'd you 
start the company in 2011?
JEFF: I founded Aleph Objects because I saw 
an opportunity for open-source hardware 
to be as successful and influential as Free 
Software projects such as GNU/Linux and 
Wikipedia. The community and momentum 
that was building around 3-D printing was 
unlike anything that I had seen in hardware 
before. Arduino had an active community, 
and it enabled the RepRap project to get off 
the ground, but RepRap brought open-source 
hardware to a much larger audience. 
C. J.: Why open source?
JEFF: Free software, Libre Innovation, and open-
source hardware are all about respecting user 
freedom. Things you buy should not spy on you, 
restrict your use, or impede you from learning 
how they work. By respecting the individual’s 
right to understand how their 3-D printer 
works, we build a collaborative community that 
shares these values. In turn, that community 
collaborates, sharing improvements and 
modifications to their hardware, which helps us 
iterate and bring innovations to market faster. 
To that end, we share everything, from CAD 
files to Bills of Materials to the layout of our 
manufacturing floor.
C. J.: Can you tell us a bit about the main 
customers for your LulzBot Mini? Are they 
mostly home users or perhaps architects 
and engineers?
JEFF: The LulzBot Mini was conceived as a 
less expensive, easier-to-operate sibling to 
the LulzBot TAZ, aimed at new users and 
people with smaller budgets. But read the 
reviews, and you’ll learn that the LulzBot 
Mini is just an all-around great 3-D printer. 
It’s fast, versatile, portable, and incredibly 
reliable. So, while our target audience of 
home users, teachers, and libraries has been 
happy with their LulzBot Minis, we also sell 
them to engineers, architects, researchers, 
and manufacturing startups. In our own 
LulzBot 3-D printing cluster that we use to 
manufacture parts for our assembly line, over 
half of the machines are LulzBot Minis.
C. J.: You announced the LulzBot TAZ 
MOARstruder Tool Head at the 2017 
Consumer Electronics Show (CES). What has 
LulzBot TAZ
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been the feedback from users since then?
JEFF: We’ve heard a number of times that 
it’s like having a brand new bigger printer. 
It enables people to utilizethe TAZ’s whole 
build volume without tying up their printer for 
days. We are seeing more robust functional 
printed components as well. Plus, it’s just fun 
to watch that much plastic moving through 
the extruder and seeing those big layers 
stacking up. You feel closer to the process 
because you can really see your part taking 
shape. 
C. J.: When developing the MOARstruder, 
what was your main focus? Enabling higher 
printing speed? Higher output? Object 
strength?
JEFF: We called it the MOARstruder because 
it enables all of those things, but speed was 
the primary development driver. The TAZ 6 is 
huge, but because full-volume prints can take 
so long, it’s not always convenient to utilize 
the whole build volume. With the MOARstruder 
that equation changes dramatically. The 
increased speed is a function of larger and 
wider extrusion, which in turn makes the 
parts printed with the MOARstruder much 
stronger. The strength improvements alone 
are reason enough to buy one.
C. J.: Can you tell us about any new products 
in the pipeline?
JEFF: Of course. We are nearing a beta 
release of Cura 2 LulzBot Edition software. 
Cura 2 has a lot of new 3-D printing features, 
an improved interface, and better slicing 
performance. Aleph Objects is also funding 
development of a new elementary/beginner 
interface for Blender called “Blender 101,” 
which will make the software more suitable 
for those just starting in 3-D. On the 
hardware front, we are working on a next-
generation 3-D printer, code-named Athena. 
Athena is being developed after months of 
research into state-of-the-art open-source 
3-D printing technology and will feature all-
new electronics, extruders, and hot ends 
developed collaboratively with partners 
around the globe. We’re always looking at 
ways to improve printing with our current 
hardware too. Look for future upgrades to 
our heated bed design, hot ends, and other 
upgrades to LulzBot TAZ and Mini 3-D printers. 
We share all of our hardware research and 
development projects on a public server that 
is updated every half hour here: devel.lulzbot.
com and software development here: code.
alephobjects.com.
C. J.: Where you do see the most opportunity 
for the company's growth? The personal or 
industrial 3-D printing market?
JEFF: Poor-performing, closed-source 
machines that flooded the market seem to 
have cooled the hype that formed around “a 
3-D printer in every home.” Plus, there are 
now Chinese-made printers available for just 
a couple hundred dollars and we have no 
intention of competing in that pricing tier. 
That said, our customer split is still close to 
50/50 between personal and professional use. 
Cheaper machines can serve to open one’s 
eyes to the potential, but don’t perform well 
enough to live up to it. So, a LulzBot printer is 
often someone’s second or third 3-D printer 
purchase, when they’re fed up with the lack of 
reliability from lower-quality machines. Our 
Athena project is definitely targeted more 
at the professional and industrial end of the 
market as that is where we anticipate more 
growth will happen over the next several 
years. 
C. J.: Have you seen any new and exciting 
applications for 3-D printing? For instance, 
are any of your customers doing surprising 
things with LulzBot printers?
JEFF: Our customers are constantly surprising 
us. From NASA engineers hacking a TAZ to 
print high-temperature aerospace plastics 
to a company printing rugged dirt bike 
motorcycle parts. One customer that has 
gotten viral attention recently is Hyperflesh, 
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out of Denver, Colorado. They make hyper-
realistic silicone masks of celebrities and 
politicians, using a LulzBot TAZ to print the 
molds.
C. J.: Where do you see the 3-D printing 
industry going in the next five to 10 years?
JEFF: A lot has changed in this industry since 
we started up in 2011. Quality and speed 
have improved, prices have come down, 
material selection has grown exponentially, 
and I would expect these trends to continue. 
We have also seen a continual shift toward 
more open development. The most popular 
3-D printers in the world are or are based 
on open-source designs, and free slicing 
and printing software dominates. Even 
traditionally secretive companies are 
dabbling in less restrictive development, 
like HP allowing third-party material 
development for their new machines. With 
collaborative development leading the way, 
innovation will continue to accelerate.
C. J.: Which industry (e.g., medical, 
aerospace, automotive) stands to benefit 
the most from advances in 3-D printing and 
why?
JEFF: While they all stand to benefit 
tremendously, medical applications seem likely 
to be the most disruptive. Current generation 
LulzBot 3-D printers print with thermoplastics 
only, so our exposure is limited to external use 
medical applications. Nonetheless, there are 
already amazing things being printed with 
LulzBot printers in the medical field. Custom 
3-D-printed prosthetics can save people 
thousands of dollars over traditionally 
fabricated prosthetics. 3-D-printed surgical 
reference models can lead to improved surgical 
outcomes. In the greater 3-D printing field, 
exploration of 3-D printing implants, grafts, 
drugs, and even organs is compelling. 
www.cc-webshop.com
www.elprotronic.com
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3D Hubs
• Location: Amsterdam, Netherlands
• Web: www.3dhubs.com
• Business: The 3D Hubs platform connects 
users with local 3-D printing services. 
It checks a user’s digital design and its 
matchmaking algorithms optimizes 3-D 
print options. To use 3D Hubs, customers 
upload a 3-D design, choose a material, 
and select a 3-D printing service.
• Services: Rapid Prototyping, Additive 
Manufacturing, 3-D Printing for Education
3D Slash 
• Location: Paris, France
• Web: www.3dslash.net
• Business: 3D Slash's mission is to make 
3-D printing accessible to everyone. It 
offers a handy 3-D modeling tool. Users 
create their models by "slashing a cube." 
• Products: 3D Slash Modeling Tool
Airwolf 3D
• Location: Costa Mesa, CA, USA
• Web: www.airwolf3d.com
• Business: Designs highly accurate, high-
speed desktop 3-D printers for engineers, 
hobbyists, and students alike. 
• Products: AXIOM Printers and Apex 3D 
Printing Software
Axis Prototypes
• Location: Toronto, Canada
• Web: www.axisproto.com
• Business: A 3-D printing service bureau 
that creates accurate prototypes directly 
from digital files and delivers them 
within a few days in North America. It 
also distributes the latest in 3-D SLA 
printers based on digital light processing 
(DLP) technology.
• Products: 3-D Printing and Prototyping 
Services
Resources for Cutting-Edge 3-D 
Printing & Related Products
BCN3D Technologies Sigma 3-D printer
http://www.3dhubs.com
http://www.3dslash.net
http://www.airwolf3d.com
http://www.axisproto.com
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BCN3D Technologies
• Location: Barcelona, Spain
• Web: www.bcn3dtechnologies.com
• Business: BCN3D manufactures 
open-source 3-D printers. Its IDEX 
(Independent Dual Extruder) system 
works with multi-material, multicolor 
prints and support structures. 
• Products: BCN3D Sigma 3-D Printer, 
BCN3D Ignis Laser Cutting Machine, Kit 
BCN3DR Open-Source 3-D Printer, BCN3D 
Sigma and Simplify3D Software, Sigma 
Progen
BigRep
• Location: Berlin, Germany
• Web: www.bigrep.com
• Business: BigRep aims to revolutionize 
3-D printing and manufacturing. Its 
BigRep ONE and BigRep Studio enable 
large-scale 3-D printing.
• Products: BigRep ONE 3D Printer, BigRep 
Studio 3-D Printer, and Polymers for 3-D 
Printing Applications
byFlow
• Location: Eindhoven, Netherlands
• Web: www.3dbyflow.com
• Business: Manufactures a foldable, 
portable 3-D printer
• Product: Focus Portable 3-D Printer
colorFabb
• Location: Belfeld, Netherlands• Web: www.colorfabb.com
• Business: colorFabb develops high-
quality filaments for FDM 3-D printing. 
It offers a wide range of 3-D printing 
materials that are well suited for most 
FDM 3-D printers. 
• Products: PLA/PHA and Co-Polyester-
Based Materials for FFF/FDM 3-D Printing
Fargo 3D Printing
• Location: Fargo, ND, USA
• Web: www.fargo3dprinting.com
• Business: Fargo 3D Printing provides 
3-D printer sales, service, support, and 
education to businesses, educational 
institutions, and individuals.
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CIRCUIT CELLAR • JUNE 2017 #32350
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MakerBot Industries, LLC
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Rize, Inc.
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CIRCUIT CELLAR • JUNE 2017 #32352
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THE CONSUMMATE ENGINEER
Automatic Control (Part 2) 
Last time, George covered the basic 
principles of automatic control, including 
a simple closed-loop control system, 
common control laws, and proportional 
system shortcomings. This month, he 
focuses on frequency domain analysis.
By George Novacek 
In Part 1 of this series, we discussed automatic control systems in general. Let’s 
step back a little now and take a quick look 
under the hood of control theory. The widely 
used frequency domain analysis represents 
classic control theory, which is intuitive 
to those of us who design analog circuits. 
The same principles apply to all feedback 
electronic circuits: oscillators, amplifiers of 
all kinds, phase-locked loops, voltage and 
current regulators, and so on. This series, 
however, focuses on automatic systems 
containing mechanical components.
It begins with Laplace transform: 
F(s) = f(t)e dtst
0
−∞∫
The function f(t) is a function of time. s is 
the Laplace operator. F(s) is the transformed 
function. Typical Laplace transfer functions 
are 1/s for integration. s for differentiation. 
e—sT is for delay and so forth. Let’s say, 
for example, that an input signal into an 
integrator vi(t) generates output vo(t). Using 
the Laplace transformation, we can write:
V (s) = V (s)
so
i
The Laplace operator s is defined: 
s + j≡ s w
This means that s is a complex variable. As 
we know, j is the imaginary variable defined 
as √–1. In electrical engineering, we prefer j 
instead of i common in mathematics because 
i often designates immediate current. Omega 
w is the sign for circular frequency, which 
equals to 2πf. Because control systems’ 
analyses investigate steady-state sinusoidal 
signals, s is zero. Consequently, we can write:
s = j2 fπ
It is obvious that for a DC signal where f is 
0, the resulting s is 0. Every circuit designer 
knows that the gain of a differentiator or a 
high-pass filter at DC is zero. An integrator, 
on the other hand, would be approaching 
infinity at f > 0 limited by saturation or by 
attenuation for a low-pass filter.
The frequency domain analysis of a 
system is valid for a range restricted to where 
the system is linear and time invariant (i.e., 
the LTI range). For a system to be considered 
LTI, three conditions must be satisfied. 
Homogeneity: An element is homogenous for 
the values of k where an input r(t) produces 
output c(t), and then an input k × r(t) produces 
output k × c(t). Superposition: If an input r1(t) 
Frequency Domain Analysis
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produces output c1(t) and input r2(t) produces 
output c2(t), then input r1(t) + r2(t) = c1(t) + 
c2(t). Time invariance: If r(t) generates c(t), 
then r(t – τ) mustgenerate c(t – t) for all t 
> 0.
These severe restrictions can be satisfied 
within a limited range only. Therefore, our 
design must come to LTI requirements as 
much as possible. This is not an unusual 
problem in engineering, including electronics. 
No components (e.g., resistors, capacitors, 
and inductors) are purely resistive or reactive. 
They all contain parasitic components of the 
other types, but competent engineers know 
how to select them so that the effects of those 
parasitic characteristics can be ignored within 
the operational range. Active components 
also have limitations including saturation. We 
must build amplifiers and other processing 
circuits with sufficient headroom to make 
them behave as LTI within the required scope.
With some notable exceptions, well 
designed electronics are rarely the LTI limiting 
component. Those exceptions are usually 
within the plant characteristics where size, 
weight and cost limitations may encroach on 
some electronic components’ LTI.
I already mentioned transfer functions 
of controller elements (i.e., an integrator, a 
differentiator, and a delay). Given voltage V 
and current I, let’s consider some transfer 
functions of electronic components. 
Inductance L: 
V(s) = Ls I(s)
v(t) = L di(t)
dt
×
×
Capacitance C: 
V(s) = 1
C
 I(s)
s
v(t) = v + 1
C
i(t)dt0
×
∫
Resistance R:
V(s) R I(s)
v(t) R i(t)
= ×
= ×
Many transfer functions applying to 
mechanical elements (e.g., velocity, mass, 
spring, inertia, and pressure) have equivalents 
in electronics. While common transfer 
functions are available in books on control 
systems, others may have to be determined. 
The Circuit Cellar readers are mostly electrical 
engineers, so they can relate to transfer 
functions of the electrical components 
FIGURE 1
Bode plot of gain (a) and phase (b) trace with different damping factor a versus the frequency of a second-
order system.
ABOUT THE AUTHOR
George Novacek is a professional engineer 
with a degree in Cybernetics and Closed-
Loop Control. Now retired, he was most 
recent l y pres ident o f a mu l t inat iona l 
manufacturer for embedded control systems 
for aerospace applications. George wrote 26 
feature articles for Circuit Cellar between 
1999 and 2004. Contact him at gnovacek@
nexicom.net with “Circuit Cel lar ”in the 
subject line.
a) 
b) 
CIRCUIT CELLAR • JUNE 2017 #32354
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mentioned above. Mechanical components, 
unfortunately, are seldom as intuitive to us. 
In a perfect world the electronic controller 
designer should be given the required gains 
and limits, while leaving the selection, design 
and characterization of the control system 
and its components to mechanical engineers. 
But that doesn’t always happen.
With the help of the transfer functions the 
response of a control system can be calculated. 
In the frequency domain analysis we use 
sinewave, because it is the only waveform that 
does not change its shape in an LTI system. 
Using sinewaves does not cause a problem 
because, thanks to M. Jean-Baptiste Joseph 
Fourier we know that any waveform shape 
can be generated by a series of sinewaves. 
Therefore, the response of an LTI system 
can be characterized by investigating the 
gain and the phase of its frequency response 
also referred to as the Bode plot. This can 
be accomplished by calculations, computer 
simulation or measurement and graphically 
displayed. 
Figure 1 is a Bode plot of a second-order 
system with resonant frequency f = 10 Hz 
and critical and low damping factors a, often 
designated by x. Such a system’s response is 
defined as:
f(s) 
s 2 
2
2 2= + × × × +
w
x w ws
In this instance, w = 2pf. x is the damping 
coefficient and s is the Laplace operator. Both 
circuitcellar.com/ccmaterials
RESOURCES
G. Ellis, Control System Design 
Guide, Elsevier Academic 
Press, 2002.
B. C. Kuo, Automatic Control Systems, Prentice 
Hall, 2009.
G. Novacek, “Electro-Hydraulic Servo Valves,” 
Circuit Cellar 253, 2011.
Wikipedia, Nyquist Stability Criterion, 
https://en.wikipedia.org/wiki/
Nyquist_stability_criterion.
FIGURE 2
Combining the forward and the feedback 
transfer functions into one OLG G(s)
H(s)
C(s)R(s)
+
−
R(s)
G(s)
C(s)1 + G(s)H(s)
FIGURE 3
OLG Bode plot of a controller
www.circuitcellar.com/ccmaterials.
https://en.wikipedia.org/wiki/
Nyquist_stability_criterion
circuitcellar.com 55
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the gain and the phase responses are affected 
by the damping factor x. 
Being from the slide ruler generation I 
must admit that I never enjoyed making those 
calculations. So quite often we minimized 
the number of calculations by generating 
asymptotes only. Anything more than a 
second-order system response calculation 
used to be nearly impossible, but thanks to 
computers, the Bode plots can nowadays 
be generated very quickly by the multitude 
of simulation or mathematical tools such as 
PSpice, LTSpice, Matlab, Mathcad, Simulink 
and others.
To analyze automatic systems in frequency 
or time domain, we start by defining it by a 
block diagram. The functional blocks (there 
can be many) are gradually combined into a 
single block to obtain the transfer function 
of the system. Figure 2 shows just two 
blocks, the forward and the feedback paths 
for simplicity. To check for stability the gain 
and the phase are plotted with the feedback 
disconnected. This is called an open loop gain 
(OLG).
The result will be something like the Bode 
plot in Figure 3. This one is the OLG response 
of the analog electronic controller shown in 
Part 1 with an actuator. I spread the plot 
frequency until the phase reached 180° to 
illustrate the phase and the gain margins.
The OLG vs. frequency is shown in decibels 
(dB) and the phase in degrees. The main point 
of interest for us to judge the potential for 
unwanted oscillations is where the phase 
reaches –180° while the OLG is greater than 
0 dB. In our case, the phase at 0 dB OLG is 
–89°. This means that the phase margin is 
180 – 89 = 91°. Another point of interest is 
where the phase reaches -180°. The OLG here 
is -29dB, thus the gain margin is 29dB. If the 
OLG was greater than 0dB when the phase 
reached 180° the system would oscillate after 
closing the feedback loop. The large phase 
and gain margins of Figure 3 will guarantee 
no oscillations, but will not guarantee a 
possibility of instability, namely in response 
to a step input. Automatic systems are rarely 
exposed to a step in the setpoint, but a step 
input may be due to an external disturbance. 
We shall address that issue when we discuss 
the time domain response.
In many electromechanical systems the 
plant, due to its inertia, stops responding 
above certain, fairly low frequency. This is 
not unusual. However, the bandwidth of the 
electronic controller should always be at least 
ten times the fastest component in the plant.
To complete our excursion into the 
frequency domain analysis we must mention 
the Nyquist plot also used for assessing the 
system stability. Figure 4 shows the plots 
related to the frequency, phase and damping 
illustrated by Figure 1 and defined by 
Equation 8. Nyquist contour is a parametric 
plot of the frequency response of a system 
transfer function with the feedback closed. 
The real and the imaginary parts of the 
transfer function are plotted in Cartesian 
coordinates with the real part on the x-axis 
and the imaginary part on the y-axis, with the 
frequency as a parameter. 
The system stability is assessed using the 
Nyquist Stability Criterion. It is determined by 
evaluating the Nyquist contour in relation to 
the point at x = –1 and y = 0. Next month 
we’ll discuss time domain analysis and digital 
systems using z transform. 
FIGURE 4
Nyquist contours for the critically (left) and under damped (right) system described by Equation 8
CIRCUIT CELLAR • JUNE 2017 #32356
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GREEN COMPUTING
High-performance chips have significant heat generation 
variations across theirvarious microachitectural and 
circuit blocks. This article argues that hybrid and 
heterogeneous cooling methods that tackle the “hot 
spots” locally and use efficient cooling methods to remove 
the background heat offer the potential to substantially 
improve power efficiency.
By Ayse K. Coskun
High temperatures on chips have been among the primary limiting factors in 
building and running high-performance 
processors. This is because high 
temperatures adversely affect reliability and 
increase leakage power consumption. Rising 
temperatures have been getting even more 
attention recently in tandem with aggressive 
technology scaling, which has resulted in high 
power densities (i.e., high power consumption 
per area). 
As processor manufacturers continue to 
pack more functionality into a single chip, 
maintaining safe temperatures becomes even 
more challenging. In the next generation 
processors targeting “exascale computing,” 
power densities of 1 to 2 kW/cm2 are 
anticipated. For example, IBM’s recent work on 
two-phase cooling introduces a new method 
to handle such high power densities.[1]
Another thermal challenge with future 
high-performance chips is that heat 
generation across a processor die is 
significantly heterogeneous. While one corner 
of a circuit block may reach extremely high 
power densities, others may operate at much 
more moderate power levels. Consequently, 
chips often exhibit very high temperature 
peaks that are localized. In fact, one can 
find in the literature many thermal maps 
(e.g., constructed via infrared cameras) 
that demonstrate the heat heterogeneity in 
various modern real-world processors.
While heat generation is highly 
heterogeneous and it is expected to become 
even more visibly heterogeneous in future 
processors, cooling subsystems are generally 
homogeneous—meaning that the cooling 
infrastructure on a chip typically has the 
same cooling capability across the chip and it 
is built using a single cooling technology. This 
homogeneous design of the cooling subsystem 
causes cooling inefficiencies (under- or over-
cooling) for chips with spatially heterogeneous 
heat profiles.
There are a number of advanced cooling 
methods that have been developed in the recent 
years following the growing significance of 
efficient thermal management. These cooling 
methods, including liquid cooling, two-phase 
cooling, thermoelectric coolers (TEC), the use 
of phase-change materials (PCMs) on chip or 
on package, and others, have rather distinct 
response times, efficiencies, or granularities. 
For example, while TECs are great in reducing 
the temperatures of local hot spots rapidly, 
using a large number of TECs on chip may 
cause prohibitively high cooling power as 
TECs are “active” devices that consume 
energy to provide cooling. Liquid cooling 
achieves efficient heat removal, but typically 
the operational settings of pumps (that push 
the liquid) can be changed in the order of 
hundreds of milliseconds or seconds; thus, 
On the Potential of 
Hybrid Cooling
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this granularity may hinder effective rapid 
thermal management. Generally speaking, 
a single cooling solution that is able to 
efficiently optimize cooling for any arbitrary 
chip does not exist; so, one needs to consider 
the tradeoffs in response time, cooling power, 
overall efficiency, and others while selecting 
the best cooling method for a given system.
Can we combine different cooling methods 
together to maximize the energy efficiency 
of heat removal? By putting together the 
strengths of different cooling methods, it 
may be possible to design systems whose 
efficiency substantially surpasses that of 
the systems designed today. The rest of this 
article discusses “hybrid cooling” strategies 
that integrate multiple cooling methods on a 
given system, often in a heterogeneous way 
across the chip (i.e., using different cooling 
devices or geometries on different parts of 
the chip), so as to address the differences in 
heat generation.
ADVANCED COOLING SOLUTIONS
The idea of hybrid cooling can apply to 
many cooling methods. For example, one 
can consider putting together a conventional 
heat sink with a liquid-cooled cold plate. Or 
modern data centers that combine in-row 
liquid coolers with conventional fans and heat 
sinks at the server level could be considered 
as early adopters of hybrid cooling. In this 
article, I will specifically focus on hybrid 
cooling on the chip because removing the 
generated heat directly on the chip can 
enable dramatically pushing the performance 
limits imposed by the critical temperature 
thresholds on chips. I will discuss hybrid 
and heterogeneous integration of several 
advanced cooling methods together, including 
TECs, liquid cooling, and PCMs.
A TEC operates based on the Peltier effect 
such that when current passes through the 
TEC device, heat is absorbed from one side 
(cold side) and rejected to the other side (hot 
side), creating a thermal gradient across 
the two sides. Superlattice-based thin film 
TECs are compatible with silicon fabrication 
and can be directly integrated on the back 
of a silicon chip. Existing on-chip TEC devices 
are composed of ultrathin (5 to 10 µm) 
thermocouples sandwiched between copper 
and they are covered with ceramic insulator 
plates at the outmost surfaces. The cooling 
ability of a TEC is dependent on the applied 
current: typically, the higher the current, the 
higher the cooling ability. While TECs can 
provide rapid reduction of temperature on 
local hot spots, larger TEC sizes can easily 
become too costly in terms of the cooling 
power (as more current needs to flow). 
Liquid cooling can remove heat from 
chips more efficiently compared to air 
cooling. Liquid-cooled cold plates or applying 
liquid cooling at the racks/data center are 
already in use in modern data centers or 
high-performance computing clusters. An 
emerging advanced liquid cooling method 
is etching hannels on the backside of a chip 
or placing microchannels in between the 
stacked dies in a 3D-stacked system. (Refer 
to my Circuit Cellar 284 article on “Greener 
Cooling.”) Liquid cooling is ideal for removing 
the background heat and its efficiency 
increases for more uniform heat distributions 
on the chip. Otherwise, in case of large local 
hot spots, liquid flow rate and/or channel 
dimensions need to be adjusted to handle the 
worst-case hot spot. Thus, such cases result 
in over-cooling of the lower-power areas of 
the chip and higher pump power.
TECs and liquid cooling are both “active” 
cooling methods, which means they require 
external power to cool the chip. A passive 
emerging cooling method is using PCMs 
on chip. PCMs (such as cerrobend, gallium, 
or mixes of PCMs with metal to increase 
conductivity) absorb large amounts of heat 
FIGURE 1
An example hybrid cooling solution includes placing TECs on the hot spots and then removing the background 
heat of the chip using microchannel-based liquid cooling. In this way, one can reduce the total cooling power 
required and/or achieve higher performance.
ABOUT THE AUTHOR
Ayse K. Coskun (acoskun@bu.edu) is an associate 
professor in the Electrical and Computer 
Engineering Department at Boston University 
(BU). She received MS and PhD degrees in 
Computer Science and Engineering from the 
University of California, San Diego. Coskun’s 
research interests broadly include energy-
efficient computing and intelligent management 
of computing systems, from mobile devices to 
data centers. She worked at Sun Microsystems 
(now Oracle) in San Diego, CA, prior to her 
current position at BU. Coskun was an associate 
editor of the IEEE Embedded Systems Letters, and currently serves as an 
associate editor for the IEEE Transactions on Computer Aided Design.
mailto:acoskun@bu.edu
CIRCUIT CELLAR • JUNE 2017 #32358
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during phase change (i.e., during melting) 
and create an opportunity to burn high power 
for a limitedtime without increasing the 
temperature. Fulya Kaplan and Charlie De 
Vivero’s 2015 article, “Hardware Testbed with 
Phase Change Material-Based Cooling” (Circuit 
Cellar 298), discusses PCM-based cooling.
HETEROGENEOUS COOLING
Can we optimize the design and operation of 
these chip-level cooling methods to efficiently 
address the heat generation heterogeneity on 
chips? For example, for PCM, it is possible to 
design a mechanism to track which part of 
the PCM has melted already and, then, send 
more load to computational cores that are 
under un-melted PCM blocks (assuming PCM 
is contained in a metal mesh and does not 
flow across the chip when melted/in liquid 
form). Fulya Kaplan’s 2016 article, “Adaptive 
Sprinting” (Circuit Cellar 316), provides the 
details of such an approach.
In the case of liquid cooling, water flowing 
through the microchannels from the inlet to 
the outlet carries the heat and, consequently, 
warms up along the way. Thus, placing 
high-power-density microarchitectural units 
closer to the inlet can achieve more even 
temperatures on the chip. Alternatively, it is 
possible to modulate microchannel dimensions 
to balance spatial heat distribution (e.g., the 
“GreenCool” method[2] designs channels 
that are wider at the inlet and narrower at 
the outlet to balance on-chip temperatures). 
Placing TECs at specific hot spot locations 
(as opposed to placing a symmetric array 
of TECs) is another way to reduce the heat 
heterogeneity on a chip.
HYBRID COOLING
Above, I briefly discussed how a single 
cooling method can be optimized to address 
heat generation heterogeneity (in other 
words, to balance temperature) on chips. 
In my research group, my students and I 
have recently been working on quantifying 
the benefits of combining different cooling 
methods together. In this way, our goal is 
to dramatically raise the energy efficiency of 
high-performance systems.
Specifically, we have recently explored 
putting together TECs and liquid cooling.[3] 
Figure 1 demonstrates a sample hybrid 
cooling solution, where TECs are placed on top 
of the hot spots and liquid cooling removes 
the background heat, which is more uniformly 
distributed after the placement of the TECs, 
from the chip.
Such an integration of TECs with liquid 
cooling can reduce the total cooling power 
that is needed to cool down a particular 
power density value for a given system. 
Figure 2 shows a mock diagram of how hybrid 
cooling improves cooling efficiency. This 
cooling efficiency improvement also enables 
achieving higher performance or surpassing 
the performance limits imposed by high 
temperatures (i.e., a chip cannot operate at 
a temperature above a manufacturer-defined 
critical threshold and, therefore, throttles 
down the power upon reaching such a 
threshold). In other words, a larger amount of 
computational load can be run without hitting 
the critical thermal thresholds when cooling 
is more efficient. In this way, a system’s 
throughput per watt could substantially 
increase.
FIGURE 2
Hybrid and heterogeneous cooling can cool a given heat flux using a lower amount of cooling power. This 
superior cooling ability results from tackling thermal hot spots locally where they are generated. In other 
words, in this way one can design a heterogeneous cooling subsystem that matches the heat heterogeneity 
on a chip. 
circuitcellar.com/ccmaterials
References
[1] M. Schultz, F. Yang, E. 
Colgan, et al, “Embedded 
Two-Phase Cooling of 
Large Three-Dimensional 
Compatible Chips with Radial 
Channels,” ASME Journal of 
Electronic Packaging, 138, no. 2, 
2016.
[2] M. M. Sabry, A. 
Sridhar, J. Meng, A. K. Coskun, and D. 
Atienza, “GreenCool: An Energy-Efficient 
Liquid Cooling Design Technique for 3D 
MPSoCs Via Channel Width Modulation,” IEEE 
Transactions on Computer-Aided Design of 
Integrated Circuits and Systems, vol.32, no.4, 
2013.
[3] F. Kaplan, S. Reda, and A. K. Coskun, “Fast 
Thermal Modeling of Liquid, Thermoelectric, 
and Hybrid Cooling,” Intersociety Conference 
on Thermal and Thermomechanical 
Phenomena in Electronic Systems (ITherm), 
2017.
[4] D. F. Hanks, Z. Lu, S. Narayanan, et 
al, “Nanoporous Evaporative Device for 
Advanced Electronics Thermal Management,” 
Intersociety Conference on Thermal and 
Thermomechanical Phenomena in Electronic 
Systems (ITherm), 2014.
www.circuitcellar.com/ccmaterials
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An important challenge in experimenting 
with hybrid and heterogeneous cooling 
is regarding thermal modeling. A system 
designer needs to be able to model different 
cooling models together and simulate them 
under realistic system, architecture, and 
application assumptions in reasonable 
simulation time. Existing “compact” models 
that allow fast thermal evaluation, however, 
typically contain models for only one type of 
cooling. Using detailed accurate multi-physics 
simulators, on the other hand, is substantially 
time consuming: setting up a hybrid cooling 
model requires expertise and running these 
models can take days when simulating large 
systems.
In my research group, we put together 
compact models that enable modeling TECs 
and liquid cooling together.[3] We integrated 
our modeling approach in commonly used 
thermal simulators, which can be connected 
with microarchitectural performance and 
power simulation as well. Our modeling 
approach is several orders of magnitude 
faster than multiphysics simulators (such 
as COMSOL) and achieves similar accuracy 
overall, reaching 2° to 3°C maximum error in 
rare cases.
Figure 3 shows some example results 
that indicate the potential of hybrid and 
heterogeneous cooling. These experiments 
were run assuming a large 20 mm × 20 
mm chip with a single 500 µm × 500 µm 
hot spot generating various heat fluxes 
as shown in the x-axis of the figure. The 
background heat across the chip was 50 W/
cm2. These values align with values seen in 
high-performance processors. One can see in 
the figure that hybrid cooling can provide up 
to 15° reduction in the hot spot temperature 
in comparison to using only liquid cooling. A 
hybrid cooling system can also maintain the 
maximum temperature value (such as the 
80° threshold in the figure) for larger heat 
fluxes, while liquid cooling cannot reduce 
temperature beyond a certain level of heat 
flux. This limitation of liquid cooling is because 
of the flow rate restrictions imposed by the 
maximum pressure drop that can be tolerated 
in the microchannels, which typically have 
around tens of microns of width and height 
(e.g., 50umx100um in our experiments).
OPEN PROBLEMS 
The results above demonstrate the 
potential for hybrid and heterogeneous 
cooling. But an open problem is designing 
efficient optimizers that can solve the cooling 
placement and runtime cooling power control 
problem for a given arbitrary chip.
Another obvious open problem is 
investigating how different combinations 
of cooling methods and geometries would 
impact cooling. For example, one could 
envision combining PCM with liquid cooling. In 
such a combination, PCM placed on a chip can 
reduce its peak temperature by a few degrees 
and allow performance boosting during 
melting, while liquid cooling can provide the 
overall chip-wide cooling and perhaps cool 
down the PCM rapidly after melting. Different 
combinations of cooling methods will likely 
be more preferable in different computing 
domains: for example, a small-form-factor 
and cost-constrained mobile system can 
benefit from PCM and/or a limited amount 
of TEC devices, but liquid cooling can work 
better in dense large-scale high-performance 
systems.
There are also new cutting edge cooling 
methods that are being developed by 
thermomechanical engineers. Designing 
nanoscale evaporator devices to perform 
two-phase cooling directly on the chip is an 
example of such methods.Abstracting the 
models of such new devices into compact 
simulators will be an essential step in 
designing future efficienthigh-performance 
computing systems that are integrated with 
their customized cooling.
It is also worth noting that a number of 
new computing, communication, and memory 
devices are being manufactured (e.g., carbon 
nanotubes, memristive devices, silicon 
photonics, and many others). Open problems, 
therefore, include exploring the thermal 
challenges of these devices and designing 
methods to integrate emerging computing 
systems with the best-fitting cooling 
solutions. 
FIGURE 3
An example experiment shows how a hybrid cooling system integrating a TEC placed on the hot spot with 
liquid cooling improves cooling efficiency compared to using liquid cooling only. Hybrid cooling can achieve 
lower temperatures in high heat flux cases and this benefit makes room for achieving higher performance 
per watt.
CIRCUIT CELLAR • JUNE 2017 #32360
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EMBEDDED SYSTEMS ESSENTIALS
Last month, I introduced a type of attacks on embedded systems called power 
analysis attacks. I used these to attack a 
simple PIN code check, where the power 
analysis attack told us what steps the code 
was performing. This was possible because 
different instructions had unique signatures 
we could see in a detailed measurement of 
the power of the device as it was performing 
operations. I won’t replicate the hardware 
setup I discussed in the previous column, 
but again the example figures here will be 
measured on my open-source ChipWhisperer-
Lite platform.
I’ll be returning to the PIN code check I 
have in Listing 1. This code uses an XOR of 
the input PIN code (could be a password or 
anything else) with the correct code. If the 
input and correct code are the same value, 
the result of all the XORs will be zero. If a 
single bit differs, the XOR will output a 1 for 
that bit. The accumulating OR circuit will then 
keep that bit set to “1” for the remainder of 
the comparisons.
BACKGROUND
Let’s begin with a little background. 
Consider a digital device like our 
microcontroller. Internally, it has a data 
bus, which moves data from one section 
(e.g., a register) to another section (e.g., the 
arithmetic logic unit, or ALU).
Is there some way an external observer 
could detect details of that data? It turns out 
there might be, and it might be a lot easier 
than you expect. That data bus contains 
a number of lines, which we can model as 
capacitors. Changing the logic state of those 
lines is the same as changing the voltage on 
those lines, as in Figure 1.
While changing the voltage on a capacitor 
takes energy—a tiny amount of energy—but 
it still physically requires a little bit of power. 
When four data lines change from a 0 to a 
1 state, it actually takes more power than 
when only one of the data lines change state. 
And when it comes to a microcontroller, as 
we make a more complete picture, things 
get even easier for us. Most buses on 
microcontrollers use a precharge state, which 
you can consider a state partway between a 
0 and a 1. 
To transfer data on the bus, the bus goes 
from this intermediate state, to the final state, 
and then back to the intermediate state. What 
this means for us is the amount of power 
consumed may depend not on the difference 
In his previous column, Colin showed how timing attacks could be used to break a password 
check. This article brings out a more advanced type of attack called a power analysis 
attack, which exploits small leaks about internal states of a microcontroller to recover the 
password.
By Colin O’Flynn
Breaking a Password 
with Power Analysis Attacks
int check_pin( uint8_t entered_pin[]){
 uint8_t correct_pin[4] = {1,2,3,4};
 uint8_t pin_fail = 0;
 for (int i = 0; i < 4; i++){
 pin_fail |= correct_pin[i] ^ entered_pin[i];
 }
 
 if(pin_fail){
 return 0;
 } else {
 return 1;
 }
}
LISTING 1
This password check code came from my previous column, as it was written to avoid timing attacks. We’re 
going to use a more advanced type of attack in this column to break the code.
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between number of bits set in the data, but 
in fact just on the number of bits in the data. 
For example, if you transfer 0xFF on the data 
bus, you’ll see a slightly higher spike at that 
instant in time than if you transferred 0x00 
on the data bus. This probably still seems a 
little abstract, so let’s keep working and see 
two different ways this can be used to break 
the XOR code of Listing 1.
DPA ATTACK
The first attack I’ll discuss will be the 
“classic” differential power analysis (DPA) 
attack, which was published by Paul Kocher, 
Joshua Jaffee, and Benjamin Jun in the paper 
entitled “Differential Power Analysis” around 
1999. For this attack to work, assume we 
have a method of sending in a four-digit 
guess for the pin-code of Listing 1, and we 
can trigger such that we can record the 
power consumption around when the XOR is 
happening. We don’t need to guarantee we get 
the exact moment; just that we know roughly 
when the XOR test is happening. Practically, 
this can be pretty easy. You know at some 
point after sending the input data the XOR will 
happen, so you just need to record a section 
of power after sending the input data.
Next, assume we could send a bunch of 
wrong guesses. For each wrong guess, we 
record the guess and the power trace of the 
system processing this guess. Figure 2 shows 
a number of such power traces overlaid on 
each other. Notice that the traces are mostly 
uniform, but certain small areas seem to have 
minor differences.
Next, we’ll do the most important part, 
which is to take the power traces and move 
them into two groups. Our attack will work by 
looking at a single bit of the secret pin at a 
time. Let’s say we want to get the value of byte 
0, bit 0. Taking our set of known inputs and 
associated power traces, we can split them 
into two groups—one where byte 0, bit 0 is 
“0” and one where that same bit is “1.” We’ll 
take the average of these two groups to end up 
with two traces. Finally, taking the difference 
between these “average” traces (a difference of 
means) tells us specifically where the amount 
of power varied for each operation.
What has all this fuss accomplished? First 
off, we’d expect to see a very small spike in 
power consumption at the point that byte 0 is 
manipulated. If bit 0 of byte 0 is “1,” it will 
take a tiny bit more power than when that bit 
is “0.” “But what about the other bits?” you 
might ask, as they are also being flipped. The 
rest of the bits are set to random values, so the 
average of them should be the same between 
the two groups. The only difference between 
those groups was the value of byte 0, bit 0. 
And it’s that bit we are concentrating on.
Then there will be a second spike, as the 
“correct” PIN code is a constant that will 
basically either flip (if the bit of the pin-code 
is “1”) or not flip (if the bit of the PIN code 
is “0”) that spike. This is shown in Figure 3, 
where the bit of the secret key is “1,” so we see 
two opposite polarity spikes. These are from 
real measurements performed on Listing 1 
running on an Atmel XMEGA microcontroller 
FIGURE 1
Changing the voltage on an internal 
data bus is equivalent to charging or 
discharging a capacitor, something 
that takes a tiny amount of energy.
FIGURE 2
An example power trace as the code in Listing 1 is executed an a XMEGA device.
ABOUT THE AUTHOR
Col in O’F lynn (cof lynn@newae.com) has 
been bu i ld ing and break ing e l ec t ron i c 
d e v i c e s f o r m a ny y e a r s . H e i s c u r -
ren t l y comp le t i ng a PhD a t Da lhous i e 
University in Halifax, NS, Canada. His most re-
cent work focuses on embedded security, but 
he still enjoys everything from FPGA devel-
opment to hand-soldering prototype circuits. 
Some of his work is posted on his website at 
www.colinoflynn.com.
mailto:coflynn@newae.com
http://www.colinoflynn.com
CIRCUIT CELLAR • JUNE 2017 #32362
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measured with myChipWhisperer-Lite. These 
tiny differences are clear as day—it might 
seem impossible from the text, but it works 
in real life!
And as in my other article, I encourage 
you to try this yourself. This is something you 
can measure with a regular oscilloscope and 
using a shunt resistor in the voltage line of a 
microcontroller, as discussed in my April 2017 
column.
If you need a hint, the code in Listing 2 
shows a simple Python listing that performs 
this splitting of an array of data into two 
groups, averages them, does the difference, 
and plots this for you. This will give the value 
of a single bit of the secret key.
BREAKING A REAL SYSTEM
Moving from that single-bit break to a 
real system requires little more than taking 
the same power traces, and iterating through 
each bit and byte to recover the complete 
value. You’ll be able to get the entire PIN code 
(or password) out of the system, even though 
there appears to be no timing or similar errors.
As a test, we can do this for the case 
where we know the “secret key.” I’ve done 
this for Byte 0 in Figure 4, where you can 
see all the bits with a certain state have a 
positive power difference, and all the bits 
with the opposite state have a negative power 
difference. The red and blue coloring is only 
possible as I know the secret key, if I hadn’t 
known it we would recover it based on the 
difference direction.
A complete attack is shown in Listing 3. 
Note that I just consider a single point to 
determine if the bit is a “0” or a “1.” This point 
moves for each byte. Because this is an 8-bit 
microcontroller, the byte moves further in time 
every 8 bits that are processed. If I had a 32-bit 
microcontroller then it could have processed 4 
bytes at once, for example. But looking at the 
difference traces (such as in Figure 3) helps 
you determine where exactly to look for a large 
difference, even if you don’t know much about 
the device you are attacking or how the code 
works. The only tricky part is getting a nice 
trigger. In many systems, this can be done 
by triggering on the communication line. For 
example, if you have a UART protocol to send 
the password, you can trigger when you see 
the last byte go over the UART.
You can even get fancy by triggering on 
patterns in the analog waveform. Certain 
oscilloscopes provide this capability, and it’s 
possible with custom hardware such as I 
built for the ChipWhisperer-Pro (a higher-end 
version of the same capture hardware). But 
in most practical cases it’s enough to trigger 
on communication lines that are already 
present. The open-source ChipWhisperer 
from chipwhisperer.common.api.CWCoreAPI import 
CWCoreAPI
from matplotlib.pylab import *
cwapi = CWCoreAPI()
cwapi.openProject(‘xortest_1000.cwp’)
tm = cwapi.project().traceManager()
number_traces = tm.numTraces()
zerolist = []
onelist = []
for tnum in range(0, number_traces):
 entered_pin = tm.getTextin(tnum)
 trace_data = tm.getTrace(tnum)
 #Get value of bit 1 in data we sent
 bit_value = entered_pin[0] & 0x02
 
 #Seperate into group based on bit value
 if bit_value:
 onelist.append(trace_data)
 else:
 zerolist.append(trace_data)
 
#Take mean of both groups of traces
one_mean = np.mean(onelist, axis=0)
zero_mean = np.mean(zerolist, axis=0) 
#Get difference
diff = one_mean - zero_mean
plot(diff)
LISTING 2
This Python code performs a single-bit DPA attack, by attempting to determine the value of bit 0 of the key. 
The resulting plot is given in Figure 3.
FIGURE 3
This shows the power difference when attacking a single bit of a password byte. I’ve averaged two groups 
of traces and subtracted them to see the difference between the groups. See Listing 2 for the code that 
generated this plot.
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software I’m using here also has capabilities 
to resynchronize traces with some “jitter” in 
them by looking for patterns that appear in 
both traces and lining them up.
Hopefully, this article has opened your 
eyes to how it’s possible to attack real 
systems using side-channel power analysis. 
This is just the tip of the iceberg for advanced 
hardware attacks that are possible, and I’ll be 
sharing more of these with you in the coming 
columns.
If you want more detailed examples, I’ll 
link them from a blog post for this article on 
oflynn.com, but they are all part of the open-
source ChipWhisperer project. I’m creating 
some unique examples for my columns here, 
but the overall goals will be the same. 
from chipwhisperer.common.api.CWCoreAPI import CWCoreAPI
from matplotlib.pylab import *
cwapi = CWCoreAPI()
cwapi.openProject(‘xortest_1000.cwp’)
tm = cwapi.project().traceManager()
number_traces = tm.numTraces()
for byte in range(0, 4):
 recovered_byte = 0
 for bit in range(0, 8):
 zerolist = []
 onelist = []
 for tnum in range(0, number_traces):
 entered_pin = tm.getTextin(tnum)
 trace_data = tm.getTrace(tnum)
 
 #Get value of bit in input guess for this trace 
 bit_value = entered_pin[byte] & (1<<bit)
 
 #Seperate into group based on bit value
 if bit_value:
 onelist.append(trace_data)
 else:
 zerolist.append(trace_data)
 #Take mean of all traces where one, all traces where zero
 one_mean = np.mean(onelist, axis=0)
 zero_mean = np.mean(zerolist, axis=0) 
 #Get difference
 diff = one_mean - zero_mean
 
 #Based on our graphical plotting, we identified point 129 in byte 0
 #and that point occurs 92 samples later in each successive byte
 print “byte %d, bit %d = “%(byte, bit),
 if diff[129 + 92*byte] < 0:
 print “0” 
 else:
 print “1”
 recovered_byte |= (1<<bit)
 print “Guess for byte %d: 0x%02x”%(byte, recovered_byte)
LISTING 3
This is Python code for breaking complete system iterates through the test done in Listing 2. (See text for details.)
FIGURE 4
This shows differences for all 8 bits of a guessed password byte, where red power traces are bits where the 
value of the key-bit ‘0’, and blue power traces are values of the key are ‘1’. You can see all the bits of each 
value go in opposite directions.
CIRCUIT CELLAR • JUNE 2017 #32364
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THE DARKER SIDE
PHOTO 1
An online emulator for my old Apple II
For the last 30 years, C has been my programming language of choice. As you 
probably know, C was invented in the early 
1970s by Dennis M. Ritchie for the first UNIX 
kernel and ran on a DEC PDP-11 computer. I am 
probably a bit old-fashioned. Yes, C is outdated, 
but I’m simply addicted to it, like plenty of 
other embedded system programmers. For 
me, C is a low level but portable language 
that’s adequate for all my professional and 
personal projects ranging from optimized code 
on microcontrollers to signal processing or 
even PC software. I know that there are many 
powerful alternatives like Java and C++, but, 
well, I’m used to C.
C is not the only vintage programming 
language, and playing with some others is 
definitively fun. This month, I’ll present several 
vintage languages and show you that each 
language has its pros and cons. Maybe you’ll 
find one of them helpful for a future project? I’m 
sure you won’t use COBOL in your next device, 
but what about FORTH or LISP? As you’ll see, 
thanks to web-based compilers and simulators, 
playing with programming languages is simple. 
And after you’re finished with this review of 
1970s-era computing technology, give one or 
two a try!
BASIC
Like many teenagers in the 1970s, I learned 
to program with Beginner’s All-purpose 
Symbolic Instruction Code (BASIC). In 1980, 
after some early tests with programming 
calculators, a friend let me try a Rockwell AIM-
65 computer. An expanded version of the KIM-
Vintage Programming 
Languages
According to Robert,“vintage programming languages 
are not dead.” In fact, he argues that you might even find 
some of them more helpful than C or Java for your future 
projects. In this article, he presents a few of the hundreds 
of different programming options at your disposal. 
By Robert Lacoste
circuitcellar.com 65
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1, it had an impressive 1 KB of RAM and a BASIC 
interpreter in ROM. It was my first contact 
with a high-level programming language. I 
was really astonished. This computer seemed 
to understand me! “Print 1+1.” “Ok, that’s 2.” 
One year later, I bought my first computer, an 
Apple II. It came with a much more powerful 
BASIC interpreter in ROM, AppleSoft Basic. 
(This interpreter was developed for Apple by 
a small company named Microsoft, but that’s 
another story.) 
Now let’s launch an Apple II emulator 
and write some software for it. Look at 
Photo 1. Nice, isn’t it? This pretty emulator, 
developed in JavaScript by Will Scullin, is 
available online. Just launch it, enter this 10-
line program, and then type “RUN”. It will 
calculate for you the factorial of eight: 8! = 1 
× 2 × 3 × 4 × 5 × 6 × 7 × 8, which is 40,320.
Since its invention in 1964 at Dartmouth 
College, BASIC is more of a concept than a well-
specified language. Plenty of variants exist up 
to Microsoft’s Visual Basic. But it has plenty of 
disadvantages, especially its early versions: a 
lack of structured data and controls, mandatory 
line numbering, a lack of type checking, 
low speed, and so on. Nevertheless, it is 
ultra-simple to learn and to understand. 
Even if you have never used BASIC, you’ll 
understand the code shown in Photo 1 without 
any problem. The main program starts by 
initializing a variable N with the value 8. I then 
calls a subprogram that starts at line 100, 
displays the result F, and stops. The subprogram 
initializes F to 1 and multiplies the result by 
each integer up to N. Straightforward.
C LANGUAGE
Let compare this BASIC with a C version of 
the same algorithm. For this article, I looked 
for online compilers and simulators. I found 
a great option at www.ideone.com, which, 
developed by Sphere Research Labs, supports 
more than 60 programming languages. You 
can edit a program using any of them, compile 
it, and test it without having to install anything 
on your PC. This is great for experimenting.
The C variant of the factorial algorithm is 
depicted in Photo 2. I could have used plenty 
of different approaches, but I tried to stay 
as close as possible to the “spirit” of C. So, 
how does it compare with BASIC? The code 
is significantly more structured, but a little 
harder to read. C aficionados loves short forms 
like f*=i++ (which multiplies f by i and then 
increments i) even when they can be avoided. 
While this makes the code shorter and helps 
the compiler with optimization, it is probably 
cryptic to someone new to the language. 
Of course, C also has great strengths. In 
particular, it offers you precise control of the 
data types and memory representation, which 
LISTING 1 
This is the factorial program using FORTRAN 77.
 PROGRAM MAIN
 PRINT *,FACT(8)
 STOP
 END
 FUNCTION FACT(N)
 INTEGER I,N
 FACT=1
 DO 10 I = 2,N,1
 FACT=FACT*I
10 CONTINUE
 END
PHOTO 2
At Ideone.com, you can enter, 
compile, and simulate numerous 
programming languages. Here you 
see C language.
LISTING 2
The COBOL version looks a little stranger, right?
IDENTIFICATION DIVISION.
PROGRAM-ID. TESTFACT.
DATA DIVISION.
WORKING-STORAGE SECTION.
77 N PIC 99999 .
77 F PIC 99999 .
77 I PIC 99999 .
PROCEDURE DIVISION.
 MOVE 8 TO N.
 PERFORM FACT.
 DISPLAY F.
 STOP RUN.
 FACT.
 MOVE 1 TO F.
 PERFORM MULT VARYING I FROM 1 BY 1 UNTIL I>N.
 MULT.
 MULTIPLY F BY I GIVING F.
http://www.ideone.com
CIRCUIT CELLAR • JUNE 2017 #32366
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helps for low level programming. That’s probably 
why it has been so widely for nearly 50 years.
FORTRAN & COBOL
Let’s stay in the 1970s. BASIC or assembly 
language was for hobbyists and experimenters. 
C was used by early UNIX programmers. The 
rest of the programming world was divided 
into two camps. Scientifics used FORTRAN. 
Business leaders used COBOL.
FORTRAN (from FORmula TRANslation) 
was actually the first high-level programming 
language. Developed by an IBM team led by 
John Backus, the first version of FORTRAN was 
released in 1957 for the IBM 704 computer. 
It was followed by several incremental 
improvements: Fortran 66 (1966), Fortran 77, 
and Fortran 90, all the way up to Fortran 2008. 
Refer to Listing 1 for the factorial program 
using FORTRAN 77. It seems close to BASIC, 
right? That’s not a surprise as BASIC was in 
fact based on concepts from FORTRAN and 
from another disapeared language, ALGOL. I’m 
sure that you are able to read and understand 
the FORTRAN in Listing 1, but its equivalent 
in COBOL is a bit stranger (see Listing 2). I 
must admit that it took me some time to make 
it working, even after reading some COBOL 
tutorials on the web. COBOL is an acronym 
for Common Business-Oriented Language, so 
it is not exactly targeting an application like a 
factorial calculation. It was developed in 1959 by 
a consortium named CODASYL, based on works 
from Grace Hopper. Even though its popularity 
fading, COBOL is still alive. I even read that an 
object-oriented version was released in 2002 
(COBOL 2002) and even upgraded in 2014.
PASCAL AND ITS FRIENDS
I never actually used FORTRAN or COBOL, 
but I developed software on my Apple II using 
PASCAL. Released in 1970 by Niklaus Wirth (ETH 
Zurich, Swizerland), PASCAL was probably one 
of the earliest efforts to encourage structured 
and typed programming. Based on ALGOL-W 
(also invented by Wirth), it was followed by 
MODULA-2 and OBERON, which were less 
known but still influential.
Do you want to calculate a factorial in 
PASCAL? Here it is Listing 3. It may look 
familiar to FORTRAN or BASIC, but its 
advantages are in the details. PASCAL is a 
so-called strongly typed language. (You can’t 
add a tomato and a donut, contrarily to C.) It 
also forbids unstructured programming and 
it is very easy to read. PASCAL was a limited, 
but true, success. It was used in particular by 
Apple for the development of the Lisa computer 
as well as the first versions of the Macintosh. It 
is still in use today through one of its object-
oriented versions, DELPHI.
THE ADA STORY
In the 1970s, the United States Department 
of Defense (DoD) conducted a survey and found 
that they were using no less than 450 different 
programming languages. So, it decided to 
define and develop yet another one—that is, a 
new language to replace all of them. After long 
LISTING 3
This is the PASCAL version. Easy to read.
program test;
 function fact(n:integer):integer;
 begin
 var i,f: integer;
 f:=1;
 for i:=2 to n do
 f:=f*i;
 fact:=f;
 end;
begin
 writeln(fact(8));
end.
LISTING 4
ADA is more verbose.
with Ada.Integer_Text_IO;
procedure TestFact is
begin
 declare
 function Fact (N: Integer) return Integer is
 i,f:Integer;
 begin
 f:=1;
 for i in Integer range 1 .. N loop
 f:=f*i;
 end loop;
 return(f);
 end Fact;
 begin
 Ada.Integer_Text_IO.Put (Item => Fact(8), Width => 1);
 end;
end TestFact;
LISTING 5
LISP is definitively fun!
(defun fact (n)
 (if (= n 0)
 1
 (* n (fact (- n 1))) ) )
 
(print (fact 8))
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specification and selection phases, a proposal 
from Jean Ichbiah (CII Honeywell Bull, France) 
was selected. The result was ADA. The name 
ADA, and its military standard reference (MIL-
STD-1815), are in memory of Augusta Ada, 
Countess of Lovelace (1815–1852), who created 
of the first actual algorithms intended for a 
machine.
While ADA is, well, strongly typed and 
very powerful, it’s complex and quite boring 
to use (see Listing 4). The key advantage 
of ADA is that it is well standardized and 
supports constructs like concurrency. Thanks 
to its very formal syntax and type checking,it is nearly bug-proof. Based on my minimal 
experience, it is so strict that the first version 
of the code usually works, at least after you 
correct hundreds of compilation errors. That’s 
probably why it is still largely used for critical 
applications ranging from airplanes to military 
systems, even if it failed as a generic language.
LISP AND FORTH
ADA is a difficult language. In my opinion, 
LISP (List Processing) is far more interesting. 
It is an old story too. Designed in 1960 by John 
McCarthy (Stanford University), its concepts are 
still interesting to learn. McCarthy’s goal was to 
develop a simple language with full capabilities. 
That’s quite the opposite of ADA. The result 
was LISP. The syntax can be frightening, but 
you must try it. Listing 5 is a version of the 
factorial calculation in LISP.
In LISP, everything is a list, and a list is 
enclosed between parentheses. To execute a 
function, you have to create a list with a pointer 
to the function as a first element and then the 
parameters. For example, (- n 1) is a list that 
calculates n – 1. (if A B C) is a structure 
which evaluates A, and then evaluates either 
B or C based on the value of A. If you read 
this program, you will see that it is not based 
on a loop like all other versions I’ve presented, 
but on a concept called recursion. A factorial 
of a number is calculated as 1 if the number 
is 0, and as N times the factorial of (N – 1) 
otherwise. LISP was in fact the first language 
to support recursion—meaning, the possibility 
for a function to call itself again and again. It 
is also the first language to manage storage 
automatically, using garbage collection. Even 
more interesting, in LISP everything is a list, 
even a program. So in LISP, it is possible to 
develop a program that generates a program 
and executes it!
Another of my favorites is FORTH. Designed 
by Charles Moore in 1968, FORTH also supports 
self-modifying programs like LISP, and it is 
probably even more minimalist. FORTH is based 
on the concept of a stack, and operators push 
and pop data from this stack. It uses a postfix 
syntax, also named Reversed Polish Notation, 
like vintage Hewlett-Packard calculators. For 
example, 1 2 + . means “push 1 on the 
stack,” “push 2 on the stack,” “get two figures 
from the stack, add them and put the result 
back on the stack,” and “get a figure from the 
stack and display it.”
Here is our factorial program in FORTH:
: fact dup 1 do I * loop ; 
8 fact .
The first line defines a new function named 
fact, and the second line executes it after 
pushing the value 8 on the stack. The syntax is 
of course a bit strange due to the postfixing but 
it is clear after a while. Let’s start with 8 on the 
stack. The command dup duplicates the top of 
the stack. The do…loop structure gets count 
and first index from the stack so it executes I 
* with I varying from 1 to 7, and each iteration 
PHOTO 3 
This is an example of FORTH in the Repl.it online compiler and simulator.
LISTING 6
The PROLOG version based on a completely different paradigm.
fact(X, 1) :- X<2.
fact(X, F) :- XM1 is X-1, fact(XM1,FM1), F is FM1*X.
?- fact(8,X), print(X).
ABOUT THE AUTHOR
Robert Lacoste lives in France, between Paris and 
Versailles. He has 30 years of experience in RF 
systems, analog designs, and high speed elec-
tronics. Robert has won prizes in more than 15 
international design contests. In 2003 he started 
a consulting company, ALCIOM, to share his pas-
sion for innovative mixed-signal designs. Rob-
ert’s bimonthly Darker Side column has been 
published in Circuit cellar since 2007. You can 
reach him at rlacoste@alciom.com.
mailto:rlacoste@alciom.com
CIRCUIT CELLAR • JUNE 2017 #32368
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multiplies the top of the stack by the index I. 
That’s it. You can try it using another web-based 
programming and simulation host: https://repl.
it. Look at the result in Photo 3.
FUN WITH PROLOG & APL
LISP and FORTH are fun, but PROLOG is 
stranger. Developed by Alain Colmerauer and 
his team in 1972, PROLOG is the first of the 
so-called declarative languages. Rather than 
specifying an algorithm, such a declarative 
language defines facts and rules. It then lets 
the system determine if another fact can be 
deduced from them. An example is welcome. 
Listing 6 is our factorial in PROLOG. The 
first fact states that the factorial of any number 
lower than 2 is 1. The second fact states that 
the factorial of any number X is F only if F is the 
product of X and another number, named here 
FM1, and if FM1 is the factorial of X – 1. This 
looks like a recursion, and this is recursion, but 
expressed differently. Then the last line states 
that X is the factorial of 8 and ask PROLOG to 
display X, and you will have the result. This is a 
confusing approach, but it is close to the needs 
of artificial intelligence algorithms.
Lastly, I can’t resist to the pleasure to 
show you another exotic vintage programming 
language, A Programming Language (APL). 
Refer to the factorial example in APL in Photo 4. 
I can’t even write it in the text of this article 
because APL uses nonstandard characters. In 
fact, APL-enabled computers had APL-specific 
keyboards! Published in 1962 by Kenneth 
Iverson (Harvard University and then IBM), it 
was firstly a mathematical notation and then 
a programming language. Based largely on 
data arrays, APL targets numerical calculations 
so it isn’t a surprise to see that our factorial 
example is so compact in this language. Let’s 
understand it by reading the first line from 
right to left. The omega Greek symbol is the 
parameter of the function (that is, 8 in this 
case). The small symbol just before the omega 
called “iota” is generating a vector from 0 to 
N – 1, so here it is generating 0 1 2 3 4 5 6 7. 
The 1+ is adding one to each element of the 
array. This gives 1 2 3 4 5 6 7 8. Lastly, the x/ 
asks to multiply each value of the vector, which 
is the factorial!
GET STARTED
After finishing this article, I searched the 
web for other interesting languages and found, 
well, a more than impressive website. Launch 
your browser right now and enter http://
rosettacode.org. These crazy guys simply listed 
837 programming tasks, and let the community 
program each of them with all programming 
languages. Yes, all of them, and no less than 
648 different languages are referenced! Of 
course, I searched for a factorial calculation 
algorithm and found it. Versions of the factorial 
code for 220 different languages are provided! 
So, you can find similar versions to the ones 
I provided in this article as versions for more 
recent languages (Java, Python, Perl, etc.). You 
will also find obscure languages.
My goal with this article was to show you 
that languages other than C and JAVA can 
be fun and even helpful for specific projects. 
Vintage languages are not dead. For example, it 
seems that FORTH was used for NASA’s Rosetta 
mission. Moreover, innovation in computing 
languages goes on, and new and exciting 
alternatives are proposed every month!
Don’t hesitate to play with and test 
programming languages. The web is an 
invaluable tool for discovering new tools, so 
have fun! 
circuitcellar.com/ccmaterials
REFERENCES 
CodingUnit, “The Histo-
ry of the C Language,” 
www.codingunit.com/
the-history-of-the-c-language.
 
D. Harper and L. M. Stock-
man, “The History of FOR-
TRAN,” Obliquity, www.obliq-
uity.com/computer/fortran/
history.html.
Rosetta Code, https://rosettacode.org/wiki/
Factorial.
SOURCES
Repl.it cloud coding environment
Neoreason | https://repl.it/languages
 
ngn/apl APL interpreter in JavaScript
N. G. Nikolov | https://ngn.github.io/apl/web
Apple ][ emulator in Javascript 
W. Scullin | www.scullinsteel.com
Ideone online compiler
Sphere Research Labs | www.ideone.com
PHOTO 4
APL looks great, right? It’s unique 
keyboard alone is fun!
https://repl.it/languages
https://ngn.github.io/apl/web
http://www.scullinsteel.com
http://www.ideone.com
https://repl. it
http://rosettacode.orgwww.circuitcellar.com/ccmaterials
www.codingunit.com/
the-history-of-the-c-language
www.obliq-uity.com/computer/fortran/history.html
https://rosettacode.org/wiki/Factorial
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CIRCUIT CELLAR • JUNE 2017 #32370
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As a young man, Marconi created a storm monitor—a rudimentary receiver—used 
to detect lightning. He extended this by 
recreating his own storm on demand, sending 
broad spectrum electromagnetic (EM) waves 
propagating from a spark gap, a simple 
transmitter. While these transmissions were 
extremely wide band, they bootstrapped the 
development of radio telegraphy (Morse code) 
and telephony (voice) within the next decade. 
Now, 100 years later, you can talk to virtually 
anyone in the world with a portable wireless 
device that fits in your pocket. 
I still listen to commercial radio while 
driving in my Jeep, which has an AM/FM radio. 
The familiar digits of a station’s frequency 
reassure me that I’ll be hearing a good mix 
of new and old tunes. This number is a radio 
station’s carrier frequency. It’s just a small 
slice of the FCC’s allocated spectrum for the 
FM broadcast band from 88.0 to 108.0 MHz. 
Station carriers are allocated every 200 kHz 
inside this band. Initially, audio was used to 
directly modulate the carrier for a monaural 
transmission requiring much less that the 
allocated bandwidth of 200 kHz. Today’s radio 
stations have found ways to use this added 
bandwidth, but that’s a different story. This one 
relates to the fact that these radio frequencies 
can pass right through our homes.
Practical radio transmission systems are 
mostly line-of-sight propagation or radio 
waves that travel in a straight line from 
the transmitting antenna to the receiving 
antenna. This process applies to garage 
door openers, cell phones, cordless phones, 
walkie-talkies, wireless networks, commercial 
radio and television broadcasting, and radar. 
Line-of-sight transmission on the Earth’s 
surface is limited to the distance to the visual 
horizon, a maximum of about 40 miles. It 
does not necessarily require a cleared sight 
path; at lower frequencies, radio waves can 
pass through building walls and foliage. 
Many of the wireless communication 
mediums used today are part of IEEE 802. 
This is a family of standards from the Institute 
of Electrical and Electronics Engineers that 
deals with local area and metropolitan area 
networks. These include working groups 
that focus on wired and wireless connection 
types. You may be most familiar with some 
of the 802 wireless groups like 802.11 (Wi-Fi), 
802.15.1 (Bluetooth), 802.15.4 (ZigBee, MiWi), 
802.15.6 (Body Area Network), and 802.15.7 
(Visible Light Communications). As carrier 
frequencies rise above 1 GHz, you’ll find these 
technologies begin to have penetration issues, 
as you can see in Figure 1.[1] It’s not a big deal 
when you are dealing with short transmission 
distances. 
The FCC has a tough job. The usable 
spectrum is limited. It is their job to allocate 
the available space. Everyone wants a piece 
of the action. To ensure everyone plays well 
together, the FCC sometimes must impose 
additional restrictions on top of who can 
use which parts of the spectrum. These 
might include maximum power radiated or 
transmission time limits. Many bands are 
licensed. Some are open, but you must still 
play by the rules. One of the open bands is 
the ISM (Industrial, Scientific, and Medical) 
band, 915 MHz (902 to 928 MHz). In the United 
States, this ISM band is also shared with error-
tolerant communications applications such as 
wireless sensor networks. My wireless house 
phone operates in this region.
If you find that your next design project’s requirements 
exceed the specifications of the wireless technology you 
are presently using, you might want to consider LoRa. In 
this series, Jeff introduces LoRa technology and discusses 
some of its advantages over older competitors. 
By Jeff Bachiochi
FROM THE BENCH
Long-Range, Low-Power Wireless 
Communications (Part 1)
Trading Throughput for Distance
circuitcellar.com 71
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We are beginning to see some technologies 
pick up on this. One new player is LoRa (Long 
Range). In this article, I’ll introduce the 
technology and then present an interesting 
project—a peer-to-peer network using the 
LoRa technology. I’ll cover the circuitry and 
explain how the hardware works.
LoRa SPECTRUM
Unlike many other technologies, the slots 
that make up the LoRa spectrum are divided 
into a number of different bandwidths. 
The 915-MHz (US) LoRa band, shown in 
Figure 2, has 64, 125 kHz, and 8, 500 kHz 
uplink channels and 8, 500 kHz down link 
channels. Note uplink channels share the 
same space. A transmission may select either 
bandwidth allocation to use and trade off 
SNR for throughput. A transmission always 
begins with channel 0. This allows a receiver 
to catch the transmission before hopping 
channels in a predetermined sequence. 
LoRa uses chirp spread spectrum (CSS) 
and is a technique that uses wideband 
linear frequency modulated “chirp” pulses 
to encode information. A chirp is a rising 
(or falling) sinusoidal signal frequency that 
varies over time. The chirp’s frequency varies 
proportional to the bandwidth of the allocated 
slot. One or more chirps can reside within a 
single time slot (frequency hop).
The data throughput is fixed by a number 
of factors in the LoRa specification, the 
bandwidth (BW), the spreading factor (SF), 
and the coding rate (CR). In our case (915-
MHz band), the uplink BW is fixed at either 
125 or 500 kHz. The SF is the number of chips 
or divisions that make up a symbol. A symbol 
is sent for each 1 bit of data and is a power 
of 2—in this case, between 6 and 12. The 
CR is an amount of forward error correction 
information added to each symbol, here 
between 1 and 4 or 0.25 to 1 extra bit.
The actual data bit count we began with 
has suddenly been expanded by the SF and 
CR into a much larger number of transmission 
data chips. The transmission data modulates 
the chirping carrier at a rate of 1 chip per 
second per 1 Hz (here, that’s 125 kbps). At a 
maximum SF and CR, that’s about 293 actual 
data bits per second (approximately 36 bytes). 
All this redundancy, allows for the best-case 
SNR, which should mean a receiver can more 
easily find and decode the transmission, 
resulting in an increase in range.
DATA PACKET
Before we look at the radio’s register 
set and initialize it, we should look at the 
elements of the packet sent by the LoRa 
radio. (The register set for the Semtech radio 
chip is available on the Circuit Cellar FTP 
site. The register set is multipurpose—that 
is, it’s register usage depends on the type 
of modulation—OOK/FSK/LoRa—identified in 
the Operational Mode Register.) There are a 
few decisions that should be made in order 
to set the configuration correctly. The LoRa 
packet is made up of a preamble, optional 
header, and payload. The preamble contains 
special symbols that allow the receiver to 
recognize it as a packet start. The length of 
preamble is programmable but must contain 
at least the syncword and sync downchirp. 
In our case, we’ll use the default of eight, 
plus program the LoRa syncword 0x12 into 
register 0x39 (RegSyncWord). Note: It looks 
like all modulationis up chirps except the final 
sync in the preamble.
The ImplictHeaderMode bit found 
within the RegSymbTimeoutMsb register 
can be set to Explicit Mode. This adds an 
optional header when the transmitter 
Sub-1 GHz
ZigBee
6LowPAN
Wi-Fi
2.4-GHz
Proprietary
Range
BLETechnology
Bluetooth
10 m 100 m 10 km
FIGURE 1 
Frequency penetration
64 + 8 Uplink Channels
902.3 903.0 904.6 914.2 923.3
8 × Downlink Channels
923.9 927.5
US902-928 Channel frequencies FIGURE 2
LoRa 915-MHz band
CIRCUIT CELLAR • JUNE 2017 #32372
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wants to tell the receiver; how many bytes 
to expect, what Coding Rate (CR) is being 
used for Forward Error Correction (FEC), 
and an optional 16-bit Cyclic Redundancy 
Check (CRC) for the payload. This can be 
eliminated if both transmitter and receiver 
have matching values manually configured 
on each side. This effectively shortens the 
packet size but offers less flexibility of the 
packet. For this project, we’ll be using the 
Explicit Mode. This requires configuration 
of registers 0x1D (RegModemConfig1), 
0x1E (RegModemConfig2), and 0x26 
(RegModemConfig3). Also, the SF, CR, 
and other information must be written so 
the transmitter can assemble the header 
information correctly. 
The payload length is a maximum of 255 
bytes; however, there is a maximum packet 
time of 400 ms, as defined by the FCC for the 
US 902–928 band (915 MHz). This will limit 
the available payload length to a lower value, 
especially when using higher SF. Payload data 
will be written into a FIFO through register 
0x00 (RegFifo) to send it. On the receiver, 
the payload data will be read through this 
register. The payload is handled by an internal 
64-byte FIFO. Data pointers are automatically 
adjusted as the data is written in by the user 
and transmitted out by the radio and received 
by the radio and read out by the user.
You’ll note (see Table 1) that the radio 
offers six I/Os that can be configured to 
indicate the status of various functions like 
PayloadReady (in RX mode) or PacketSent 
(in TX mode). These can be mapped to pins 
DIO0:5 using two registers, RegDioMapping1 
0x40 (D0:3) and RegDioMapping2 0x41 (D5:4). 
LoRa VS LoRaWAN
Semtech Corp. is responsible for the 
proprietary LoRa radio specification. They are 
also a founding member of the LoRa Alliance 
(www.lora-alliance.org), whose mission is to 
standardize Low Power Wide Area Networks 
(LPWAN) and enable the LoRa protocol 
(LoRaWAN). Semitech’s product line includes 
wireless RF transceivers. A slice of that pie is 
devoted to LoRa radios. The LoRa radio is the 
mechanism for sending data using the LoRa 
technology. This should not to be confused 
with LoRaWAN, which is a standard for 
building a LPWAN upon the LoRa technology. 
The LoRa radio specification is the 
mechanism used to transmit a payload over the 
air. Other than the initial structure or wrapper 
used around the payload, it does not define the 
payload in any way. LoRaWAN is a Media Access 
PA_BOOST
PA_HF
High band
Fractional-N PLL
PA_HP
PA_LF
TXDAC
Low band
Fractional-N PLL
RFO_HF
RFI_LF
RFO_LF
VR_PA
RFI_HF
LI
PA Regulator
ADCI
ADCO
MUX
LoRa
Modulator
NSS
FSK/OOK
Modulator
FSK/OOK
Demodulator
LoRa
Demodulator
LoRa/FSK
FIFO
SPI
Interface
Crystal
oscillator
XTA XTB
RC
oscillator Power distribution
Config
registers
VBAT_ANA VBAT_DIG VBAT_RF VR_ANA VR_DIG GND
RXTX/RFMOD
NRESET
DIO(5:0)
SCK
MOSI
MISO
FIGURE 3 
A diagram of the radio chip 
Operating 
Mode
DIOx 
Mapping
DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
ALL 00 ModeReady CadDetected CadDone FhssChangeChannel RxTimeout RxDone
01 ClkOut PllLock ValidHeader FhssChangeChannel FhssChangeChannel TxDone
10 ClkOut PllLock PayloadCrcError FhssChangeChannel CadDetected CadDone
11 - - - - - -
TABLE 1
The radio’s general-purpose I/Os can 
be configured to “map” particular 
status to the physical outputs. The 
2-bit DIOx mapping value is written 
to the appropriate mapping registers 
(0x40 for DIO0:3 and 0x41 for 
DIO4:5).
http://www.lora-alliance.org
circuitcellar.com 73
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Control (MAC) protocol for wide area networks. 
It allows low-powered devices to communicate 
with Internet-connected applications over LoRa 
wireless connections. It is one of the protocols 
implemented on top of LoRa technology. It 
allows a cloud-based application to collect 
and direct communications between itself and 
distant end points.
LoRaWAN uses the LoRa wireless 
technology in the end point to gateway 
portion of the WAN. Gateways connect LoRa 
wireless nets to cloud control via internet 
connections. LoRaWAN is beyond the scope 
of this project. This project will investigate 
the use of LoRa technology for peer-to-peer 
wireless networking where an increase in 
transmission distance is required. I will focus 
my attention on the LoRa technology, which 
can be used on its own for smaller scale peer-
to-peer networking. The hardware I chose to 
begin with is the Adafruit Feather 32u4 Radio 
with RFM95W Module, which is a $25 small 
form factor Arduino with LoRa-compatible 
radio. The RFM95W is a radio module made 
by HopeRF Electronic. The Feather is available 
with either a 433-MHz (Europe) or 868/915-
MHz (US) radio. You can find support libraries 
for the LoRa radio, but I’ll be using the SPI 
directly to read and write radio registers.
The RFM95W radio module uses Semtech’s 
SX127x family LoRa transceiver. The SPI 
requires a few I/O: CS output (SPI Chip 
Select), Reset output, and Interrupt input for 
the radio status. Let’s start with a look inside 
the transceiver. Figure 3 shows the function 
blocks of the radio module. You’ll notice that 
this radio is very flexible, because it can 
perform the normal FSK and OOK modulations 
as well as LoRa within its selected frequency 
band. Refer to Table 2 for the register set for 
the radio. You’ll note some register functions 
change depending on the mode set in the 
radio’s Operation Mode Register (0x01 in the 
table), which defaults to FSK at power-up. 
While the Feather32U4 has pad provisions 
for a uFL (antenna) connector, I chose to use a 
Operating 
Mode
DIOx 
Mapping
DIO5 DIO4 DIO3 DIO2 DIO1 DIO0
ALL 00 ModeReady CadDetected CadDone FhssChangeChannel RxTimeout RxDone
01 ClkOut PllLock ValidHeader FhssChangeChannel FhssChangeChannel TxDone
10 ClkOut PllLock PayloadCrcError FhssChangeChannel CadDetected CadDone
11 - - - - - -
RegOpMode (0x01) Bits Variable Name Mode Default value FSK/OOK Description
7 LongRangeMode r B’0’ 0 - FSK/OOK Mode
1- LoRaTM Mode
This bit can be modified only in 
Sleep mode.
A write operation on other device 
modes is ignored
5-Jun ModulationType rw B’00’ Modulation scheme:
00 - FSK
01 - OOK
10:11 - reserved
4 reserved r B’0’ reserved
3 LowFrequencyModeOn rw B’1’ Access Low Frequency Mode 
registers (from address 0x61 on)
0 - High Frequency Mode (access 
to HF test registers)
1 - Low Frequency Mode (access 
to LF test registers)
2:00 Mode rw B’001’ Transceiver modes
000 - Sleep mode
001 - Stdby mode
010 - FS mode TX (FSTx)
011 - Transmitter mode (Tx)
100 - FS mode RX (FSRx)
101 - Receiver mode (Rx)
110 - reserved
111 - reserved
TABLE 2
The Operational Mode register sets the basic function of the radio to either FSK/OOK or LoRa mode.
CIRCUIT CELLAR • JUNE 2017 #32374
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3” piece of wire as a quarter wave whip antenna 
for my initial experiments. No additional 
connections other than the USB, which is used 
for powering the board and serial debugging, 
are required to get started. 
ARDUINO SKETCH
Most Arduino sketches contain at least 
two functions, setup() and loop(). Prior 
to the setup() function, you must declare/
define those external libraries, constants, and 
variables of which you will call upon. I’ll be 
using the standard SPI and Wire libraries for 
communicating with peripherals, but not any 
libraries that mask how those peripherals 
might be used. All the registers are defined 
with names that suggest their use, to make 
the code morereadable.
Since the radio module has outputs that 
can be used as interrupts, we need to make 
sure that those variables are declared with 
the “volatile” qualifier. One variable I use in 
every sketch is int debug. This gives me 
16 bits I can use to enable/disable print 
statements that I use to show the present 
values of variables. By qualifying a print 
statement with if((debug & <bit value> 
== <bit value>), a print statement can 
be enabled or disabled from the serial output 
stream by setting or clearing the appropriate 
bits in the debug variable. So far, there has not 
been a good debugger for the Arduino IDE. If 
the code crashes, there are no clues to what’s 
going on. It behooves the user to add some kind 
breadcrumb trail to help follow the execution.
The setup() function is the place to start 
any libraries or initialize any peripherals. I’m 
using the USB for serial debugging and SPI 
to communicate with the radio module. The 
feather32u4 has a few permanent connections 
to the radio module, and since all I/O defaults 
to inputs, we must configure the SPI’s chip 
select (CS) as an output in an initialized HIGH 
state. Since this project require at least two 
radios for communications, I’ll be using the 
same sketch to operate either in a client or 
server mode and simplify the project. This 
choice could be set with a physical jumper. 
In this case, I’ll just set a Boolean variable at 
compile time to determine the function. This is 
part of the sign-on message and will display 
which function has been assigned to a board.
Many Arduino sketches never make use 
of an interrupt. The radio module can map 
six DIO pins to an internal status state, which 
might be used as interrupt sources. However, 
most Arduino boards have a limited number 
of inputs that can be defined as external 
interrupts. We’ll use one of these outputs to 
signal when a selected function has completed. 
To use an external interrupt in an Arduino 
sketch, we must define its connection in 
setup() using the attachinterrupt() 
TABLE 3
The individual interrupt status is 
available through the IRQ resister. 
We’ll be mainly interested in the 
RXDone and TXDone bits.
Name 
(Address)
Bits Variable Name Mode Reset LoRaTM Description
Reg Irq Flags 
(0x12)
7 RxTimeout Read/clear 0x00 Timeout interrupt: a write operation clears IRQ
6 RxDone Read/clear 0x00 Packet reception complete interrupt: a write 
operation clears IRQ
5 PayloadCrcError Read/clear 0x00 Payload CRC error interrupt: a write operation 
clears IRQ
4 ValidHeader Read/clear 0x00 Valid header received in Rx: a write operation 
clears IRQ
3 TxDone Read/clear 0x00 FIFO Payload transmission complete interrupt: a 
write operation clears IRQ
2 CadDone Read/clear 0x00 CAD complete: write to clear: a write operation 
clears IRQ
1 FhssChangeChannel Read/clear 0x00 FHSS change channel interrupt: a write operation 
clears IRQ
0 CadDetected Read/clear 0x00 Valid Lora signal detected during CAD operation: a 
write operation clears IRQ
 
circuitcellar.com/ccmaterials
REFERENCE 
[1] G. Reiter, “Wireless connectivity for the 
Internet of Things,” Texas Instruments, 2014, 
www.ti.com/lit/wp/swry010/swry010.pdf.
SOURCES
Feather 32u4 Bluefruit LE
Adafruit | www.adafruit.com
RFM95W 868/915Mhz RF Transceiver Module
HOPE Microelectronics | www.hoperf.com
http://www.ti.com/lit/wp/swry010/swry010.pdf
http://www.adafruit.com
http://www.hoperf.com
www.circuitcellar.com/ccmaterials
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PHOTO 1 
These are the Feather32U4 boards I’m using for this project. Twin copies of Realterm are executing on 
my PC. These are connected through USB cables to the client and server PCBs. You can see the ongoing 
conversations taking place.
function. This assigns an input pin to interrupt 
routine and also defines the kind of operation 
that will cause the interrupt (a logic level or 
change in state).
INTERRUPTS 
In the setup(), we just described 
what it take to indicate that an interrupt 
event has taken place. Now, we need to 
define what happens when the event occurs 
with a function (named in setup()’s 
attachinterrupt() function). We are 
using one interrupt input to signal multiple 
potential radio events. We can determine 
what event caused the interrupt by reading 
the radio’s “IRQ Flags” register (see Table 3).
If we’ve enabled the Receive mode and 
either an RXTimeout or PayloadCRCError 
has occurred, then nothing (good) has been 
received and we can set Idle mode and leave. 
If the RXDone bit is set, then we want to read 
the received payload from the FIFO into our 
buffer, flag it as “good,” set Idle mode, and 
leave. If we’ve transferred a payload to send 
from the buffer to the FIFO and enabled the 
Transmit mode, then the radio will wrap our 
payload up and transmit it. When it has been 
sent, the TXDone bit is set. We don’t need to 
do anything since the work is done, except to 
set Idle mode and leave.
It’s worth noting here that the radio 
provides another function that may be of 
interest. The CAD mode can be used to check 
the radio for channel activity. In a busy 
environment, it may be advantageous to see 
if anyone else is transmitting, so you don’t 
trample their communication.
LOOP()
We finally arrive at the point where we 
can put all of this groundwork to good use. 
The main loop() will simply divide the 
application into one of two functions—that of 
client or server (based on my Boolean variable 
IamAServer). A client will transmit a packet 
to the server and look for some response. A 
server will monitor for a client’s request and 
respond to it. Photo 1 shows the set up for 
this column executing the Arduino sketch. 
You might picture an application where some 
sensor array is beyond the immediate area. 
Most wireless networks are somewhat limited 
in maximum distance—say, within the extents 
of your home. While you might be able to see 
a neighbor’s Wi-Fi network, its signal strength 
will most likely be weak and unreliable.
To test the LoRa radios, we’ll send a simple 
message between endpoints and look for 
confirming responses. One of the reasons for 
selecting the Feather32u4 is the inclusion of 
a Lithium cell charger that allows a module 
to run on one Lithium cell and be recharged 
via the USB connection. This enables one unit 
to become mobile so I can do some range 
testing. To aid in implementation, I will add 
a few items to this circuit, a couple of push 
buttons to adjust the radio’s TX power, and a 
small display to show the test results. I’ll be 
adding this to one radio so it can become a 
mobile test bed.
Next time, before we proceed with some 
range testing, we’ll look at the simple 
mechanism for implementing data 
transactions and what’s required to support a 
small I2C 128 × 64 pixel OLED display. This 
will provide up to eight rows of data in less 
than 1 square inch, at a parts cost of less than 
$10, and an increase in the current budget of 
only around 10 mA! 
Name 
(Address)
Bits Variable Name Mode Reset LoRaTM Description
Reg Irq Flags 
(0x12)
7 RxTimeout Read/clear 0x00 Timeout interrupt: a write operation clears IRQ
6 RxDone Read/clear 0x00 Packet reception complete interrupt: a write 
operation clears IRQ
5 PayloadCrcError Read/clear 0x00 Payload CRC error interrupt: a write operation 
clears IRQ
4 ValidHeader Read/clear 0x00 Valid header received in Rx: a write operation 
clears IRQ
3 TxDone Read/clear 0x00 FIFO Payload transmission complete interrupt: a 
write operation clears IRQ
2 CadDone Read/clear 0x00 CAD complete: write to clear: a write operation 
clears IRQ
1 FhssChangeChannel Read/clear 0x00 FHSS change channel interrupt: a write operation 
clears IRQ
0 CadDetected Read/clear 0x00 Valid Lora signal detected during CAD operation: a 
write operation clears IRQ
ABOUT THE AUTHOR
Jeff Bachiochi (pronounced BAH-key-AH-
key) has been writing for Circuit Cellar 
s ince 1988. His background inc ludes 
product des ign and manufac tur ing . 
You can reach himat jeff.bachiochi@
i m a g i n e t h a t n o w. c o m o r a t w w w. 
imaginethatnow.com.
www.imaginethatnow.com
mailto:jeff.bachiochi@imaginethtnow.com
CIRCUIT CELLAR • JUNE 2017 #32376
TE
ST
S 
&
 C
HA
LL
EN
G
ES
ACROSS
1. 10–5 N
3. Virtual barrier
4. At rest
5. Electrical union/connection
7. Describes circuit structure; Verilog
12. Electronics featuring semiconductors rather 
than mechanical circuits [2 words]
13. Pulse used to initiate a circuit action
14. LoRa [2 words]
15. Remove a wire’s jacket
16. NAND, OR, AND, NOT
17. Rubber, glass, air
18. Package for small- and medium-scale 
integrated circuits with up to approximately 
48 pins
19. Code that can detect single- and double-bit 
errors, and it can correct single-bit errors
CROSSWORD 
The answers will be available at circuitcellar.com/category/crossword/
JUNE 2017
1 2
3
4
5 6
7 8
9
10 11
12
13
14
15
16
17
18
19
EclipseCrossword.com
DOWN
2. 10–9 s
5. Secret point of access
6. Close proximity to an antenna [2 words]
8. 1337
9. Fixed-location wireless transceiver
10. m/s2
11. Limits surge
www.circuitcellar.com/category/crossword
circuitcellar.com 77
TESTS &
 CHALLENG
ES
TEST YOUR EQ 
Contributed by David Tweed 
ANSWERS TO EQ IN CIRCUIT CELLAR 322:
ANSWER 1—In the most general case, you would treat 
a binary (base 2) message as one giant number. To 
transmit that message through a channel that can only 
carry N different symbols, you’d convert that number to 
base N and transmit the resulting digits one at a time. 
In practice, you’d break a long data stream into fixed-
length blocks and then transmit those blocks one at a 
time, using the above scheme, possibly adding extra 
error detecting and/or correcting bits to each block.
ANSWER 2—For the specific case of 8-bit bytes through 
a 15-symbol channel, you might pick a block length of 
20 bytes, after noticing that 1541 is 1.6586 × 1048, just 
a little bit larger than 2160 = 1.4615 × 1048. Each block 
of 20 bytes would require 41 symbols to be transmitted, 
achieving an efficiency of 160/41 = 3.90 bits/symbol, 
which is very close to the theoretical maximum of 3.91 
bits/symbol that’s implied by having 15 states.
ANSWER 3—There are three important effects that the 
“lumped component” model (the model on which KVL 
and KCL are based) ignores: the fact that any circuit 
node of nonzero size has some capacitance (the ability 
to store charge) relative to the world at large; the 
fact that any circuit loop of nonzero size has some 
inductance (the ability to store energy in a magnetic 
field); and the fact that fields propagate at a specific 
velocity (e.g., at the speed of light in a vacuum). Note 
that “parasitic” capacitances and inductances can be 
explicitly added to a lumped component model (where 
relevant) in order to bring the analysis closer to reality. 
However, dealing with propagation speed issues (e.g., 
transmission line effects) requires a different kind of 
analysis. Such effects can only be crudely approximated 
in a lumped-component model.
ANSWER 4—There are a number of observables 
associated with a radio network. The contents of 
a message can be used to calculate distance if the 
transmitter reports its own position in a mutually 
agreed-upon coordinate system, and the receiver also 
knows its own position. The time of arrival can be used 
to calculate distance if the time that the message was 
transmitted is also known. Again, you can get this 
from the contents of the message if the transmitter 
and receiver have adequately synchronized clocks. 
The direction of arrival can be used (assuming the 
receiver’s antenna is directional enough) to determine 
the direction of the transmitter relative to the receiver’s 
orientation. Measurements from multiple transmitters 
can establish the receiver’s position (and hence its 
distance) relative to those transmitters. However, this is 
easily confused by signal reflections in the environment 
(multipath). The radio signal strength can also be used 
to estimate distance, but it is a measurement that 
depends on many things besides distance that need to 
be accounted for, such as antenna gain and orientation 
(at both ends), multipath and RF absorption, transmitter 
power level calibration. This makes it the least useful 
(and least accurate) way to measure distance.
More info: http://circuitcellar.com/category/test-your-eq/
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CIRCUIT CELLAR • JUNE 2017 #32378
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80 CIRCUIT CELLAR •JUNE 2017 #323
TE
CH
 T
HE
 F
U
TU
RE
The embedded FPGA is not new, but only recently has it started becoming a mainstream solution for designing chips, SoCs, 
and MCUs. A key driver is today’s high-mask costs of advanced 
ICs. For a chip company designing in high nodes, a change in RTL 
could cost millions of dollars and set the design schedule back 
by months. Another driver is constantly changing standards. The 
embedded FPGA is so compelling because it provides designers 
with the flexibility to update RTL at any time after fabrication, 
even in-system. Chip designers, management, and even the CFO 
like it.
Given these benefits, the embedded FPGA is here to stay. 
However, like any technology, it will evolve to become better and 
more widespread. Looking back to the 1990s when ARM and 
others offered embedded processor IP, the technology evolved 
to where embedded processors appear widely on most logic 
chips today. This same trend will happen with embedded FPGAs. 
In the last few years, the number of embedded FPGA suppliers 
has increased dramatically: Achronix, Adicsys, Efinix, Flex Logix, 
Menta, NanoXplore, and QuickLogic. The first sign of market 
adoption was DARPA’s agreement with Flex Logix to provide 
TSMC 16FFC embedded FPGA for a wide range of US government 
applications. This first customer was critical as it validated the 
technology and paved the way for others to adopt.
There are a number of things driving the adoption of the 
embedded FPGA:
• Mask costs are increasing rapidly: approximately $1 
million for 40 nm, $2 million for 28 nm, and $4 million 
for 16 nm. 
• The size of design teams required to design advanced 
node is increasing. Fewer chips are being designed, but 
they want the same functions as in the past. 
• Standards are constantly changing.
• Data centers require programmable protocols.
• AI and machine learning algorithms
Surprisingly, embedded FPGAs don’t compete with FPGA 
chips. FPGA chips are used for rapid prototyping and lower-
volume products that can’t justify the increasing cost of ASIC 
development. When systems with FPGAs hit high volume, FPGAs 
are generally converted to ASICs for cost reduction.
In contrast, embedded FPGAs don’t use external FPGAs and 
they can do things external FPGAs can’t, such as:
• They are lower power because SERDES aren’t needed. 
Standard CMOS interfaces can run 1 GHz+ in 16 nm 
for embedded FPGA with hundreds and thousands of 
interconnects available.
• Embedded FPGA is lower cost per LUT. There is no 
expensive packaging and a one-third of the die area of 
an FPGA chip is SERDES, PLLs, DDR PHYs, etc. that are no 
longer needed.
• 1-GHz operations in the control path
• Embedded FPGAs can be optimized: lots of MACs 
(Multiplier-Accumulators) for DSP or none; exactly the 
kind of RAM needed or none.
• Tiny embedded FPGAs of just 100 LUTs up to very large 
embedded FPGAs of greater than 100K LUTs
• Embedded FPGAs can be optimized for very low power 
operation or very high performance.
The following markets are likely to see widespread utilization 
of embedded FPGAs: the Internet of Things (IoT); MCUs and 
customizable programmable blocks on the processor bus; 
defense electronics; networking chips; reconfigurable wireless 
base stations; flexible, reconfigurable ASICs and SoCs; and AI and 
deep Learning accelerators.
To integrate embedded FPGAs, chip designers need them to 
have the following characteristics: silicon proven IP; density in 
LUTs/square millimeters similar to FPGA chips; a wide range of 
array sizes from hundreds of LUTs to hundreds of thousands of 
LUTs; options for a lot of DSP support and the kind of RAM a 
customer needs; IP proven in the process node a company wants 
with support of their chosen VT options and metal stack; an IP 
implementation optimized for power or performance; and proven 
software tools.
Over time, embedded FPGA IP will be available on every 
significant foundry from 180 to 7 nm supporting a wide range 
of applications. This means embedded FPGA suppliers must 
be capable of cost-effectively “porting” their architecture to 
new process nodes in a short time (around six months). This is 
especially true because process nodes keep getting updated over 
time and each major step requires an IP redesign.
Early adopters of embedded FPGA will have chips with wider 
market potential, longer life, and higher ROI, giving designers a 
competitive edge over late adopters. Similar benefits will accrue 
to systems designers. Clearly, this technology is changing the way 
chips are designed, and companies will soon learn that they can’t 
afford to "not" adopt embedded FPGA.
The Future of Embedded FPGAs
By Geoff Tate
Geoff Tate is CEO/Cofounder of Flex Logix Technologies. He earned a BSc 
in Computer Science from the University of Alberta and an MBA from 
Harvard University. Prior to cofounding Rambus in 1990, Geoff served as 
Senior Vice President of Microprocessors and Logic at AMD.
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