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A New Design for Precision Clock Synchronization Based on FPGA Yang. Kong, Jie.Wu, MP. Xie, Zhuan.Yu Abstract–NTP and IEEE1588 are two widely used protocols for clock synchronization in large distributed systems. NTP has its limitation that the synchronization accuracy is normally no better than 1 millisecond. The realization of the IEEE1588 system needs expensive components such as high-end microcontrollers or dedicated 1588 network hardware. This paper puts forward a method based on FPGA and short broadcast frames to realize a high level of synchronization accuracy between the master node clock and slave node clocks. When the master starts to synchronize, it sends a synchronous broadcast frame and memorizes this starting time in master clock. Each FPGA of the slave nodes, which needs to be synchronized, immediately returns a local node information frame as soon as it received the broadcast frame. FPGA in the Master measures and memorizes the return moment of each node information frame precisely, and then calculates the correct value for each node. According to these correct values, slave nodes modify the local time to make it consistent with the master clock. The experiment result, which is done with LVDS data signal on shot wire 10cm and long wire 55m, shows that the synchronization accuracy is better than 200 nanoseconds, and the system can maintain the synchronization accuracy for a long time. The measured values of clock offset between master and slave node clock match well with the theoretical values. Experiments show that this design based on FPGA can save CPU resources and transmission bandwidth effectively for a large distributed system. I. INTRODUCTION YNCHRONIZATION is very important for application systems such as acquisition systems which are mostly built on distributed environment. It is very hard to manage every node to work properly as a whole net without a synchronized clock. NTP and IEEE1588 are two widely used protocols for clock synchronization in large distributed systems. The Precision Timing Protocol (PTP) or IEEE 1588 is an emerging standard that addresses the weaknesses of current NTP implementations and provides the ability to deliver Manuscript received February 18, 2009. This work was supported in part by the Ministry of Science and Technology of China under Grant No.2008ZX05008-05A-004. Yang. Yong is with the Department of Modern Physics, University of Science and Technology of China, Hefei, CO 230026 China (telephone: 551- 3603654, e-mail: kongy@mail.ustc.edu.cn). Jie. Wu is with the Department of Modern Physics, University of Science and Technology of China, Hefei, CO 230026 China (telephone: 551-3606496, e-mail: wujie@ ustc.edu.cn). M.P. Xie is with the Department of Modern Physics, University of Science and Technology of China, Hefei, CO 230026 China (telephone: 551-3603654, e-mail: mpxie@mail.ustc.edu.cn). Zhuan. Yu is with the Department of Modern Physics, University of Science and Technology of China, Hefei, CO 230026 China (telephone: 551- 3606496, e-mail: yuzhuan@mail.ustc.edu.cn). timing and synchronization over network. The basic difference between PTP and NTP is that PTP time stamping is implemented in hardware. Achieving a high level of synchronization accuracy using IEEE 1588 requires dedicated hardware to timestamp messages as close to the physical layer as possible [1]. IEEE provide a multicast protocol to achieve synchronization for a large network system, but it: “Not scale well as the number of clocks increases” [2][3].Nevertheless, it was desirable to provide a new method to support time synchronization protocol for large distributed systems with a great number of nodes, without requiring Ethernet hardware. This paper puts forward a method based on FPGA and short broadcast frames to realize a high level of synchronization accuracy between the master node clock and slave node clocks for a large data acquisition system which based on LVDS transceivers. II. IEEE1588 Fig. 1. IEEE1588 synchronization process. IEEE 1588 is a master-slave synchronization protocol. The main functions of IEEE 1588 protocol are establishing the slave nodes clocks synchronized to the master clock and making the necessary information available for slave clocks to perform this synchronization [4]. Similar to other synchronization protocols, IEEE 1588 employs stamping certain messages. These special messages are defined as 5 types, which are called Sync message, Follow_Up message, S 2009 16th IEEE-NPSS Real Time Conference TDAP-6 978-1-4244-4455-7/09/$25.00 ©2009 IEEE 411Authorized licensed use limited to: Pontificia Universidade Catolica do Rio Grande do Sul (PUC/RS). Downloaded on September 13,2024 at 01:11:34 UTC from IEEE Xplore. Restrictions apply. Delay_Req message, Delay_Resp message and management message. For a given slave device, the offset O(t) at time t is defined by: ( ) ( ) ( )O t S t M t= − (1) where S(t) represents the time measured on the slave device's clock at physical time t, and M(t) represents the time measured on the master device's clock at physical time t. Each message exchange begins with a multicast sync message sent by the master clock to all the slaves listening on the PTP multicast group. A slave receiving this message takes note of the time T1 measured on its clock when it receives this message. The master next sends a multicast time t1 message to notify the slaves of time T0 when it sent the sync message. Each slave now knows T0 and T1. If d is the transit time of this message, and is the constant offset during this transaction, then 1 0T T O d− = + (2) Each slave now sends a respond message back to the master. For implementation reasons, this message is implemented as a multicast message, but it is a directed multicast message in that the packet containing this message includes information about the master it is being sent to. The slave measures the time T2 that it sends this message, and the master measures the time T3 that it receives this message. The master then sends a directed multicast time T3 message back to the slave to notify the slave what time it received the respond message. Note that 3 2T OT d− = − + (3) The slave now knows times T0, T1, T2, and T3. Combining the above two equations, we find that 1 2 0 3TO = 2 T T T+ − − (4) The slave now knows the offset during this transaction. While this offset will drift with time, it will be corrected the next time this exchange of transactions is launched [5]. Most papers related to IEEE 1588 assume that communication path between the master clock and the slave clock is symmetric. That’s the reason why one-way delay is calculated as in (3) [4], [6], [7], [8]. Slave nodes number is very important to a IEEE 1588 system. The more nodes are synchronized the more communication bandwidth is took. We take a 1000-nodes line for example (we assume synchronization interval is 32ms, and packet length is 64 Bytes which is the shortest value in Ethernet): ( ) ( )2 1000 64 8 1000 / 32 32 / Bitrate Byte ms ms Mbit S = × × × × = (5) Br is the theoretic bit rate of synchronization communication. This value reaches 32Mbit/s which is intolerable for this 64Mbit/s LVDS data line. Actually, multicast is used to solve this problem which will reduce nearly half of synchronization communication bandwidth, but even 16Mbit/s is unpractical. Furthermore, the behavior of systems building multicast out of point-to-point communications will not scale well as the number of clocks increases [4]. It can be seen clearly in nodes line. The slave nodes send Delay_Req messages at almost the same time, and that result a message transmission delta time which is shown in Fig 2. Fig.2. Delta-T influence on synchronization precision. Local data timing in Fig 2 indicates the theoretic moment at which Delay_Reqmessage should be send by local logic, and line data indicates the actual data stream timing in different line between each node. Delta-T equals to the time interval between the theoretic Delay_Req message sending moment and the actual Delay_Req message sending moment. 412Authorized licensed use limited to: Pontificia Universidade Catolica do Rio Grande do Sul (PUC/RS). Downloaded on September 13,2024 at 01:11:34 UTC from IEEE Xplore. Restrictions apply. When line1 of slave1 is busy, all the data of line2 must be stored in local buffer and will be sent few clocks latter. Since the instantaneous stream density is much greater than the channel bandwidth, the more nodes there are in data line the worse line accumulation time can be. Sync messages are broadcast messages and Delta-T delay only exist on Delay_Req message transmissions, so the D parameter in master-to-slave channel is not equal to what in slave-to-master channel. Delta-T affects synchronization precision by its half value multiply the number slave nodes, and this affection can reach millisecond range. Conclusions above are carried out on the premise of all nodes in a serial data line. If there is a ramose structure in the zone to be synchronized by one broadcast sync message, situations turn to be very complicated, and the data bandwidth in each ramification is very important to synchronization precision. III. SHORT FRAME SOLUTION IN This short frame solution is designed for a large distributed data acquisition system. This system consists of a mass of data unit (D-units) and some transmission units (T-units) which are shown in Fig 3. T-units are the first level unit, and D-units are the second level units. Fig. 3. Large Distributed Data Acquisition System D-unit to D-units and D-units to T-units data-lines are based on LVDS transmission, and T-units to T-units are based on Gigabit Ethernet technology. Synchronization precisions are tested on LVDS unit’s transmission line. The transceivers SN65LV1023/ SN65LV1024 produced by Texas Instruments and FPGA XC3S100E produced by Xilinx are the main data- line chips. The short frame for this distributed system is much shorter than IEEE 1588 Ethernet frame which has a minimal 64 Byte length. Frame segment and exact frame length value which is 14 Byte in this application can be set as the designer like and this design can save a lot of bandwidth. Fig 4 shows the short frame segment. (4 Bits) TypeTarget address Target UnitSource address Source address: slave node address Type: Target Unit: (6 Byte) (6 Byte) (4 Bits) Target address: Short frame segment 0x1 Sync respond message 0x0 Sync broadcast message 0x0 T-unit 0xfffffffffffe Checksum (1 Byte) Checksum: 1 Byte checksum 0x1 D-unit Fig. 4. Short Frame Segment Fig. 5. Unit Hardware Structure Target address area is a 6-bytes 0xfffffffffffe address, this apart a short frame message frame from other data frames. A frame consists of Target address, Source address, Type, Target Unit and Check sum only if the first six byte of the frame is 0xfffffffffffe. Source address area is a 6-bytes address to identify the source of the frame. This address should be used as a target address by slave units in a respond frame. Type and Target Unit are two 4-bit symbols to indicate message type (broadcast message or respond message) and target unit type (D-unit or T-unit). Sync broadcast messages and Sync respond messages consist of short frames, and Delay Modify messages are similar to Ethernet broadcast frames which are more complex and contain more information. Fig 6 shows these master slave communications. The master send a Sync message and the slave returns a Delay message to make sure they can register the exact time of t0, t1, t2, and t3. This protocol does not contain a Follow_Up message. FPGA logic of slave nodes with special design is very important to remove Delta T affection. The transmit logic of slave nodes add a 16-Byte delay for each package. This delay 413Authorized licensed use limited to: Pontificia Universidade Catolica do Rio Grande do Sul (PUC/RS). Downloaded on September 13,2024 at 01:11:34 UTC from IEEE Xplore. Restrictions apply. makes the point to point message transmission time almost a fixed value. Fig. 6. Short Frame synchronization process. When the master starts to synchronize, it sends a Sync broadcast message and memorizes this starting time (T0) exactly in master clock register. When a salve node detect a full frame of sync message, it register the receiving start time (T1) by its local clock and start to send back a Sync respond message a few clocks later after the sync message because these are done in FPGA logic. Sync respond message have the same segment of short frame segment .There is no CPU participation in creating and sending Sync respond messages and The exactly time (T2) of sending this Sync respond message is also memorize by the slave nodes. As a result of the Sync broadcast message, the master gets a large amount of Sync respond messages of all salve nodes. As there is a source address information in short frame segment, the master memorize the exactly receiving time (T3) of each Sync respond message and its source address in FPGA. The Master will send T0 and T3 to the salve as soon as it gets T3. The whole system can not get synchronization by a single sync process because the system has a ramose structure. There is a great synchronization accuracy losing at the data-line cross points. The more D-units there are in a T-line the more accuracy it loses. A two level synchronization solution must be used to make T-units and D-units get synchronized independently. At first, T-units are synchronized to the control machine by a T-unit broadcast (the Target Unit zone is filled with 0x0). After that, T-units send D-unit broadcast (the Target Unit zone is filled with 0x1) to control the D-units synchronize to them. The whole system reach synchronization by this two-level sync and the units of these two levels keep synchronization separately. IV. RESULTS AND CONCLUSION A lot of tests have been done on D-unit data lines. The D- unit interval can be as far as 55 meters and synchronization precision also be tested with 5 meters and 12 meters transmission lines. Experiment on 12 meters D-unit data lines shows that the synchronization accuracy is better than 200 nanoseconds with this new short frame protocol based on FPGA. Experiments on data lines with other length such as 5 meters and 55 meters came out the same accuracy level. Fig. 7. Synchronization Pulse. In conclusion, this new short frame solution can save data line bandwidth effectively and make the system get rid of dedicated synchronization hardware. FPGA based short frame solution over LVDS transmission line can be used to synchronize a network of distributed data acquisition system. REFERENCES [1] Rosselot David, “Simple, accurate time synchronization in an ethernet physical layer device,” 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, ISPCS 2007 Proceedings, pp. 123–127, 2007 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control and Communication, ISPCS 2007 Proceedings. [2] IEEE Instrumentation and Measurement Society, “IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (IEEE Std 1588-2002).”. [3] IEEE Instrumentation and Measurement Society, “IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (IEEE Std 61588-2004).”. [4] Lee Sungwon, “ An enhanced IEEE 1588 time synchronization algorithm for asymmetric communication link using block burst transmission,” IEEE Communications Letters, v 12, n 9, p 687-689, 2008.[5] Eidson, John C, Measurement, Control and Communication Using IEEE 1588,(April 2006).,ISBN 1-8462-8250-0. [6] T. Cooklev, J. C. Eidson, and A. Pakdaman, “An implementation of IEEE 1588 over IEEE 802.11b for synchronization of wireless LAN area network nodes,” IEEE Trans. Instrumentation and Measurement, vol. 56, no. 5, pp. 1632–1639, Oct. 2007. [7] P. Ferrari, A. Flammini, D. Marioli, and A. Taroni, “IEEE 1588 based synchronization system for a displacement sensor network,” IEEE Trans. Instrumentation and Measurement, vol. 57, no. 2, Feb. 20081992. [8] A. Vallat and D. Scheuwly, “Clock synchronization in telecommunications via PTP (IEEE 1588),” in Proc. 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