Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1711

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Step 1 of 2 15.043P The CPL (complementary pass transistor logic) for the expression Z= ABC and as follows: B B C Y = AB A Z = ABC B C X A B Figure 1 Step 2 of 2 From Figure 1, the expression at node Y is the logical AND operation of A and B. the output Z is the logical AND operation of Y and the input C. Z = ABC In Figure 1, the expression at the node X is, = X=A+B The output Z is, (since X+XY=X+Y) Thus, the CPL's for the expression Z=ABC and Z=A+B+C = is shown in Figure 1.