Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1661

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Step of 4 15.006P Refer to Figure 13.22 in the text book. (a) Just prior to the leading edge of the input pulse (i.e., at = ), the output voltage is equal to At time v, raises to causing turn OFF and to turn ON. Thus, the transistor operates in saturation at and supplies relatively large current to begin the process of discharging capacitance. The output voltage, reduces from to during the interval PHL = Thus, the expression for high to low propagation delay is, 'PHL Step 2 of 4 (b) Write the expression for equivalent resistance of RN 12.5 Derive the expression for high to low propagation delay. 'PHL Substitute for RN in the equation. 'PHL Thus, the expression for high to low propagation delay is, Step of 4 (c) Determine the value of voltage, for NMOS transistor. Substitute for 'PHL in the equation. Substitute in the equation. (1) Step of 4 Substitute 1.2 V for 0.4 V for 325 for in equation (1). The value of =1.26 V is greater than the supply voltage. So, this value is not acceptable. Thus, the value of voltage, for NMOS transistor is 0.339 V