Digital Design_ Principles and Practices, Chegg Solution Manual_parte_238

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Step of 4 6.036E Write a VHDL program for a generic 3-to-8 binary decoder with active-high inputs and outputs, based on Table 6-17 but with only a single enable input. Then write a second VHDL program, based on Table 6-16, that instantiates the first module to emulate a74x138, including multiple enable inputs. Draw a block diagram similar to Figure 6-42 that shows the relationship between the modules. Synthesize both Table 6- 16 and the second module for a CPLD of your choice, and compare the synthesized results. Explain any differences. Step of 4 VHDL program for a generic 3-to-8 binary decoder, active-high inputs and outputs, based on Table 6-17 (Refer chapter 6 in the textbook) but with only a single enable input. VHDL program; library IEEE; use entity decoder is in std_logic_vector(2 downto 0); Y out std_logic_vector(0 to 7)); end decoder; architecture behavioral of decoder is signal Y_S : std_logic_vector(0 to 7); with A select Y