Digital Design_ Principles and Practices, Chegg Solution Manual_parte_190

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Step of 4 5.027E The test bench VHDL program for prime number detector circuit is written below, library IEEE; use entity prime_tb is end prime_tb; architecture prime_tb_arch of tb is component prime port (N: in STD_LOGIC_VECTOR (3 downto 0); F: out STD_LOGIC); end component; signal Num: STD_LOGIC_VECTOR (3 downto 0), prime_out: bit; // begin U1: prime port map Num, prime_out); process begin report "Beginning of test bench" severity Step 2 of 4 //Continue the above program Num