Digital Design_ Principles and Practices, Chegg Solution Manual_parte_356

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Step of 3 7.065E test bench the program ibonacci sequence Testbench: library use IEEE LOGIC USE IEEE STD LOGIC ENTITY Fibo IS ARCHITECTURE arch OF FILE RESUL TEXT OPEN WRITE MODE COMPONENT CLK logic RESET D logic vector FIB InOut logic vector DONE END COMPONENT SIGNAL CLK SIGNAL RESET logic SIGNAL std logic vector DownTo "0000"; SIGNAL SIGNAL DONE std SHARED ERROR INTEGER SHARED VARIABLE OUT constant PERIOD time constant CYCLE real constant FFSET time BEGIN RESET DONE DONE PROCESS clock process CLK BEGIN WAI LOOP LOOP FOR (PERIOD DUTY PROCESS PROCEDURE CHECK next DONE logic; TIME INTEGER VARIABLE STR String(1 VARIABLE LOC BEGIN (DONE next DONE) THEN STD write(TX "Error STD TEXTIO STD TEXTIO STD EXTIO Expected STR(TX STD TEXTIO ASSERT FALSE REPORT TX STR SEVERITY (ERROR ERROR END; BEGIN Current 85ns RESET FIB Step 2 of 3 Current Time WAI FOR RESET Current FOR FIB Current Time: 685ns FOR Current WAIT Current 1085ns WAIT FIB Current 1115ms WAI FOR Current Time WAI FOR "1000" FIB Current Time 1315ms WAI FOR ERROR THEN errors STD TEXTIO TX_OUT): ASSERT (FAI REPORT "Simulation successful (not failure) No problems SEVERITY ELSE errors found TEXTIO ASSERT (FAL SE) REPORT Errors found during simulation" SEVERITY Step The waveforms shown in the Figure - - Figure Assume state sequence holds the previous outputs. When RESET asserted starts counting