Digital Design_ Principles and Practices, Chegg Solution Manual_parte_293

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Step 1 of 2 6.096E A 24-bit comparator is designed using three 74X682 one 74X27 and one 74X02 as shown in Figure 1. P 74x682 74x682 PO 2 PO PO 3 & Q16 & Pt 4 Pt P17 Pt 5 017 P2 6 P2 P2 02 7 018 19 2 Q2 P3 8 PEQQ Q2 P3 P19 P3 PEQQ 9 & 019 Q3 P4 11 P20 P4 1GT0_ P4 04 12 PGTQ 020 04 1 2 04 P5 13 P21 PGTQ PS PS 14 021 P6 P22 P6 P6 16 022 P7 17 P23 P7 P7 18 023 & U1 U3 74x682 74X27 12 PEQQ 2 P8 2 13 3 U4 P9 4 3 74X27 09 6 Pt PO 04 P4 P7 P6 PS P2 P3 4 6 5 7 19 74X02 8 U4 74X27 74X02 8 2 9 EQI_L 11 10 PGTQ 1 8 9 3 10 P12 11 US Q12 12 9 U4 1 US P13 13 5 74X02 013 14 GT1_L 8 4 P14 15 16 US P15 17 015 18 U2 Figure 1 Step 2 of 2 Figure 1 shows that the output is asserted when P=Q or > PEQQ is asserted when P=Q, = and PGTQ is asserted when P>Q. >