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Step 1 of 3 7.05DP An SR latch of the type shown in Figure 7-5 in textbook has the following assumptions. (i) Propagation delay of NOR gate is (ii) Input & output of SR latch rise and fall time is consider to be zero. (iii) Time division is 10 ns The input waveforms are shown in Figure X7.5 in textbook. In general the rise time and fall time for SR latch with two NOR gate can be calculated using propagation delay of two NOR gates and Rise time is given as follows, Fall time is given as follows, It is also noted that when both inputs (S and R) are changed simultaneously, then the output is ambiguous. The output will oscillate from 1 to 0 and 0 to 1. Step 2 of 3 The truth table for SR latch is, S R QN 00 last Q last QN 01 0 101 0 11 0 0 Table 1 Step 3 of 3 Considering the NOR gate delay and truth table, the output waveform for SR latch is given as follows, S R Q QN Figure 1: Output waveform for SR latch.