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Step 1 of 4 9.007E There are total 128 possible combinations of 64 product terms are possible and the final output will be the canonical sum of those terms. Here only 8 of them would be demonstrated. In Figure 9-6 according to the high order inputs (A4, A5, and A6) 74x138 asserted row (word) line will be low which will pull the corresponding column (bit) line low. Now according to the low order inputs (A3, A2, A1, and A0) the corresponding bit line will be selected and transmitted to the output of multiplexer. Step 2 of 4 Consider the following truth table. Table 1 High order address bits Low order address bits Y A6 A5 A4 A3 A2 A0 0 0 1 0 1 1 1 B7(0) 0 1 0 0 1 1 1 B7(0) 0 1 0 0 1 0 1 B5(1) 0 1 1 0 1 0 1 B5(0) 0 1 1 1 0 0 0 B8(1) 1 1 1 1 0 0 0 B8(0) 0 0 0 1 1 1 1 B15(0) 1 0 0 0 1 0 1 B5(1) Step 3 of 4 Consider the following truth table. Table 2 Output bits B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 Step 4 of 4 The first case is explained as follows. When high order input bits are selected as 010, the 5th row is asserted as Now if there are any diodes connected between row and column the corresponding column (bit) line will be pulled low. Here 7th, 11th, 13th, 14th, 15th column (bit) line will be pulled low. Finally, depending on the value of low order input bits as 0101, the corresponding column (bit) line which is B5 will be transmitted to the output.