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Step 1 of 1 8.076E Refer to the ABEL program for a timing generator from Table 8-31 in the textbook. Consider that this timing generator is used to control a dynamic memory system. Consider also that the memory contents corrupt, if the timing generator resets without completing all six phases. Modify the program in Table 8-31 to overcome this situation: module TIMING6 title Master Timing "Input and Output pins MCLK, RESET, RUN, RESTART pin; 'reg'; "State definitions equations T1.CLK = MCLK; PHASES.CLK = MCLK; when RESET and PHASES = [1, 1, 1, 1, 1, 0] then [T1 := 1; PHASES := SRESET;} else when (PHASES = SRESET) # RESTART then := 1; PHASES := P1;} else when RUN & T1 then {T1 := 0; PHASES := PHASES;} else when RUN & !T1 then {T1 := 1; PHASES := NEXTPH;} else {T1 := T1; PHASES := PHASES;} end TIMING6