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Step of 5 5.10DP Consider the NAND gate based logic circuit, A M1_L B_L X A_L B M2_L M3_L C Y M4_L Figure 1: NAND gate based logic circuit Step of 5 The structural VHDL program for the above NAND gate based logic circuit is as shown below, library IEEE; use entity nand_circuit is port in STD_LOGIC; X,Y out STD_LOGIC); end nand_circuit; architecture nand_circuit_arch of circuit is signal component INV port( I: in STD_LOGIC; O: out STD_LOGIC); end component; component NAND2 port( inp1, inp2: in STD_LOGIC; out1: out STD_LOGIC); end component; component INV_OR2 port( inp1, inp2: in STD_LOGIC; out1: out STD_LOGIC); end component; begin U1: INV port map (A, A_L); U2: INV port map (B, B_L); U3: NAND2 port map (A, B_L, U4: NAND2 port map (A_L, B, M2_L); U5: NAND2 port map (A_L, C,M3_L); U6: NAND2 port map (B, C, M4_L); U7: INV_OR2 port map (M1_L, M2_L, X); U8: INV_OR2 port map end nand_circuit_arch; Step of 5 component description INV entity INV is port in STD_LOGIC; O: out STD_LOGIC); end architecture INV_arch of INV is begin not (1); end INV_arch; Step of 5 component description NAND2 entity NAND2 is port (inp1, inp2: in out1: out end architecture NAND2_arch of NAND2 is begin out1