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Step of 1 6.049E The verilog module for the seven segment decoder can be written starting with the specifications given in Exercise 6.48 (Refer to chapter 6) for all the conditions mentioned in the problem as follows by keeping in mind that all the outputs are active low. Verilog Program: Write the VHDL program as follows: module input A,B,C,D,EN,ENHEX,ERRDET; output sega,segb,segc,segd,sege,segf,segg; reg reg [1:7] segs; always @(A or B or C or D or EN or ENHEX or ERRDET) begin if (EN=='1' & ENHEX == '0') begin case ([D,C,B,A}) // segment patterns abcdefg 2:segs=7'b1101101; 3:segs=7'b1111001; 4:segs=7'b0110011; 1/6 (with 'tail') (with 4'b1010:segs = 7'b0001000; 4'b1011:segs = 7'b1000010; 4'b1100:segs = 7'b0000111; 4'b1101:segs = 7'b0000001; 4'b1110:segs = 7'b0110000; 4'b1111:segs = 7'b0000110; Default segs=7'bx; endcase else segs=7'b0; }=segs; end when ENHEX = 1 and ERRDET = 0, then the outputs for digits A-F look like the letters A-F as in the original program. else If( ENHEX == '1' & ERRDET ==' 0') begin 4'b1010:segs = 7'b0001000; 4'b1011:segs = 7'b1000010; 4'b1100:segs = 7'b0000111; I/C 4'b1101:segs = 7'b0000001; 4'b1110:segs = 7'b0110000; 4'b1111:segs = 7'b0000110; //F Default segs=7'bx; endcase else segs=7'b0; }=segs; End when ENHEX = 1 and ERRDET = 1, then the digits A-F look like the letter S. else If (ENHEX == '1' and ERRDET == '1') begin case ([D,C,B,A}) // segment patterns abcdefg 1/6 (with 'tail') 9:segs=7'b1111011; (with 'tail') 4'b1010:segs = 7'b0001000; 4'b1011:segs = 7'b1000010; 4'b1100:segs = 7'b0000111; 4'b1101:segs = 7'b0000001; 4'b1110:segs = 7'b0110000; 4'b1111:segs = 7'b0000110; Default segs=7'bx; endcase else segs=7'b0; }=segs; end endmodule