Aula 06 VHDL para MUX e Decoders

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Implementação VHDL
Estruturas disponíveis na 
linguagem
Prof. Edward David Moreno
edwdavid@gmail.com
Estruturas
Uma implementação em VHDL pode 
utilizar várias estruturas disponíveis na 
linguagem:
� Execução concorrente com 
WITH...SELECT;
� Execução seqüencial com 
IF...THEN...ELSE;
� Execução seqüencial com CASE;
� Implementação com portas lógicas.
Exemplo 1: Multiplexador
(a)– Representação;
(b)– Tabela verdade;
(c)– Descrição com portas lógicas.
Usando WITH...SELECT
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux is
port (
e1,e2,sel: in STD_LOGIC;
s: out STD_LOGIC
);
end Mux;
architecture Mux_arch of Mux is
begin
with sel select
s<= e1 when '0',
e2 when others;
end Mux_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 1
� LUTs3: 0
� CLBs: 1
Temporização:
� TL: 6,899ns
� TR: 3,336ns
� AT: 10,235ns
Usando IF...THEN...ELSE
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux is
port (
e1,e2,sel: in STD_LOGIC;
s: out STD_LOGIC
);
end Mux;
architecture Mux_arch of Mux is
begin
process(e1,e2,sel)
begin
if sel='0' then
s<=e1;
else
s<=e2;
end if;
end process;
end Mux_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 1
� LUTs3: 0
� CLBs: 1
Temporização:
� TL: 6,899ns
� TR: 3,336ns
� AT: 10,235ns
Usando CASE
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux is
port (
e1,e2,sel: in STD_LOGIC;
s: out STD_LOGIC
);
end Mux;
architecture Mux_arch of Mux is
begin
process(e1,e2,sel)
begin
case sel is
when '0' => s <= e1;
when others => s <= e2;
end case;
end process;
end Mux_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 1
� LUTs3: 0
� CLBs: 1
Temporização:
� TL: 6,899ns
� TR: 3,336ns
� AT: 10,235ns
Usando Portas Lógicas
library IEEE;
use IEEE.std_logic_1164.all;
entity Mux is
port (
e1,e2,sel: in STD_LOGIC;
s: out STD_LOGIC
);
end Mux;
architecture Mux_arch of Mux is
begin
s <= (e1 and not(sel)) or (e2 and sel);
end Mux_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 1
� LUTs3: 0
� CLBs: 1
Temporização:
� TL: 6,899ns
� TR: 3,336ns
� AT: 10,235ns
Resumo das Estatísticas
Ocupação
Temporização
Multiplexador FF LUTs4 LUTs3 CLBs
WITH...SELECT 0 1 0 1
IF...THEN...ELSE 0 1 0 1
CASE 0 1 0 1
PORTA LÓGICA 0 1 0 1
Multiplexador TL TR AT
WITH...SELECT 6,899ns 3,336ns 10,235ns
IF...THEN...ELSE 6,899ns 3,336ns 10,235ns
CASE 6,899ns 3,336ns 10,235ns
PORTA LÓGICA 6,899ns 3,336ns 10,235ns
Exemplo 2: Decodificador 3x8
s(0)
s(1)
s(2)
s(3)
s(4)
s(5)
s(6)
s(7)
x(2)x(1)x(0)
Usando WITH...SELECT
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3x8 is
port (
x: in STD_LOGIC_VECTOR (2 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0)
);
end dec3x8;
architecture dec3x8_arch of dec3x8 is
begin
with x select
s <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"ZZZZZZZZ" when others;
end dec3x8_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 8
� LUTs3: 0
� CLBs: 4
Temporização:
� TL: 6,899ns
� TR: 5,079ns
� AT: 11,978ns
Usando IF...THEN...ELSE
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3x8 is
port (
x: in STD_LOGIC_VECTOR (2 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0)
);
end dec3x8;
architecture dec3x8_arch of dec3x8 is
begin
process(x)
begin
if (x = "000") then s<= "00000001";
elsif (x = "001") then s<= "00000010";
elsif (x = "010") then s<= "00000100";
elsif (x = "011") then s<= "00001000";
elsif (x = "100") then s<= "00010000";
elsif (x = "101") then s<= "00100000";
elsif (x = "110") then s<= "01000000";
elsif (x = "111") then s<= "10000000";
else s <= "ZZZZZZZZ";
end if;
end process;
end dec3x8_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 8
� LUTs3: 0
� CLBs: 4
Temporização:
� TL: 6,899ns
� TR: 5,079ns
� AT: 11,978ns
Usando CASE
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3x8 is
port (
x: in STD_LOGIC_VECTOR (2 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0)
);
end dec3x8;
architecture dec3x8_arch of dec3x8 is
begin
process(x)
begin
case x is
when "000" => s <= "00000001";
when "001" => s <= "00000010";
when "010" => s <= "00000100";
when "011" => s <= "00001000";
when "100" => s <= "00010000";
when "101" => s <= "00100000";
when "110" => s <= "01000000";
when "111" => s <= "10000000";
when others => s <= "ZZZZZZZZ";
end case;
end process;
end dec3x8_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 8
� LUTs3: 0
� CLBs: 4
Temporização:
� TL: 6,899ns
� TR: 5,079ns
� AT: 11,978ns
Usando Portas Lógicas
library IEEE;
use IEEE.std_logic_1164.all;
entity dec3x8 is
port (
x: in STD_LOGIC_VECTOR (2 downto 0);
s: out STD_LOGIC_VECTOR (7 downto 0)
);
end dec3x8;
architecture dec3x8_arch of dec3x8 is
begin
s(0) <= not (x(2)) and not (x(1)) and not (x(0));
s(1) <= not (x(2)) and not (x(1)) and x(0);
s(2) <= not (x(2)) and x(1) and not (x(0));
s(3) <= not (x(2)) and x(1) and x(0);
s(4) <= x(2) and not (x(1)) and not (x(0));
s(5) <= x(2) and not (x(1)) and x(0);
s(6) <= x(2) and x(1) and not (x(0));
s(7) <= x(2) and x(1) and x(0);
end dec3x8_arch;
Estatísticas
Recursos Utilizados:
� FF: 0
� LUTs4: 8
� LUTs3: 0
� CLBs: 4
Temporização:
� TL: 6,899ns
� TR: 7,872ns
� AT: 14,771ns
Resumo das Estatísticas
Ocupação
Temporização
Decodificador FF LUTs4 LUTs3 CLBs
WITH...SELECT 0 8 0 4
IF...THEN...ELSE 0 8 0 4
CASE 0 8 0 4
PORTA LÓGICA 0 8 0 4
Decodificador TL TR AT
WITH...SELECT 6,899ns 5,079ns 11,978ns
IF...THEN...ELSE 6,899ns 5,079ns 11,978ns
CASE 6,899ns 5,079ns 11,978ns
PORTA LÓGICA 6,899ns 7,872ns 14,771ns
Somador Completo (4 bits)
library IEEE;
use IEEE.std_logic_1164.all;
entity somador4bits is
port (
cin: in STD_LOGIC;
a,b: in STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: out STD_LOGIC;
s: out STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end somador4bits;
architecture somador4bits_arch of somador4bits is
begin
process(a,b,cin)
variable soma:std_logic_vector(3 downto 0);
variable c:std_logic;
begin
c := cin;
for i in 0 to 3 loop
soma(i) := a(i) xor b(i) xor c;
c := (a(i) and b(i)) or ((a(i) xor b(i)) and c);
end loop;
cout <= c;
s <= soma;
end process;
end somador4bits_arch;