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transitions. Rung
transitions can be caused by events occurring in the program (from internal logic or
by external field devices) such as parts traveling past a detector or actuating a limit
switch.
When rung conditions for a CTU instruction have made a false-to-true transition,
the accumulated value is incremented by one count, provided that the rung
containing the CTU instruction is evaluated between these transitions. The ability
of the counter to detect false–to–true transitions depends on the speed (frequency) of
the incoming signal.
Note The on and off duration of an incoming signal must not be faster than the scan time
2x (assuming a 50% duty cycle).
The accumulated value is retained when the rung conditions again become false.
The accumulated count is retained until cleared by a reset (RES) instruction that has
the same address as the counter reset.
Using Status Bits
This Bit Is Set When And Remains Set Until One of theFollowing
Count Up Overflow Bit OV
(bit 12)
accumulated value wraps
around to –32,768 (from
+32,767) and continues
counting up from there
a RES instruction having the same
address as the CTU instruction is
executed OR the count is
decremented less than or equal to
+32,767 with a CTD instruction
Done Bit DN (bit 13) accumulated value is equal
to or greater than the preset
value
the accumulated value becomes
less than the preset value
Count Up Enable Bit CU
(bit 15)
rung conditions are true rung conditions go false OR a RES
instruction having the same address
as the CTU instruction is enabled
The accumulated value is retained after the CTU instruction goes false, or when
power is removed from and then restored to the controller. Also, the on or off status
of counter done, overflow, and underflow bits is retentive. The accumulated value
and control bits are reset when the appropriate RES instruction is enabled. The CU
bits are always set prior to entering the REM Run or REM Test modes.
3333 333
(CU)
(DN)
CTU
COUNT UP
Counter C5:0
Preset 120
Accum 0
Output Instruction
Basic Instructions
1–25
Count Down (CTD)
The CTD is an instruction that counts false-to-true rung transitions. Rung
transitions can be caused by events occurring in the program such as parts traveling
past a detector or actuating a limit switch.
When rung conditions for a CTD instruction have made a false-to-true transition,
the accumulated value is decremented by one count, provided that the rung
containing the CTD instruction is evaluated between these transitions.
The accumulated counts are retained when the rung conditions again become false.
The accumulated count is retained until cleared by a reset (RES) instruction that has
the same address as the counter reset.
Using Status Bits
This Bit Is Set When And Remains Set Until Oneof the Following
Count Down Underflow Bit UN
(bit 11)
accumulated value wraps
around to +32,767 (from
–32,768) and continues
counting down from there
a RES instruction having the
same address as the CTD
instruction is enabled. OR
the count is incremented
greater than or equal to
+32,767 with a CTU
instruction
Done Bit DN (bit 13) accumulated value is equal
to or greater than the preset
value
the accumulated value
becomes less than the preset
Count Down Enable Bit CD
(bit 14)
rung conditions are true rung conditions go false OR
a RES instruction having the
same address as the CTD
instruction is enabled
The accumulated value is retained after the CTD instruction goes false, or when
power is removed from and then restored to the controller. Also, the on or off status
of counter done, overflow, and underflow bits is retentive. The accumulated value
and control bits are reset when the appropriate RES instruction is executed. The CD
bits are always set prior to entering the REM Run or REM Test modes.
3333 333
(CD)
(DN)
CTD
COUNT DOWN
Counter C5:1
Preset 120
Accum 0
Output Instruction
PrefaceInstruction Set Reference Manual
1–26
High-Speed Counter (HSC)
The High-Speed Counter is a variation of the CTU counter. The HSC instruction is
enabled when the rung logic is true and disabled when the rung logic is false.
For information on using the high-speed counter instruction, see chapter 7.
Note The HSC instruction counts transitions that occur at input terminal I:0/0. The HSC
instruction does not count rung transitions. You enable or disable the HSC rung to
enable or disable the counting of transitions occurring at input terminal I:0/0. We
recommend placing the HSC instruction in an unconditional rung. Do not place the
XIC instruction with address I:0/0 in series with the HSC instruction because counts
will be lost.
The HSC is a special CTU counter for use with 24 VDC SLC fixed and 24 VDC
MicroLogix 1000 controllers. The HSC’s status bits and accumulated values are
non-retentive.
Note This instruction provides high-speed counting for fixed I/O controllers with 24 VDC
inputs. One HSC instruction is allowed per controller. To use the instruction, you
must cut the jumper as shown below. A shielded cable is recommended to reduce
noise to the input.
High-Speed Counter Operation
For high-speed counter operation you must do the following:
1. Turn off power to the fixed controller.
2. Remove the SLC 500 cover.
3. Locate and cut jumper wire J2. Do not remove completely but make certain
that the ends of the cut jumper wire are not touching each other.
33
HIGH SPEED COUNTER
Counter C5:0
Preset 120
Accum 0
(CU)
(DN)
HSC
Output Instruction
Basic Instructions
1–27
J2J2
The High–Speed Counter jumper is located either beneath
the battery connector OR to the right of the battery connector.
4. Replace the cover.
Note Input I:0/0 then operates in the high-speed mode. The address of the high–speed
counter enable bit is C5:0/CU. When rung conditions are true, C5:0/CU is set and
transitions occurring at input I:0/0 are counted.
To begin high-speed counting, load a preset value into C5:0.PRE and enable the
counter rung. To load a preset value, do one of the following:
• Change to the REM Run or REM Test mode from another mode.
• Power up the processor in the REM Run mode.
• Reset the HSC using the RES instruction.
Automatic reloading occurs when the HSC itself sets the DN bit on interrupt.
Each input transition that occurs at input I:0/0 causes the HSC accumulated value to
increment. When the accumulated value equals the preset value, the Done bit
(C5:0/DN) is set, the accumulated value is cleared, and the preset value (C5:0.PRE)
is loaded into the HSC in preparation for the next high-speed transition at input
I:0/0.
Your ladder program should poll the Done bit (C5:0/DN) to determine the state of
the HSC. Once the Done bit has been detected as set, the ladder program should
clear bit C5:0/DN (using the unlatch OTU instruction) before the HSC accumulated
again reaches the preset value, or the overflow bit (C5:0/OV) will be set.
PrefaceInstruction Set Reference Manual
1–28
The HSC differs from the CTU and CTD counters. The CTU and CTD are software
counters. The HSC is a hardware counter and operates asynchronously to the ladder
program scan. The HSC accumulated value (C5:0.ACC) is normally updated each
time the HSC rung is evaluated in the ladder program. This means that the HSC
hardware accumulator value is transferred to the HSC software accumulator. Only
use the OTE instruction to transfer this value. The HSC instruction immediately
clears bit C5:0/UA following the accumulated update.
Many HSC counts may occur between HSC evaluations, which would make
C5:0.ACC inaccurate when used throughout