A maior rede de estudos do Brasil

Grátis
LogixProCCZF

Pré-visualização | Página 50 de 50

to +32,767. You can
reset this bit with an OTU instruction or by executing an RAC or RES
instruction.
• Update High-Speed Counter Accumulator Bit UA (bit 10) is used with an
OTE instruction to update the instruction image accumulator value with the
hardware accumulator value. (The HSC instruction also performs this operation
each time the rung with the HSC instruction is evaluated as true.)
• Accumulator ≥ High Preset Bit HP (bit 9) is a reserved bit for all Up
Counters (modes 1 and 2).
For the Bidirectional Counters (modes 3–8), if the hardware accumulator
becomes greater than or equal to the high preset, the HP bit is set. If the
hardware accumulator becomes less than the high preset, the HP bit is reset by
the controller. Do not write to this bit. (Exception – you can set or reset this bit
during the initial configuration of the HSC instruction. See page 7–6 for more
information.)
Using High-Speed Counter Instructions
7–5
• Accumulator ≤ Low Preset Bit LP (bit 8) is a reserved bit for all Up
Counters.
For the Bidirectional Counters, if the hardware accumulator becomes less than
or equal to the low preset, the LP bit is set by the controller. If the hardware
accumulator becomes greater than the low preset, the LP bit is reset by the
controller. Do not write to this bit. (Exception – you can set or reset this bit
during the initial configuration of the HSC instruction. See page 7–6 for more
information.)
• Overflow Caused High-Speed Counter Interrupt Bit IV (bit 7) is set to
identify an overflow as the cause for the execution of the high-speed counter
interrupt routine. The IN, IH, and IL bits are reset by the controller when the IV
bit is set. Examine this bit at the start of the high-speed counter interrupt
routine (file 4) to determine why the interrupt occurred.
• Underflow caused High-Speed Counter Interrupt Bit IN (bit 6) is set to
identify an underflow as the cause for the execution of the high-speed counter
interrupt routine. The IV, IH, and IL bits are reset by the controller when the IN
bit is set. Examine this bit at the start of the high-speed counter interrupt
routine (file 4) to determine why the interrupt occurred.
• High Preset Reached Caused High-Speed Counter Interrupt Bit IH (bit 5)
is set to identify a high preset reached as the cause for the execution of the
high-speed counter interrupt routine. The IV, IN, and IL bits are reset by the
controller when the IH bit is set. Examine this bit at the start of the high-speed
counter interrupt routine (file 4) to determine why the interrupt occurred.
• Low Preset Reached Caused High-Speed Counter Interrupt Bit IL (bit 4)
is set to identify a low preset reached as the cause for the execution of the
high-speed counter interrupt routine. The IV, IN, and IH bits are reset by the
controller when the IL bit is set. Examine this bit at the start of the high-speed
counter interrupt routine (file 4) to determine why the interrupt occurred.
• High-Speed Counter Interrupt Pending Bit PE (bit 3) is set to indicate that
a high-speed counter interrupt is waiting for execution. This bit is cleared by
the controller when the high-speed counter interrupt routine begins executing.
This bit is reset if an RAC or RES instruction is executed. Do not write to this
bit.
• High-Speed Counter Interrupt Lost Bit LS (bit 2) is set if an high-speed
counter interrupt occurs while the PE bit is set. You can reset this bit with an
OTU instruction or by executing an RAC or RES instruction.
• High-Speed Counter Interrupt Enable Bit IE (bit 1) is set when the
high-speed counter interrupt is enabled to run when an high-speed counter
interrupt condition occurs. It is reset when the interrupt is disabled. This bit is
also set when the high-speed counter is first configured. Do not write to this
bit.
PrefaceInstruction Set Reference Manual
7–6
High-Speed Counter (HSC)
Use this instruction to configure the high-speed counter. Only one HSC instruction
can be used in a program. The high-speed counter is not operational until the first
true execution of the HSC instruction. When the HSC rung is false, the high-speed
counter is disabled from counting, but all other HSC features are operational.
The Counter address of the HSC instruction is fixed at C5:0. After the HSC is
configured, the image accumulator (C5:0.ACC) is updated with the current
hardware accumulator value every time the HSC instruction is evaluated as true or
false.
Entering Parameters
Enter the following parameters when programming this instruction:
• Type indicates the counter selected. Refer to page 7–7 for making your
high-speed counter selection. Each type is available with reset and hold
functionality.
• High Preset is the accumulated value that triggers a user-specified action such
as updating outputs or generating an high-speed counter interrupt.
• Accumulator is the number of accumulated counts.
The following terminology is used in the following table to indicate the status of
counting:
• Up↑ – increments by 1 when the input energizes (edge).
• Down↑ – decrements by 1 when the input energizes (edge).
• Reset↑ – resets the accumulator to zero when the input energizes (edge).
• Hold – disables the high-speed counter from counting while the input is
energized (level).
• Count – increments or decrements by 1 when the input energizes (edge).
• Direction – allows up counts when the input is de-energized and down counts
while the input is energized (level).
• A – input pulse in an incremental (quadrature) encoder (edge/level).
• B – input pulse in an incremental (quadrature) encoder (edge/level).
• Z – reset pulse in an incremental (quadrature) encoder (edge/level).
• ↑ – the signal is active on the rising edge only (off to on).
33
HSC
HIGH SPEED COUNTER
Type
Counter C5:0
High Preset 0
Accum 0
(CD)
(CU)
(DN)
Using High-Speed Counter Instructions
7–7
The table below lists the function key you press to choose the type of high-speed
counter you want.
High-Speed Counter Type
H -Speed Coun er Func onal
Input Terminal UsedHigh-Speed Counter Type
and Function Key High-Speed Counter Functionality I/0 I/1 I/2 I/3
Up Up Counter operation uses a single-ended
input. Up↑ Not Used Not Used Not Used
Up
(with reset and hold)
Up Counter operation uses a single input
with external reset and hold inputs. Up↑ Not Used Reset↑ Hold
Pulse and direction Bidirectional operation uses both pulse
and direction inputs. Count↑ Direction Not Used Not Used
Pulse and direction
(with external reset and hold)
Bidirectional operation uses both pulse
and direction inputs with external reset and
hold inputs.
Count↑ Direction Reset↑ Hold
Up and down Bidirectional operation uses both up and
down direction inputs. Up↑ Down↑ Not Used Not Used
Up and down
(with external reset and hold)
Bidirectional operation uses both up and
down pulse inputs with external reset and
hold inputs.
Up↑ Down↑ Reset↑ Hold
Encoder Bidirectional operation uses quadrature
encoder inputs.
A B Not Used Not Used
Encoder
(with external reset and hold)
Bidirectional operation uses both
quadrature encoder inputs with external
reset and hold inputs.
A B Z Hold
One difference between Up Counters and Bidirectional Counters is that for
Bidirectional Counters the accumulator and preset values are not changed by the
high-speed counter when the presets are reached. The RAC and HSL instructions
must be used for this function. The Up Counters clear the accumulator and re-load
the high preset values whenever the preset is reached.
PrefaceInstruction Set Reference Manual
7–8
Using the Up Counter and the Up Counter with Reset and Hold