CS310-CH20 - APPA - SequentialCircuits

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Sequential Circuits
Western Illinois University
Department of Computer Science
Prof. Paulo Martins
Created by W. Stallings
Modified by P. Martins
Computer Organization 
& Architecture 
6th Edition
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Sequential Circuits
� Combinational Circuits provide no 
memory 
� Exception: ROM memory
� The current output of a Sequential 
Circuit depends on the:
� Current Input
� The past history of inputs (or current state)
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Flip-Flops and Latches
� Simplest form of sequential circuit
� They are a bistable device:
� Exist in one of two states
� In the absence of input, remains in that 
state
� Function as a 1-bit memory
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The S-R Latch
S
R
Q
Q
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The characteristic table
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Timing Diagram
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Clocked S-R Latch
� It is often convenient to prevent the 
latch from changing state except at 
certain specified times;
� To achieve this goal, we modify the 
basic circuit slightly to get a clocked SR 
latch.
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Clocked S-R Latch
S
R
Q
Q
CLK
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Notes: Clocked SR
� Why is it called clocked latches?
� Why the clock is implemented?
� Events in a digital computer are 
synchronized to a clock pulse
� Changes occur when the clock pulse 
occurs
� Synchronous or asynchronous operation
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The Characteristic table
Important!
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Response to Series of Inputs
T 0 1 2 3 4 5 6 7 8 9
S 1 0 0 0 0 0 0 0 1 0
R 0 0 0 1 0 0 1 0 0 0 
Q 1 1 1 0 0 0 0 0 1 1 
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D Latch
D
Q
Q
CLK
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1. A problem with SR latch is that the 
condition R = S = 1 must be avoided
2. Allow just a single (inverted) input – by 
doing that we avoid R = S = 1
3. The output of the latch is equal to the most 
recent value applied to the input
4. It remembers and produces the last input
5. It is also called a delay latch because it 
delays a 0 or 1 for a single clock pulse
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J-K Latch
K
J
Q
Q
CLK
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Notes JK
1. All possible input values are possible
2. The first three combinations are the same 
as for the SR Latch
3. When both J and K are 1 the function 
performed is a toggle function: the output is 
reversed
4. J = 1 alone set the Latch
5. K = 0 alone reset the Latch
6. The student should verify that the 
implementation in this figure produces this 
characteristic function.
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The SR Latch
Q
Q
CLK
S
R
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The JK Latch
Q
Q
CLK
J
K
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The D Latch
Q
Q
CLK
D
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A pulse generator
a
d
b
c
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Timing at four points in the 
circuit
a
c
b
B and C
d
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The D Flip-Flop
a
d
b
c
Q
Q
CLK
D
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Parallel Registers
� A set of 1-bit memories that can be 
read or written simultaneously.
� Used to store data.
� Internal CPU registers are parallel 
registers
� S-R latches are used
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Registers
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Notes-Parallel Registers
� Set of 1-bit memories
� Can be read or written simultaneously
� USE: Store data
� Inputs might be output of MUX
� Several sources can be loaded to the 
Register
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5-Bit Shift Register
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Shift Register
� Accepts/ transfers information serially
� Fig. A31 – Built from clocked D FFs
� Purpose – ALU logical shift and rotation
� Interface to serial I/O
� Example: Interface Computer –
Peripheral (USB) – Universal Serial Bus
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Counters
� Counters are registers whose value is 
incremented until the capacity of the 
register.
� They can be asynchronous or 
synchronous
� Asynchronous are typically slow
� Synchronous: All outputs change at the 
same time (are used in CPUs).
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Ripple Counter (Asynchronous)
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Counter - Timing Diagram
Synchronous Counter
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