CS310-CH20 - APPA - SequentialCircuits

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Sequential Circuits
Western Illinois University
Department of Computer Science
 Prof. Paulo Martins
Created by W. Stallings Modified by P. Martins
Computer Organization 
& Architecture 
6th Edition
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Sequential Circuits
Combinational Circuits provide no memory 
Exception: ROM memory
The current output of a Sequential Circuit depends on the:
Current Input
The past history of inputs (or current state)
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Flip-Flops and Latches
Simplest form of sequential circuit
They are a bistable device:
Exist in one of two states
In the absence of input, remains in that state
Function as a 1-bit memory
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The S-R Latch
S
R
Q
Q
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The characteristic table
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Timing Diagram
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Clocked S-R Latch
It is often convenient to prevent the latch from changing state except at certain specified times;
To achieve this goal, we modify the basic circuit slightly to get a clocked SR latch.
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Clocked S-R Latch
S
R
Q
Q
CLK
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Notes: Clocked SR
Why is it called clocked latches?
Why the clock is implemented?
Events in a digital computer are synchronized to a clock pulse
Changes occur when the clock pulse occurs
Synchronous or asynchronous operation
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The Characteristic table
Important!
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Response to Series of Inputs
 T 0 1 2 3 4 5 6 7 8 9
 S 1 0 0 0 0 0 0 0 1 0
 R 0 0 0 1 0 0 1 0 0 0 
 Q 1 1 1 0 0 0 0 0 1 1 
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D Latch
D
Q
Q
CLK
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A problem with SR latch is that the condition R = S = 1 must be avoided
Allow just a single (inverted) input – by doing that we avoid R = S = 1
The output of the latch is equal to the most recent value applied to the input
It remembers and produces the last input
It is also called a delay latch because it delays a 0 or 1 for a single clock pulse
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J-K Latch
K
J
Q
Q
CLK
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Notes JK
All possible input values are possible
The first three combinations are the same as for the SR Latch
When both J and K are 1 the function performed is a toggle function: the output is reversed
J = 1 alone set the Latch
K = 0 alone reset the Latch
The student should verify that the implementation in this figure produces this characteristic function.
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The SR Latch
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The JK Latch
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The D Latch
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A pulse generator
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Timing at four points in the circuit
a
c
b
B and C
d
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The D Flip-Flop
Q
Q
CLK
D
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Parallel Registers
A set of 1-bit memories that can be read or written simultaneously.
Used to store data.
Internal CPU registers are parallel registers
S-R latches are used
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Registers
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Notes-Parallel Registers
Set of 1-bit memories
Can be read or written simultaneously
USE: Store data
Inputs might be output of MUX
Several sources can be loaded to the Register
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5-Bit Shift Register
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Shift Register
Accepts/ transfers information serially
Fig. A31 – Built from clocked D FFs
Purpose – ALU logical shift and rotation
Interface to serial I/O
Example: Interface Computer – Peripheral (USB) – Universal Serial Bus
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Counters
Counters are registers whose value is incremented until the capacity of the register.
They can be asynchronous or synchronous
Asynchronous are typically slow
Synchronous: All outputs change at the same time (are used in CPUs).
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Ripple Counter (Asynchronous)
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Counter - Timing Diagram
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1. Constructed from two NOR gates
2. Remembers previous input value
3. Outputs are complementary (A state with both outputs 0 is inconsistent)
4. Outputs are not uniquely determined by the current inputs
5. S = R = Q = 0
6. S = R = 0 and Q = 1
7. When S=R=0, the latch has two states that are stable and either 0 or 1 depending on 
Why it is used for memory: think that R = S = Q=0 initially. We set S = 1 and Q will be 1.
Now if S returns to 0, Q remains 1. It is a memory. Whatever the value of S, Q = 1.
8. We avoid R = S = 1 because the circuit becomes non-deterministic
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A problem with SR latch is that the condition R = S = 1 must be avoided
Allow just a single (inverted) input – by doing that we avoid R = S = 1
The output of the flip-flop is equal to the most recent value applied to the input
It remembers and produces the last input
It is also called a delay latch because it delays a 0 or 1 for a single clock pulse
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All possible input values are possible
When both J and K are 1 the function performed is a toggle function: the output is reversed
The student should verify that the implementation in this figure produces this characteristic function.
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Show that the outputs goes from 0000, 0001, 0010, 0011,….1111, 0000
Show the delay in propagation.
It is proportional to the length of the counter
Applications:
Digital Clock
 Frequency division