xbox360-service-manual

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[4] CPU, CLOCKS + EEPROM + STRAPPING
[21] MEMORY, A MIRRORED (BOTTOM)
[23] MEMORY, B MIRRORED (BOTTOM)
[25] MEMORY, C MIRRORED (BOTTOM)
[27] MEMORY, D MIRRORED (BOTTOM)
[28] ANA, CLOCKS + STRAPPING
[29] ANA, VIDEO + FAN + JTAG
K7 X803600-011 RETAIL XX/XX/XX
XENON
RETAIL
REV K7
SCHEMATIC REV PB NUMBER VER BOM RELEASE DATE
FAB K
[49] VREGS, INPUT + OUTPUT FILTERS
[51] VREGS, GPU OUTPUT PHASE 1,2,3
[52] VREGS, GPU CONTROLLER
[53] VREGS, GPU OUTPUT PHASE 1,2
[57] DEBUG BOARD, CPU + GPU BREAKOUT
[60] DEBUG BOARD, CPU TERM
[61] DEBUG BOARD, TITAN + YETI CONN
[63] XDK, LEDS
[64] LABELS AND MOUNTING
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
[PAGE_TITLE=COVER PAGE]
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
13.) SUFFIX _EN FOR ENABLE
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
5.) LANED SIGNALS ARE GROUPED ON SYMBOLS
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
RULES: (APPLIED WHEN POSSIBLE)
[32] POWER TRACE EMI CAPS
[19] DUAL ETHERNET PHY
[18] GPU, DECOUPLING
[17] GPU, CORE POWER + MEM POWER
[14] GPU, MEMORY CONTROLLER A + B
[13] GPU, VIDEO + PCIEX + EEPROM
[12] GPU, FSB
[11] CPU, DECOUPLING
[10] CPU, DECOUPLING
[9] CPU, DECOUPLING
[8] CPU, POWER
[7] CPU, CORE POWER
[6] CPU, FSB POWER + PLL POWER
[5] CPU, FSB
[3] RESET/ENABLE DIAGRAM
[2] CLOCK DIAGRAM
[1] COVER PAGE
PAGE
[35] SB, FLASH + USB + SPI
[36] SB, ETHERNET + AUDIO + SATA
[37] SB, STANDBY POWER + DECOUPLE
XENON
[38] SB, MAIN POWER + DECOUPLE
[39] SB OUT, ETHERNET
[40] SB OUT, AUDIO
[41] SB OUT, FLASH
[33] SB, PCIEX + SMM GPIO + JTAG
[34] SB, SMC
[42] SB OUT, FAN + INFRARED + BUTTONS
[43] CONN, AVIP
[44] CONN, RJ45 + USB COMBO
[15] GPU, MEMORY CONTROLLER C + D
3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING PLEASE REFER TO THE XENON DESIGN SPEC
[24] MEMORY, C (TOP)
[22] MEMORY, B (TOP)
[48] CONN, ARGON + POWER
[47] CONN, ODD AND HDD
[46] BACKUP CLOCK + V_5P0 DUAL
[45] CONN, GAME PORTS + MEMORY PORTS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
1.) MSB TO LSB IS TOP TO BOTTOM
15.) PWRGD FOR POWER GOOD
[30] ANA, POWER + DECOUPLING
[56] XDK, DEBUG CONN
CONTENTS
[16] GPU, PLL POWER + FSB POWER
[20] MEMORY, A (TOP)
[26] MEMORY, D (TOP)
12.) SUFFIX _P FOR P JUNCTION
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
[31] DEBUG MAPPING, WN DBG VS WN XDK
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
[55] VREGS, LINEAR REGULATORS
[58] DEBUG BOARD, CPU CONN
[62] DEBUG BOARD, GPU CONN + TERM
[59] DEBUG BOARD, CPU CONN + TERM
[54] VREGS, SWITCHED 1.8, 5.0V
[50] VREGS, CPU CONTROLLER
CONTENTSPAGE
XX/XX/XX
SCH, PBA, XENON
X803600-011
XENON_FABK
XENON_RETAIL 1/73 K7Wed Aug 24 09:41:55 2005
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
BOM RELEASE DATE
TITLE
DATE
ENGR
SIGNATURE
APVD
CHK BY
PB NUMBER
DRN BY
APVD
APVD
MICROSOFT XBOX
ENET
PHY
SB
VMEM VR
5P0 VR
3P3 VR
1P8 VR
<PAGE_TITLE=CLOCK DIAGRAM>
MPORT VR
I2S_MCLK(12.288MHZ)
ENET_CLK(25MHZ)
ANA_XTAL_IN(27MHZ)
I2S_BCLK(3.072MHZ)
HDD
SATA_CLK_DP/DN(100MHZ)
SATA_CLK_REF(25MHZ)
STBY_CLK(48MHZ)
AVIP
CONN POWER
PCIEX_CLK_DP/DN(100MHZ)
AUD_CLK(24.576MHZ)
MEM
CLAM C+D
AUDIO
DAC
BCKUP
ANA
DEBUG
CONN
GPU_CLK_DP/DN (100MHZ)
MC_CLK1_DP/DN(800MHZ)
GPUANABCKUP
FLSH
EJECT
SW
CPU
M
B
_C
LK
0_
D
P
/D
N
(8
00
M
H
Z)
M
B
_C
LK
1_
D
P
/D
N
(8
00
M
H
Z)
M
A
_C
LK
0_
D
P
/D
N
(8
00
M
H
Z)
M
A
_C
LK
1_
D
P
/D
N
(8
00
M
H
Z)
CONN
CONN
IR
PWR
CONN
DVD
SATA
DVD
RJ45/USB
MEM MEM
CONN SW
BIND
CLAM A+B
MEM
CONN
ARGON
EFUSE VR
CONN
GPU VR
CONN
TITAN JTAG
CPU VR
CNTL
CONN
GAME
CONN
GPU VR
CNTL
RISCWATCH
CPU
VR
CONN
CONN
FAN
CLOCK DIAGRAM
CONN
MD_CLK0_DP/DN(800MHZ)
MD_CLK1_DP/DN(800MHZ)
MC_CLK0_DP/DN(800MHZ)
CPU_CLK_DP/DN(100MHZ)
ANA
PIX_CLK_OUT_DP/DN(100MHZ)
K72/73XENON_RETAILWed Jul 27 21:53:30 2005
XENON_FABK PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
RJ45/USB
S
B
_R
S
T_
N
3P3
VR
5P0 VR
VMEM VRVREG_1P8_EN_N
V
R
E
G
_3
P
3_
E
N
S
M
C
_D
B
G
_E
N
V
R
E
G
_C
P
U
_P
W
R
G
D
DEBUG
CONN
CONN
DVD
HDD
CONN
SATA
DVD
E
X
T_
P
W
R
_O
N
_N
AUD_RST_N
VREG_GPU_EN_N
DAC
AUDIO
EXT_PWR_ON_N
GPU_RST_DONE
MEM_RST
MEM_SCAN_EN
GPU
M
E
M
_R
S
T
M
E
M
_S
C
A
N
_B
O
T_
E
N
M
E
M
_S
C
A
N
_T
O
P
_E
N
M
E
M
_S
C
A
N
_E
N
MEM_SCAN_TOP_EN
SB
MEM_SCAN_BOT_EN
RESET/ENABLE DIAGRAM
GPU_RST_N
CLAM A+B
CLAM C+D
MEM
SMC_RST_N
TITAN JTAG
CONN
ARGON
CONN
VREG_EFUSE_EN
ANA_CLK_OE
ANA_RST_N
AVIP
CPU_CHECKSTOP_N
ANA
AUD_CLAMP
PWR
PSU_V12P0_EN
CPU
CPU_PWRGD
EFUSE VR
MEM
RISCWATCH
CPU_RST_N
CPU_PWRGD
VREG_CPU_EN
CNTL
CPU VR
GPU VR
CONN
FAN
MEM
CONN
BIND
CONN
GAME
IR SW
EJECT
SWCONN
MEM
CONN
CPU
CONN
POWER
ENET
VR
GPU VR
CONN
CNTL
CONN
CONN
ENET_RST_NPHY
VREG_5P0_EN_N
VREG_GPU_PWRGD
[PAGE_TITLE=RESET/ENABLE DIAGRAM] K73/73XENON_RETAILWed Jul 27 21:53:44 2005XENON_FABK
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
CPU, CLOCKS + EEPROM + STRAPPING
N: STUFF C?,C? WITH .01UF CAPS FOR SHIVA
N: STUFF C?,C? WITH ZERO OHM R'S FOR WN
LAYOUT: MUST BE ACCESSIBLE
[PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING] K74/73XENON_RETAIL
4
49
49
4
56
4
49
4
34
49
34
55
4
4
29
4
4
4
46
46
4
29
4
49
49
Wed Aug 24 09:27:00 2005
2 1R7F7
2
1
C7R113
2
1 C7R112
1
FT7T7
1
FT7R5
1
FT7R1
1
FT7R2
1
FT7R6
1
FT7R4
2
1
TP6D1
2
1
R7U3
2
1 C6R46 2 1R6R10
1
FT7T5
1
FT7T3
1
FT7T41
FT7T1
1
FT7T2
1
FT2P12
1
FT2P11
2
1
R7F4
2
1
R7F3
2
1
R7R2
2
1
R7R1
2
1
R6R9
21 R7R11
21 R7R10
21 R7R16
21 R7R4
2
1
R6E1
2
1
R6D1
1
DB7R1
2
1
TP7R22
1
TP7R4
2
1
TP7R3
2
1
TP7R1
65
43
21
J7F1
2
1
R7D1
R7F2
R6E2
R7E7
2 1R7F1
2 1R7E8
2
1 C6F1
2 1R6R5
2 1R6R4
2
1
R7R17
2
1
R7R18
2
1
R7R19
2
1
R7R3
2
1
R7R5
2
1
R7R20
2
1
R7R23
2
1
R7R22
2
1
R7R13
2
1
R7R12
2
1
R7R21
3
8
2
5
6
7
4
1
U7E1
21
TP6R2
21
TP6R1
2
1
R7R6
2
1
R7R15
2
1
R7R7
2
1
R7R8
21 R7R24
2
1
R7R14
2
1
R6D2
2
1
R7R9
2
1
R6R8
2
1
R6R6
2
1
R6R7
C5
A5
B4
A4
B5
C4
AJ4
AK5
AH13
AK12
AG16
AK20
AK21
AH4
AH1
AK3
A3
B3
B2
A2
AJ1
AK1
AK14
AK15
AJ16
AK16
AF16
AK11
AK10
AK9
AJ10
AH10
AH16
AJ2
AK25
AK24
AH22
AJ22
AG18
AK23
AK22
AF18
C6
AK17AJ25
AH25
AF24
AG24
U7D1
360PF
10%
50V
NPO
360PF
10%
603
50V
NPO
603
CPU_PWRGD_V1P1_N
FSB_CLK_DP
X02046-002
IC1 OF 10
CPU_SPI_SI
1%6.19K
XENON_FABK
V_GPUCORE
V_MEM
V_GPUCORE
V_GPUCORE
V_MEM
V_MEM
V_MEM
V_GPUCORE
V_GPUCORE
V_MEM
402
10K
10K
5%
EMPTY
402
10K
CH
5%
10K
402
SMT
1206
EMPTY
5.11K
CPU_VREG_APS4
CPU_VREG_APS5
10%
6.3V
X5R
402
CPU_SPI_SI_R
EMPTY
5%
10K
402
CPU_SPI_SI
CH
402
5%
100
CPU_SYS_CONFIG1
CPU_PULSE_LIMIT_BYPASS
CPU_TRIGGER_IN
CPU_RST_V1P1_N
CPU_SPI_EN
CPU_SPI_SO_R
CPU_VREG_APS2
CPU_SPI_SO
CPU_FSB_CLK_SEL
CPU_PLL_BYPASS
CPU_RST_N
FSB_CLK_DN
CPU_ANL_1
CPU_FSB_IMPED_CAL_DP
CPU_FSB_IMPED_CAL_DN
CPU_SPI_EN_R
CPU_SPI_CLK_R
CPU_VREG_APS3
CPU_VDDS1_DN
CPU_VDDS1_DP
CPU_PWRGD
CPU_SPARE1
CPU_PSRO0_OUT
CPU_VDDS0_DN
VREG_EFUSE_EN
CPU_TEST_EN
CPU_SPI_SO
CPU_ANL_1_R
CPU_SPI_EN
CPU_TEMP_P
CPU_FSB_HF_CLKOUT_DN
CPU_FSB_HF_CLKOUT_DP
CPU_RES0_DP
CPU_VDDS0_DP
CPU_RES0_DN
CPU_SPI_WP_N
CPU_CORE_IF_BGR_PLL
CPU_SPI_CLK
CPU_ANL_2
CPU_SPARE0
CPU_SPI_WP_N
CH
402
5%
EMPTY
10K
402
5%
5%10K
402
402
5%
CH
CH
1.07K
1%
402
402
CH
10K
5%
402
10K
5%
5%
CH402
1K
0
1
2
3
4
EMPTY
5%
402
10K
SMT
CH
5%
10K
402
CH
402
10UF
6.3V
10%
EMPTY402
1%
0
EMPTY
402
5%
EMPTY
5%
0
10K
5%
CH
402
CH402
CH402
3.92K 1%
6.19K
402 CH
1%
402
1%
CH
3.92K
10K
402
CH
5%
402
CH
1%
931
TP
SMT
SMT
SMT
SMT
402
CH
5%
10K
402
1K 5%
CH
CH
5%
402
1K
CH
5%
402
1K
5%
402
10K
EMPTY
CH
5%
402
10K
.1UF
CH
5%
402
1K
CH
1K 5%
402
402
CH
5%
10K
5%
402
EMPTY
402
10K
5%
402
EMPTY
5%
402
10K
EMPTY
402
5%
10K
EMPTY
402
CH
10K
5%
402
5%
CH
10K
402
CH
10K
402
5%
402
10K
CH
5%
432104
3
2
1
0
IC
X800552-001
SMT
EMPTY
5%
10K
10K
CPU_POST_IN<0..4>
CPU_SYS_CONFIG0
CH
EMPTY
5%
10K
CH
5%
10K
CPU_CLK_DN
CPU_CLK_DP
CPU_SPI_SI
CPU_TEMP_N
CPU_SPI_CLK
CPU_VREG_APS0
CPU_VREG_APS1
EMPTY
CPU_EXT_CLK_EN
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
OUT
OUT
OUT
OUT
OUT
OUT
FTP
FTP
FTP
FTP
FTP
FTP
PROBE
OUT
FTP
FTP
FTP
FTP
FTP
FTP
FTP
OUT
OUT
IN
IN
PROBE
PROBE
PROBE
PROBE
IN
OUT
OUT
2X3HDR
IN
IN
IN
OUT
AT25020A
GND
SDO
VCC
WP_N*
CS_N*
HOLD_N*
SDI
SCK
CPU VERSION 20
CORE_CLK_DP
CORE_CLK_DN
HARD_RESET_B
POWER_GOOD
FSB_CLK_DP
FSB_CLK_DN
FSB_CLK_SEL
PULSE_LIMIT_BYPASS
TRIGGER_IN
PSRO0_OUT
POST_IN1
EXT_CLK_EN
VDDS0_DP
FSB_IMPED_CAL_DN
RESISTOR0_DP
SYS_CONFIG0
SYS_CONFIG1
PLL_BYPASS
CORE_IF_BGR_PLL
EFU_POWERON
VID1
VID2
VID3
VID4
VID5
VID0
SPI_EN
SPI_CLK
TE
TEMP_P
TEMP_N
SPI_SI
POST_IN0
POST_IN2
POST_IN4
POST_IN3
SPI_SO
ANL_1
ANL_2
SPARE1
SPARE0
FSB_HF_CLKOUT_DP
FSB_HF_CLKOUT_DN
FSB_IMPED_CAL_DP
RESISTOR0_DN
VDDS1_DN
VDDS1_DP
VDDS0_DN
PROBE
PROBE
OUT
OUT
OUT
OUT
OUTIN
OUT
IN
IN
IN
CPU, FSB
[PAGE_TITLE=CPU, FSB] K75/73XENON_RETAIL
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12 12
12
12
12
12
12
12 12
12 12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
Wed Aug 24 09:27:01 2005
2
1 C6R6
2
1 C6T32
2
1 C6T33
2
1 C6T27
2
1 C6R14
2
1 C6R25
2
1 C6R37
2
1 C6T19
2
1 C6T7
L28
L27
K29
K30
J30
J29
J28
J27
H29
H30
G28
G27
F29
F30
E30
E29
E28
E27
G30
G29
AD29
AD30
AC29
AC30
AB30
AB29
AB28
AB27
AA29
AA30
Y28
Y27
W29
W30
V30
V29
V28
V27
Y30
Y29
U30
U29
U27
U28
T30
T29
R30
R29
R27
R28
N30
N29
N27
N28
M30
M29
L30
L29
P30
P29
AK27
AK28
AK30
AK29
AJ29
AJ30
AH27
AH28
AH30
AH29
AF27
AF28
AF30
AF29
AE29
AE30
AD28
AD27
AG29
AG30
U7D1
X02046-002
IC2 OF 10
XENON_FABK
FSB_CP_GP0_DATA0_DP
FSB_CP_GP0_CLK_DN
FSB_CP_GP1_DATA0_DP
FSB_CP_GP1_FLAG_DN
FSB_CP_GP1_FLAG_DP
FSB_GP_CP0_DATA7_DN
FSB_GP_CP1_FLAG_DN
FSB_GP_CP1_DATA5_DP
FSB_GP_CP1_DATA1_DP
FSB_GP_CP1_DATA0_DN
FSB_GP_CP1_DATA0_DP
FSB_GP_CP1_DATA3_DN
FSB_GP_CP1_DATA4_DN
FSB_GP_CP1_DATA7_DP
FSB_GP_CP1_CLK_DP
FSB_GP_CP0_DATA6_DP
FSB_CP_GP1_DATA6_DP
FSB_GP_CP1_DATA6_DN
FSB_GP_CP1_CLK_DN
FSB_CP_GP0_DATA3_DN
FSB_CP_GP0_DATA0_DN
FSB_GP_CP0_DATA2_DP
FSB_GP_CP1_DATA1_DN
FSB_GP_CP1_DATA3_DP
FSB_CP_GP0_FLAG_DP
FSB_CP_GP0_FLAG_DN
FSB_CP_GP0_DATA4_DP
FSB_CP_GP0_DATA4_DN
FSB_CP_GP0_DATA5_DP
FSB_CP_GP0_DATA5_DN
FSB_CP_GP0_DATA6_DP
FSB_CP_GP0_DATA6_DN
FSB_CP_GP0_DATA7_DP
FSB_CP_GP0_DATA7_DN
FSB_CP_GP1_CLK_DP
FSB_CP_GP1_CLK_DN
FSB_CP_GP1_DATA0_DN
FSB_CP_GP1_DATA1_DP
FSB_CP_GP1_DATA1_DN
FSB_CP_GP1_DATA3_DN
FSB_CP_GP1_DATA5_DP
FSB_GP_CP0_FLAG_DN
FSB_GP_CP0_DATA7_DP
FSB_CP_GP0_DATA2_DP
FSB_GP_CP0_DATA4_DP
FSB_GP_CP0_DATA5_DP
FSB_CP_GP1_DATA7_DN
FSB_CP_GP1_DATA7_DP
FSB_CP_GP1_DATA6_DN
FSB_CP_GP1_DATA5_DN
FSB_CP_GP1_DATA4_DN
FSB_CP_GP1_DATA4_DP
FSB_CP_GP1_DATA2_DN
FSB_GP_CP1_DATA2_DP FSB_CP_GP1_DATA2_DP
FSB_GP_CP1_FLAG_DP
FSB_GP_CP0_DATA6_DN
FSB_GP_CP0_DATA5_DN
FSB_GP_CP0_DATA3_DN
FSB_CP_GP0_DATA3_DP
FSB_GP_CP0_DATA2_DN FSB_CP_GP0_DATA2_DN
FSB_GP_CP0_DATA1_DN FSB_CP_GP0_DATA1_DN
FSB_CP_GP0_DATA1_DP
FSB_GP_CP0_DATA0_DP
FSB_GP_CP0_FLAG_DP
FSB_GP_CP0_CLK_DP
FSB_GP_CP0_DATA1_DP
FSB_GP_CP0_DATA4_DN
FSB_GP_CP1_DATA2_DN
FSB_GP_CP1_DATA4_DP
FSB_GP_CP1_DATA6_DP
FSB_GP_CP1_DATA7_DN
FSB_GP_CP0_CLK_DN
FSB_GP_CP0_DATA0_DN
FSB_GP_CP0_DATA3_DP
FSB_CP_GP0_CLK_DP
FSB_GP_CP1_DATA5_DN
FSB_CP_GP1_DATA3_DP
402
X5R
6.3V
10%
.1UF
402
.1UF
10%
6.3V
X5R
402
X5R
6.3V
10%
.1UF
402
.1UF
10%
6.3V
X5R
402
X5R
6.3V
10%
.1UF
V_GPUCORE
X5R
.1UF
10%
6.3V
402
.1UF
X5R
6.3V
10%
402
6.3V
10%
.1UF
402
X5R
.1UF
X5R
6.3V
10%
402
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAMEDRAWING
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
CPU VERSION 20
GP_CP0_DATA5_DP
GP_CP0_DATA4_DN
GP_CP0_DATA4_DP
CP_GP0_DATA2_DP
CP_GP0_DATA1_DP
GP_CP0_DATA7_DP
GP_CP0_DATA7_DN
GP_CP1_CLK_DP
GP_CP1_CLK_DN
GP_CP1_FLAG_DP
GP_CP1_FLAG_DN
GP_CP1_DATA0_DP
GP_CP0_DATA0_DN
GP_CP0_DATA0_DP
GP_CP0_FLAG_DN
GP_CP0_FLAG_DP
GP_CP0_CLK_DN
GP_CP0_CLK_DP
GP_CP0_DATA5_DN
GP_CP0_DATA6_DP
GP_CP0_DATA6_DN
CP_GP1_DATA7_DN
CP_GP1_DATA7_DP
CP_GP1_DATA6_DN
CP_GP1_DATA6_DP
CP_GP1_DATA5_DN
CP_GP1_DATA5_DP
CP_GP1_DATA4_DN
CP_GP1_DATA4_DP
CP_GP1_DATA3_DN
CP_GP1_DATA3_DP
CP_GP1_DATA2_DN
CP_GP1_DATA2_DP
CP_GP1_DATA1_DN
CP_GP1_DATA1_DP
CP_GP1_DATA0_DN
CP_GP1_DATA0_DP
CP_GP1_FLAG_DN
CP_GP1_FLAG_DP
CP_GP1_CLK_DN
CP_GP1_CLK_DP
CP_GP0_DATA7_DN
CP_GP0_DATA7_DP
CP_GP0_DATA6_DN
CP_GP0_DATA6_DP
CP_GP0_DATA5_DN
CP_GP0_DATA5_DP
CP_GP0_DATA4_DN
CP_GP0_DATA4_DP
CP_GP0_FLAG_DN
CP_GP0_FLAG_DP
CP_GP0_CLK_DN
CP_GP0_CLK_DP
GP_CP1_DATA7_DN
GP_CP1_DATA7_DP
GP_CP1_DATA6_DN
GP_CP1_DATA6_DP
GP_CP1_DATA5_DN
GP_CP1_DATA5_DP
GP_CP1_DATA4_DN
GP_CP1_DATA4_DP
GP_CP1_DATA3_DN
GP_CP1_DATA3_DP
GP_CP1_DATA2_DN
GP_CP1_DATA2_DP
GP_CP1_DATA1_DN
GP_CP1_DATA1_DP
GP_CP1_DATA0_DN
GP_CP0_DATA3_DN
GP_CP0_DATA3_DP
GP_CP0_DATA2_DN
GP_CP0_DATA2_DP
GP_CP0_DATA1_DN
GP_CP0_DATA1_DP
CP_GP0_DATA0_DP
CP_GP0_DATA0_DN
CP_GP0_DATA1_DN
CP_GP0_DATA2_DN
CP_GP0_DATA3_DP
CP_GP0_DATA3_DN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
CPU, FSB POWER + PLL POWER
[PAGE_TITLE=CPU, FSB POWER + PLL POWER] K76/73XENON_RETAILWed Aug 24 09:27:01 2005
2
1
C7R116
2
1
C7R115
2
1
C7R114
2 1R7T2
2
1 C7D1
21
ST7D1
21
FB7D1
2
1
C6R3
21
ST6R2
21
FB6R2
2
1 C6R2
21
ST6R1
21
FB6R1
2
1
C6D1
21
ST6D1
21
FB6D1
21
ST7R1
2
1 C7R1
21
FB7R1
2
1 C7D2
2
1
C6R5
2
1 C6R4
2
1
C6D4 B6
A6
AK13
AK6
AK26
AJ27
AH26
AG27
AF26
Y26
W27
V26
U26
T27
R26
P27
AE27
N26
M27
L26
K27
J26
H27
G26
F27
E26
D29
AD26
D27
D25
D21
D17
D13
D10
C26
C23
C20
C17
AC27
C14
C11
C8
B27
B24
B21
B18
B15
B12
B9
AB26
AA27
AJ13
AF20
AG20
AF22
AG22
AK19
AK18
AJ19
AH19
U7D1
2
1 C7R7
X02046-002
IC4 of 10
XENON_FABK
6.3V
CPU_VDDE
V_CPU_FSB_HF_VDDA_PLL
V_CPU_CORE_HF_VDDA_PLL
V_CPU_CORE_HF_GNDA_PLL
V_CPU_CORE_IF_VDDA_PLL
V_CPU_CORE_IF_GNDA_PLL
V_CPU_FSB_HF_GNDA_PLL
V_CPU_FSB_IF_VDDA_PLL
V_CPU_FSB_IF_GNDA_PLL
V_CPU_VDDA_RNG
V_CPU_GNDA_RNG
2.2UF
603
X5R
6.3V
10%
10%
6.3V
603
X5R
2.2UF
6.3V
603
X5R
10%
2.2UF
X5R
6.3V
10%
2.2UF
603
2.2UF
603
X5R
6.3V
10%
.1UF
X5R
402
6.3V
10%
6.3V
.1UF
402
X5R
10% 10%
402
X5R
.1UF
V_1P8
10K
CH
5%
402
1UF
603
10%
50V
EMPTY
V_EFUSE
1K FB
603
0.7DCR
0.2A
.1UF
402
10%
X5R
6.3V
FB1K
603
0.7DCR
0.2A
402
.1UF
10%
6.3V
X5R
603
FB1K
0.7DCR
0.2A
10%
.1UF
6.3V
X5R
402
603
FB1K
0.7DCR
0.2A
402
X5R
6.3V
.1UF
10%
0.7DCR
0.2A
FB
603
1K
V_CPUPLL V_GPUCORE
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
CPU VERSION 20
VDD_IO
VDDE
VDDE_SEC
CORE_HF_VDDA_PLL
CORE_HF_GNDA_PLL
CORE_IF_VDDA_PLL
CORE_IF_GNDA_PLL
FSB_HF_VDDA_PLL
FSB_HF_GNDA_PLL
FSB_IF_VDDA_PLL
FSB_IF_GNDA_PLL
VDDA_RNG
GNDA_RNG
VDD_FSB0
VDD_FSB1
VDD_FSB2
VDD_FSB3
VDD_FSB4
VDD_FSB5
VDD_FSB6
VDD_FSB7
VDD_FSB8
VDD_FSB9
VDD_FSB10
VDD_FSB11
VDD_FSB12
VDD_FSB13
VDD_FSB14
VDD_FSB15
VDD_FSB16
VDD_FSB17
VDD_FSB18
VDD_FSB19
VDD_FSB20
VDD_FSB21
VDD_FSB22
VDD_FSB23
VDD_FSB24
VDD_FSB25
VDD_FSB26
VDD_FSB27
VDD_FSB28
VDD_FSB29
VDD_FSB30
VDD_FSB31
VDD_FSB32
VDD_FSB33
VDD_FSB34
VDD_FSB35
VDD_FSB36
VDD_FSB37
VDD_FSB38
VDD_FSB39
VDD_FSB40
VDD_FSB41
VDD_FSB42
VDD_FSB43
VDD_FSB44
VDD_FSB45
VDD_FSB46
SHORT
SHORT
SHORT
SHORT
SHORT
CPU, CORE POWER
[PAGE_TITLE=CPU, CORE POWER] K77/73XENON_RETAILWed Aug 24 09:27:01 2005
Y25
Y23
Y21
Y19
Y17
Y15
Y13
Y11
Y9
Y7
Y5
Y3
Y1
W24
W22
W20
W18
W16
W14
W12
W10
W8
W6
W4
W2
V25
V23
V21
V19
V17
V15
V13
V11
V9
V7
V5
V3
V1
U24
U22
U20
U18
U16
U14
U12
U10
U8
U6
U4
U2
T25
T23
T21
T19
T17
T15
T13
T11
T9
T7
T5
T3
T1
R24
R22
R20
R18
R16
R14
R12R10
R8
R6
R4
R2
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P5
P3
P1
N24
N22
N20
N18
N16
N14
U7D1
E4
E2
D9
D7
N12
N10
N8
N6
N4
N2
M25
M23
M21
M19
M17
M15
M13
M11
M9
M7
M5
M3
M1
L24
L22
L20
L18
L16
L14
L12
L10
L8
L6
L4
L2
K25
K23
K21
K19
K17
K15
K13
K11
K9
K7
K5
K3
K1
J24
J22
J20
J18
J16
J14
J12
J10
J8
J6
J4
J2
H25
H23
H21
H19
H17
H15
H13
H11
H9
H7
H5
H3
H1
G24
G22
G20
G18
G16
G14
G12
G10
G8
G6
G4
G2
F11
F9
F7
F5
F3
F1
E10
E8
E6
U7D1
D5
D3
D1
C2
B1
AJ14
AA20
AJ11
AJ8
AJ5
AH15
AH12
AH9
AH6
AH3
AG14
AG12
AA18
AG10
AG8
AG6
AG4
AG2
AF25
AF23
AF21
AF19
AF17
AA16
AF15
AF13
AF11
AF9
AF7
AF5
AF3
AF1
AE24
AE22
AA14
AE20
AE18
AE16
AE14
AE12
AE10
AE8
AE6
AE4
AE2
AA12
AD25
AD23
AD21
AD19
AD17
AD15
AD13
AD11
AD9
AD7
AA10
AD5
AD3
AD1
AC24
AC22
AC20
AC18
AC16
AC14
AC12
AA8
AC10
AC8
AC6
AC4
AC2
AB25
AB23
AB21
AB19
AB17
AA6
AB15
AB13
AB11
AB9
AB7
AB5
AB3
AB1
AA24
AA22
AA4
AA2
U7D1
X02046-002
IC
7 of 10
X02046-002
IC
6 of 10
X02046-002
IC
5 of 10
XENON_FABK
V_CPUCOREV_CPUCOREV_CPUCORE V_CPUCORE V_CPUCOREV_CPUCORE
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
CPU VERSION 20
VDD51
VDD50
VDD49
VDD10
VDD11
VDD12
VDD13
VDD41
VDD40
VDD42
VDD43
VDD45
VDD58
VDD56
VDD57
VDD59
VDD73
VDD72
VDD93
VDD94
VDD95
VDD88
VDD89
VDD90
VDD91
VDD92
VDD83
VDD84
VDD85
VDD86
VDD87
VDD82
VDD78
VDD79
VDD80
VDD81
VDD77
VDD74
VDD75
VDD76
VDD67
VDD68
VDD69
VDD70
VDD71
VDD62
VDD63
VDD64
VDD65
VDD66
VDD60
VDD61
VDD52
VDD53
VDD54
VDD55
VDD48
VDD2
VDD1
VDD0
VDD7
VDD9
VDD8
VDD6
VDD46
VDD47
VDD44
VDD35
VDD36
VDD37
VDD38
VDD39
VDD34
VDD30
VDD31
VDD32
VDD33
VDD29
VDD25
VDD26
VDD27
VDD28
VDD24
VDD19
VDD20
VDD21
VDD22
VDD23
VDD14
VDD15
VDD16
VDD17
VDD18
VDD4
VDD5
VDD3
CPU VERSION 20
VDD237
VDD197
VDD196
VDD193
VDD194
VDD195
VDD202
VDD201
VDD198
VDD207
VDD204
VDD203
VDD205
VDD206
VDD212
VDD208
VDD209
VDD210
VDD211
VDD213
VDD217
VDD214
VDD215
VDD216
VDD218
VDD222
VDD219
VDD220
VDD221
VDD223
VDD228
VDD227
VDD224
VDD225
VDD226
VDD233
VDD232
VDD229
VDD230
VDD231
VDD234
VDD235
VDD236
VDD192
VDD191
VDD190
VDD199
VDD200
VDD244
VDD243
VDD240
VDD241
VDD242
VDD249
VDD248
VDD245
VDD246
VDD247
VDD254
VDD251
VDD250
VDD252
VDD253
VDD259
VDD255
VDD256
VDD257
VDD258
VDD260
VDD264
VDD261
VDD262
VDD263
VDD265
VDD269
VDD266
VDD267
VDD268
VDD270
VDD275
VDD274
VDD271
VDD272
VDD273
VDD280
VDD279
VDD276
VDD277
VDD278
VDD281
VDD282
VDD283
VDD239
VDD238
CPU VERSION 20
VDD146
VDD145
VDD96
VDD97
VDD98
VDD99
VDD104
VDD105
VDD106
VDD143
VDD147
VDD148
VDD149
VDD150
VDD151
VDD168
VDD189
VDD188
VDD187
VDD184
VDD183
VDD182
VDD185
VDD186
VDD179
VDD178
VDD177
VDD180
VDD181
VDD176
VDD174
VDD173
VDD172
VDD175
VDD171
VDD169
VDD167
VDD170
VDD166
VDD164
VDD163
VDD162
VDD161
VDD165
VDD159
VDD158
VDD156
VDD157
VDD160
VDD153
VDD152
VDD154
VDD155
VDD144
VDD142
VDD141
VDD140
VDD137
VDD136
VDD135
VDD138
VDD139
VDD132
VDD131
VDD130
VDD133
VDD134
VDD129
VDD127
VDD126
VDD125
VDD128
VDD124
VDD122
VDD121
VDD120
VDD123
VDD119
VDD117
VDD116
VDD115
VDD114
VDD118
VDD112
VDD111
VDD109
VDD110
VDD113
VDD107
VDD108
VDD101
VDD100
VDD102
VDD103
CPU, POWER
[PAGE_TITLE=CPU, POWER] K78/73XENON_RETAILWed Aug 24 09:27:02 2005
Y24
Y22
Y20
Y18
Y16
Y14
Y12
Y10
Y8
Y6
Y4
Y2
W28
W26
W25
W23
W21
W19
W17
W15
W13
W11
W9
W7
W5
W3
W1
V24
V22
V20
V18
V16
V14
V12
V10
V8
V6
V4
V2
U25
U23
U21
U19
U17
U15
U13
U11
U9
U7
U5
U3
U1
T28
T26
T24
T22
T20
T18
T16
T14
T12
T10
T8
T6
T4
T2
R25
R23
R21
R19
R17
R15
R13
R11
R9
R7
R5
R3
R1
P28
P26
P24
P22
P20
P18
P16
P14
P12
P10
P8
P6
P4
P2
N25
N23
N21
N19
N17
N15
N13
N11
N9
N7
N5
N3
N1
M28
M26
M24
M22
M20
M18
M16
M14
M12
M10
U7D1
M8
M6
M4
M2
L25
L23
L21
L19
L17
L15
L13
L11
L9
L7
L5
L3
L1
K28
K26
K24
K22
K20
K18
K16
K14
K12
K10
K8
K6
K4
K2
J25
J23
J21
J19
J17
J15
J13
J11
J9
J7
J5
J3
J1
H28
H26
H24
H22
H20
H18
H16
H14
H12
H10
H8
H6
H4
H2
G25
G23
G21
G19
G17
G15
G13
G11
G9
G7
G5
G3
G1
F28
F26
F24
F22
F20
F18
F16
F14
F12
F10
F8
F6
F4
F2
E9
E7
E5
E3
E1
D30
D28
D26
D23
D19
D15
D11
D8
D6
D4
D2
C27
C24
C21
C18
C15
C12
C9
C3
C1
B29
B26
B23
B20
B17
B14
U7D1
AH21
AH20
AH18
AH17
AH14
AH11
AH8
AH5
AH2
AG28
AA19
AG26
AG25
AG23
AG21
AG19
AG17
AG15
AG13
AG11
AG9
AA17
AG7
AG5
AG3
AG1
AF14
AF12
AF10
AF8
AF6
AF4
AA15
AF2
AE28
AE26
AE25
AE23
AE21
AE19
AE17
AE15
AE13
AA13
AE11
AE9
AE7
AE5
AE3
AE1
AD24
AD22
AD20
AD18
AA11
AD16
AD14
AD12
AD10
AD8
AD6
AD4
AD2
AC28
AC26
AA9
AC25
AC23
AC21
AC19
AC17
AC15
AC13
AC11
AC9
AC7
AA7
AC5
AC3
AC1
AB24
AB22
AB20
AB18
AB16
AB14
AB12
AA5
AB10
AB8
AB6
AB4
AB2
AA28
AA26
AA25
B11
B8
AJ28
AJ26
AJ24
AJ23
AJ21
AA23
AJ20
AJ18
AJ17
AJ15
AJ12
AJ9
AJ6
AJ3
AH24
AH23
AA21
AA3
AA1
U7D1
X02046-002
IC
10 of 10
X02046-002
IC
9 of 10
X02046-002
IC
8 of 10
XENON_FABK PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
CPU VERSION 20
VSS117
VSS118
VSS175
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS131
VSS133
VSS134
VSS136
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS207
VSS206
VSS232
VSS231
VSS230
VSS227
VSS225
VSS226
VSS228
VSS229
VSS215
VSS214
VSS212
VSS211
VSS210
VSS213
VSS209
VSS205
VSS208
VSS204
VSS202
VSS201
VSS200
VSS199
VSS203
VSS197
VSS196
VSS194
VSS195
VSS198
VSS191
VSS190
VSS189
VSS192
VSS193
VSS186
VSS185
VSS184
VSS187
VSS188
VSS181
VSS180
VSS179
VSS182
VSS183
VSS178
VSS177
VSS176
VSS174
VSS173
VSS172
VSS169
VSS167
VSS168
VSS170
VSS171
VSS164
VSS163
VSS162
VSS165
VSS166
VSS159
VSS158
VSS157
VSS160
VSS161
VSS156
VSS154
VSS153
VSS152
VSS155
VSS151
VSS149
VSS148
VSS147
VSS150
VSS146
VSS144
VSS143
VSS142
VSS141
VSS145
VSS139
VSS138
VSS137
VSS140
VSS132
VSS135
VSS130
VSS122
VSS121
VSS120
VSS119
CPU VERSION 20
VSS286
VSS287
VSS288
VSS289
VSS291
VSS292
VSS293
VSS335
VSS334
VSS333
VSS331
VSS330
VSS329
VSS328
VSS322
VSS323
VSS348
VSS347
VSS346
VSS343
VSS341
VSS342
VSS344
VSS345
VSS338
VSS337
VSS336
VSS339
VSS340
VSS332
VSS327
VSS326
VSS325
VSS321
VSS324
VSS320
VSS318
VSS317
VSS316
VSS315
VSS319
VSS313
VSS312
VSS310
VSS311
VSS314
VSS307
VSS306
VSS305
VSS308
VSS309
VSS302
VSS301
VSS300
VSS303
VSS304
VSS297
VSS296
VSS295
VSS298
VSS299
VSS294
VSS257
VSS258
VSS290
VSS285
VSS283
VSS284
VSS280
VSS279
VSS278
VSS281
VSS282
VSS275
VSS274
VSS273
VSS276
VSS277
VSS272
VSS270
VSS269
VSS268
VSS271
VSS267
VSS265
VSS264
VSS263
VSS266
VSS262
VSS260
VSS259
VSS261
VSS255
VSS254
VSS252
VSS253
VSS256
VSS249
VSS248
VSS247
VSS250
VSS251
VSS244
VSS243
VSS242
VSS245
VSS246
VSS239
VSS238
VSS237
VSS240
VSS241
VSS236
VSS235
VSS233
VSS234
CPU VERSION 20
VSS58VSS0
VSS113
VSS114
VSS116
VSS115
VSS109
VSS108
VSS110
VSS111
VSS112
VSS103
VSS104
VSS105
VSS106
VSS107
VSS98
VSS99
VSS100
VSS101
VSS102
VSS97
VSS93
VSS94
VSS95
VSS96
VSS92
VSS88
VSS89
VSS90
VSS91
VSS87
VSS83
VSS84
VSS85
VSS82
VSS86
VSS78
VSS77
VSS79
VSS80
VSS81
VSS72
VSS73
VSS74
VSS75
VSS76
VSS67
VSS68
VSS69
VSS70
VSS71
VSS62
VSS64
VSS63
VSS65
VSS66
VSS59
VSS60
VSS61
VSS28
VSS27
VSS26
VSS22
VSS21
VSS20
VSS57
VSS56
VSS55
VSS52
VSS50
VSS51
VSS53
VSS54
VSS47
VSS46
VSS45
VSS48
VSS49
VSS42
VSS41
VSS40
VSS43
VSS44
VSS39
VSS37
VSS36
VSS35
VSS38
VSS34
VSS32
VSS31
VSS30
VSS33
VSS29
VSS25
VSS24
VSS19
VSS23
VSS16
VSS15
VSS14
VSS17
VSS18
VSS11
VSS10
VSS9
VSS12
VSS13
VSS6
VSS5
VSS4
VSS7
VSS8
VSS3
VSS2
VSS1
CPU, DECOUPLING
[PAGE_TITLE=CPU, DECOUPLING] K79/73XENON_RETAILWed Aug 24 09:27:03 2005
21
C7T45
21
C7T1
21
C7R16
21
C7R13
21
C7R11
21
C7R10
21
C7R12
21
C7T88
21
C7T76
21
C7T77
21
C7T78
21
C7T79
21
C7D20
21
C7T33
21
C7R28
21
C7T32
21
C7E3
21
C7R2
21
C7T87
21
C7E11
21
C7E10
21
C7E12
21
C7D16
21
C7T93
21
C7T101
21
C7T94
21
C7D21
21
C7E14
21
C7E8
21
C7R122
21
C7R121
21
C7T84
21
C7D17
21
C7D14
21
C7E5
21
C7D11
21
C7T83
21
C7R118
21
C7D13
21
C7T36
21
C7D19
21
C7E7
21
C7R119
21
C7D6
21
C7R92
21
C7T96
21
C7R117
21
C7R26
21
C7E4
21
C7D15
21
C7R29
21
C7R91
21
C7E16
21
C7D7
21
C7D18
21
C7R120
21
C7D3
21C7T95
21
C7R93
21
C7D5
21
C7D12
21
C7E6
21
C7T85
21
C7E1
21
C7R94
21
C7R6
21
C7T34
21
C7R5
21
C7D9
21
C7D4
21
C7D8
21
C7R27
21
C7T35
21
C7R4
21
C7D10
21
C7D22
21
C7T97
21
C7T86
21
C7E9
21
C7E15
21
C7E2
21
C7R90
21
C7R30
21
C7R3
XENON_FABK
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
.1UF
402
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
.1UF
402
X5R
10%
6.3V
.1UF
402
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
.1UF
402
X5R
10%
6.3V
.1UF
402
V_CPUCORE
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
V_CPUCORE
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
402
.1UF
X5R
10%
6.3V
.1UF
402805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
CPU SOCKET
CPU, DECOUPLING
N: EMPTY FOR
[PAGE_TITLE=CPU, DECOUPLING] K710/73XENON_RETAILWed Aug 24 09:27:03 2005
21
C7T8
21
C7T20
21
C7R48
21
C7T82
21
C7T81
21
C7T71
21
C7T72
21
C7T73
21
C7T74
21
C7T75
21
C7T70
21
C7T69
21
C7R46
21
C6R11
21
C7R45
21
C6R17
21
C7R44
21
C7R37
21
C7R38
21
C7R25
21
C7R24
21
C7R23
21
C7R77
21
C7R79
21
C7R63
21
C7R47
21
C7R53
21
C7R70
21
C7R84
21
C7R71
21
C7R54
21
C7R61
21
C6T26
21
C6R21
21
C7R64
21
C7T15
21
C7R76
21
C6R19
21
C6R16
21
C7R43
21
C6R27
21
C6R28
21
C6R29
21
C7R19
21
C7R34
21
C7R35
21
C6R20
21
C7R57
21
C7R69
21
C7R68
21
C6T5
21
C6R31
21
C7R22
21
C7R36
21
C7R78
21
C7R62
21
C7R72
21
C7R49
21
C7R55
21
C7T9
21
C6R32
21
C7R80
21
C6R30
21
C7R60
21
C6T23
21
C7R99
21
C7R74
21
C7R100
21
C7R58
21
C7R59
21
C6R23
21
C6R22
21
C7R50
21
C6T6
21
C6T25
21
C7R89
21
C7T37
21
C7R88
21
C6R36
21
C7R81
21
C6T4
21
C7T27
21
C7R102
21
C6R43
21
C6T1
21
C6R18
21
C6R39
21
C6R34
21
C6R38
21
C7T10
21
C6R35
21
C7T2
21
C7R110
21
C7R111
21
C7R66
21
C6R40
21
C6R45
21
C7T5
21
C7T3
21
C7R67
21
C6R42
21
C7R51
21
C7R52
21
C7T22
21
C6T2
21
C6R44
21
C7T19
21
C6T10
21
C6R33
21
C7T21
XENON_FABK
6.3V
.1UF 10%
X5R
402
6.3V
X5R
.1UF 10%
X5R
402
.1UF 10%
6.3V
10%.1UF
6.3V
X5R
402
X5R
402
.1UF 10%
6.3V
6.3V
X5R
402
.1UF
6.3V
402
10%
X5R
.1UF
6.3V
X5R
402
.1UF 10%
10%.1UF
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
.1UF
402
X5R
10%
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
10%
6.3V
X5R
402
.1UF
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
X5R
402
6.3V
.1UF 10%
402
X5R
6.3V
.1UF 10%
402
6.3V
.1UF 10%
X5R
.1UF
402
X5R
10%
X5R
6.3V
.1UF 10%
X5R
6.3V
10%.1UF
402
.1UF 10%
X5R
402
6.3V
402
10%
6.3V
X5R
402
.1UF
402
6.3V
X5R
10%
6.3V
X5R
402
.1UF
402
.1UF 10%
X5R
6.3V
402
X5R
10%
6.3V
X5R
.1UF 10%
402
10%
X5R
402
.1UF
.1UF
6.3V
X5R
402
10%
6.3V
X5R
.1UF 10%
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF
6.3V
X5R
10%
6.3V
X5R
402
.1UF 10%
402
6.3V
.1UF
X5R
10%
10%
X5R
6.3V
402
.1UF
.1UF
6.3V
402
X5R
10%
6.3V
X5R
.1UF 10%
402
X5R
402
6.3V
.1UF 10%
402
10%
X5R
6.3V
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6.3V
X5R
.1UF 10%
402
6.3V
X5R
.1UF 10%
402
X5R
402
10%
6.3V
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6.3V
402
6.3V
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402
10%.1UF
6.3V
X5R
.1UF 10%
402
10%
402
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6.3V
6.3V
X5R
402
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6.3V
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402
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402
6.3V
10%
6.3V
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402
10%.1UF
6.3V
X5R
402
.1UF 10%
402
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6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
X5R
402
.1UF 10%
6.3V
.1UF
6.3V
10%
X5R
402
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
402
.1UF
402
10%
X5R
6.3V
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF
6.3V
X5R
402
.1UF
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
V_CPUCORE
6.3V
X5R
402
.1UF 10%
X5R
402
.1UF
6.3V
10%
6.3V
X5R
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
X5R
402
.1UF 10%
6.3V
X5R
.1UF
6.3V
402
10%
.1UF 10%
6.3V
402
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.1UF 10%
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
.1UF 10%
6.3V
X5R
.1UF 10%
402
402
10%
6.3V
X5R
.1UF
6.3V
X5R
10%
402
.1UF
.1UF 10%
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
10%.1UF
X5R
402
.1UF 10%
6.3V
.1UF
6.3V
X5R
402
10%
402
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.1UF 10%
.1UF 10%
6.3V
X5R
402
.1UF
6.3V
10%
402
6.3V
10%
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402
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6.3V
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.1UF 10%
402
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
10%.1UF
6.3V
X5R
402
6.3V
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402
.1UF 10%
X5R
402
6.3V
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6.3V
.1UF 10%
X5R
402
10%
402
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6.3V
.1UF
6.3V
6.3V
10%
402
.1UF
402
402
.1UF
402
10%10%
X5R
X5R
6.3V
402
10%
10% 10%
6.3V
.1UF
6.3V
.1UF 10%
6.3V
X5R
6.3V
402
.1UF 10%
X5R
10%
.1UF
6.3V
402
10%
X5R
.1UF 10%
402
6.3V
X5R
402
X5R
6.3V
.1UF
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
CPU, DECOUPLING
[PAGE_TITLE=CPU, DECOUPLING] K711/73XENON_RETAILWed Aug 24 09:27:05 2005
21
C7T80
21
C7R9
21
C7R14
21
C7R15
21
C7R8
21
C7T68
21
C7T67
21
C7T66
21
C7T65
21
C7T64
21
C7T63
21
C7T62
21
C6T30
21
C6T29
21
C6T28
21
C6R13
21
C7R107
21
C6R12
21
C6T21
21
C7R21
21
C6T3
21
C6T9
21
C7R39
21
C7R40
21
C7R41
21
C6R26
21
C7R56
21
C7R82
21
C7R42
21
C7R20
21
C7R18
21
C7T12
21
C7R31
21
C7R17
21
C6T11
21
C7R32
21
C7R33
21
C6R41
21
C6R15
21
C6R10
21
C7T31
21
C7T28
21
C6T14
21
C6T12
21
C7T41
21
C7T17
21
C7T13
21
C6T22
21
C7T49
21
C6T8
21
C7R98
21
C7T56
21
C6T20
21
C7R106
21
C7T50
21
C7R86
21
C7T59
21
C7R73
21
C6R8
21
C7T60
21
C7T61
21
C6R7
21
C6R9
21
C7T52
21
C7T53
21
C7R101
21
C7R85
21
C7R75
21
C7T40
21
C7T11
21
C7R65
21
C7T38
21
C6R24
21
C7T58
21
C7T29
21
C7T30
21
C6T24
21
C7T54
21
C7T14
21
C6T13
21
C7T16
21
C6T18
21
C7T48
21
C7T26
21
C7T23
21
C6T17
21
C7T4
21
C7R105
21
C7R109
21
C7T39
21
C7T18
21
C7T55
21
C7R108
21
C7R96
21
C7R104
21
C7T57
21
C7R97
21
C7T46
21
C7T25
21
C7T24
21
C7R83
21
C7T42
21
C7T44
21
C7T43
21
C7R103
21
C7R95
21
C7T47
21
C7T51
21
C6T16
21
C6T15
XENON_FABK
6.3V
X5R
402
.1UF 10%
6.3V
402
.1UF 10%
X5R
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
X5R
402
10%.1UF
6.3V
.1UF 10%
6.3V
X5R
402
.1UF
402
X5R
10%
6.3V
.1UF 10%
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF 10%
X5R
402
6.3V
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
X5R
.1UF 10%
6.3V
402
6.3V
X5R
402
.1UF 10%
X5R
.1UF 10%
6.3V
402
6.3VX5R
402
10%.1UF.1UF 10%
6.3V
X5R
402
.1UF
6.3V
X5R
402
10%
6.3V
X5R
402
.1UF 10%
X5R
6.3V
10%.1UF
402
.1UF
6.3V
X5R
402
10%
10%.1UF
402
X5R
6.3V
X5R
10%.1UF
6.3V
402
10%.1UF
402
6.3V
X5R
6.3V
X5R
402
.1UF 10%
10%.1UF
X5R
402
6.3V
.1UF 10%
6.3V
X5R
402
402
6.3V
X5R
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
10%.1UF
6.3V
X5R
402
X5R
402
.1UF 10%
6.3V
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
.1UF 10%
402
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
X5R
402
.1UF 10%
6.3V
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
10%.1UF
6.3V
X5R
402
402
.1UF 10%
6.3V
X5R
.1UF 10%
6.3V
X5R
402
X5R
402
10%.1UF
6.3V
402
X5R
10%
6.3V
.1UF .1UF 10%
X5R
402
6.3V
X5R
.1UF 10%
6.3V
402
.1UF
6.3V
X5R
402
10%
402
6.3V
X5R
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
.1UF 10%
402
6.3V
X5R
402
.1UF 10%
6.3V
.1UF 10%
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
402
10%
X5R
.1UF
6.3V
X5R
402
10%
6.3V
.1UF
6.3V
10%.1UF
X5R
402
10%
6.3V
X5R
402
.1UF
6.3V
X5R
10%
402
.1UF
.1UF 10%
6.3V
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
10%
6.3V
X5R
402
.1UF
6.3V
X5R
402
10%.1UF
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
10%
402
X5R
.1UF
6.3V
X5R
402
.1UF 10%
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF
6.3V
X5R
402
10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
402
X5R
.1UF 10%
402
X5R
10%.1UF
6.3V
10%
X5R
402
.1UF
6.3V
.1UF 10%
6.3V
X5R
402
6.3V
.1UF 10%
X5R
402
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
.1UF
X5R
402
6.3V
10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
10%
402
.1UF
402
X5R
.1UF 10%
6.3V
6.3V
X5R
402
.1UF 10%
10%
X5R
.1UF
402
6.3V
6.3V
X5R
402
.1UF 10%
V_CPUCORE
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
6.3V
X5R
402
.1UF 10%
X5R
.1UF 10%
6.3V
402
X5R
.1UF 10%
6.3V
402
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
GPU, FSB
[PAGE_TITLE=GPU, FSB]
FSB DECOUPLING
K712/73XENON_RETAIL
5
5
5
5
5
13
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
13
13 21 23 25
27
13
20 22 24
26
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
20 21 22
23 24 25
26 27
Wed Aug 24 09:27:06 2005
2
1
R4F8
2
1
R4U6
2
1
R2D11
2
1
R4F7
2
1
R2T1
2
1
R2T2
2
1
R2R5
21
C2D5
5
4
1
2
3
U2R1
21 R2R6
21
C2R12
5
4
1
2
3
U2D1
21 R2D12
21
C2E4
21 R2E5
5
4
1
2
3
U2E2
2 1R5C11
2 1R5C12
2
1
R5R1
2
1
R5R2
2
1
R5R3
Y29
Y30
AA34
AA33
AB33
AB34
AA29
AA30
AC32
AC31
AB29
AB30
AD34
AD33
AD29
AD30
AC28
AC29
AC33
AC34
L34
L33
M34
M33
N31
N32
P29
P30
N34
N33
R29
R30
R34
R33
T31
T32
T29
T30
P33
P34
T28
AA28
D25
B29
A29
T33
T34
U30
U29
U33
U34
V31
V32
V29
V28
W33
W34
W30
W29
Y33
Y34
AA31
AA32
V33
V34
J30
J29
H31
H32
H34
H33
K30
K29
J31
J32
L30
L29
K33
K34
L32
L31
M29
M30
J34
J33
U4D1
C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13
IC
X02056-010
1 OF 8
FSB_CP_GP0_DATA7_DN
FSB_CP_GP0_DATA7_DP
FSB_CP_GP0_DATA6_DN
FSB_CP_GP0_DATA6_DP
FSB_CP_GP0_DATA5_DN
XENON_FABK
402
6.3V
10%
.1UF
X5R
402
5%
1K
CH
1K
5%
EMPTY
402
V_GPUCORE
6.3V
402
X5R
10%
.1UF
CH402
5%1K
5%
CH402
1K
.1UF
X5R
10%
402
6.3V
402
X5R
6.3V
10%
.1UF
10%.1UF
402
X5R
6.3V
10%
402
6.3V
X5R
.1UF
V_MEM
V_MEM
V_MEM
V_MEM
1K
5%
CH
402
5%
1K
CH
402
402
CH
5%
1K
402
5%
CH
1K
V_MEM
5%
CH
402
CH
5%
1K
6.3V
402
X5R
10%
.1UF
V_GPUCORE
X5R
6.3V
.1UF
402
10%
402
X5R
6.3V
10%
.1UF
1%
402
CH
4.87K
402
X5R
6.3V
10%
.1UF
402
X5R
6.3V
10%
.1UF
MEM_SCAN_EN_BUFF
FSB_GP_CP0_DATA7_DN
FSB_GP_CP1_CLK_DP
FSB_GP_CP1_CLK_DN
FSB_BYPCLK_SEL
FSB_CP_GP0_FLAG_DP
FSB_CP_GP0_FLAG_DN
FSB_CP_GP0_DATA0_DP
FSB_CP_GP0_DATA0_DN
FSB_CP_GP0_DATA1_DP
FSB_GP_CP0_FLAG_DN
FSB_GP_CP0_FLAG_DP
FSB_GP_CP0_CLK_DN
FSB_GP_CP0_CLK_DP
FSB_GP_CP0_DATA2_DP
FSB_GP_CP0_DATA2_DN
FSB_GP_CP0_DATA3_DP
FSB_CP_GP1_CLK_DP
FSB_CP_GP1_DATA2_DP
FSB_CP_GP1_DATA2_DN
FSB_CP_GP1_DATA3_DP
FSB_CP_GP1_DATA1_DN
FSB_CP_GP1_FLAG_DN
FSB_CP_GP0_DATA5_DP
FSB_CP_GP0_DATA4_DP
FSB_CP_GP0_DATA2_DN
FSB_CP_GP0_DATA2_DP
FSB_CP_GP0_DATA1_DN
FSB_CP_GP0_DATA4_DN
FSB_CP_GP0_DATA3_DN
FSB_CP_GP1_DATA4_DN
FSB_CP_GP1_DATA4_DP
FSB_CP_GP1_DATA3_DN
MEM_SCAN_TOP_EN_BUFF
MEM_SCAN_BOT_EN_BUFF
MEM_SCAN_BOT_EN
GPU_SCAN_BUFF_EN_N
MEM_SCAN_TOP_EN
FSB_GP_CP0_DATA5_DP
FSB_GP_CP0_DATA1_DN
FSB_GP_CP0_DATA1_DP
FSB_GP_CP0_DATA0_DN
FSB_GP_CP0_DATA5_DN
FSB_GP_CP1_DATA2_DP
FSB_CP_GP0_CLK_DP
FSB_GP_CP0_DATA7_DP
FSB_GP_CP0_DATA6_DN
FSB_GP_CP0_DATA6_DP
FSB_GP_CP1_DATA7_DN
FSB_BYPCLK_DP
FSB_BYPCLK_DN
FSB_IMPED_NCAL
FSB_IMPED_CAL
FSB_GP_CP1_DATA7_DP
FSB_GP_CP1_DATA5_DN
FSB_GP_CP1_DATA6_DP
FSB_GP_CP1_DATA6_DN
FSB_GP_CP1_DATA1_DN
FSB_GP_CP1_DATA0_DP
FSB_GP_CP1_DATA1_DP
FSB_GP_CP0_DATA4_DN
FSB_GP_CP0_DATA0_DP
FSB_CP_GP0_CLK_DN
FSB_CP_GP0_DATA3_DP
FSB_CP_GP1_CLK_DN
FSB_CP_GP1_FLAG_DP
FSB_CP_GP1_DATA0_DP
FSB_CP_GP1_DATA0_DN
FSB_CP_GP1_DATA1_DP
FSB_CP_GP1_DATA5_DP
FSB_CP_GP1_DATA5_DN
FSB_CP_GP1_DATA6_DP
FSB_CP_GP1_DATA6_DN
FSB_CP_GP1_DATA7_DP
FSB_CP_GP1_DATA7_DN
FSB_GP_CP0_DATA4_DP
FSB_GP_CP1_DATA0_DN
FSB_GP_CP1_FLAG_DN
FSB_GP_CP1_DATA2_DN
FSB_GP_CP1_DATA4_DP
FSB_GP_CP1_DATA4_DN
FSB_GP_CP0_DATA3_DN
FSB_GP_CP1_DATA5_DP
FSB_GP_CP1_DATA3_DN
FSB_GP_CP1_DATA3_DP
FSB_GP_CP1_FLAG_DP
MEM_SCAN_EN
EMPTY
X801565-001
EMPTY
X801565-001
1K
402
EMPTY
402
5%0
CH
5%
402 CH
0
X801565-001
402
0 5%
CH
5%
402
CH
0
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
GPU VERSION 57
GP_CP0_DATA2_DP
GP_CP0_DATA1_DN
GP_CP0_DATA1_DP
GP_CP0_DATA0_DN
CP_GP0_FLAG_DN
CP_GP0_DATA0_DP
FSB_BYPCLK_SEL
FSB_BYPCLK_DN
FSB_BYPCLK_DP
CP_GP1_DATA6_DN
CP_GP1_DATA7_DP
CP_GP1_DATA7_DN
FSB_IMPED_NCAL
GP_CP1_FLAG_DP
GP_CP1_FLAG_DN
CP_GP1_DATA3_DP
CP_GP1_FLAG_DP
CP_GP1_CLK_DN
CP_GP1_CLK_DP
CP_GP0_DATA3_DN
CP_GP0_DATA3_DP
CP_GP0_DATA4_DP
CP_GP0_DATA4_DN
CP_GP0_DATA5_DP
CP_GP0_DATA5_DN
CP_GP0_DATA6_DN
CP_GP0_DATA7_DP
CP_GP0_DATA7_DN
GP_CP0_FLAG_DN
GP_CP0_DATA0_DP
GP_CP0_DATA4_DN
GP_CP0_DATA6_DP
GP_CP0_DATA5_DN
GP_CP0_DATA5_DP
GP_CP1_CLK_DN
GP_CP1_DATA1_DP
GP_CP1_DATA0_DN
GP_CP1_DATA0_DP
GP_CP1_DATA1_DN
GP_CP1_DATA4_DP
GP_CP1_DATA3_DN
GP_CP1_DATA3_DP
GP_CP1_DATA2_DN
GP_CP1_DATA2_DP
GP_CP1_DATA6_DN
GP_CP1_DATA6_DP
GP_CP1_DATA5_DN
GP_CP1_DATA5_DP
GP_CP1_DATA4_DN
GP_CP1_DATA7_DN
GP_CP1_DATA7_DP
GP_CP1_CLK_DP
GP_CP0_DATA7_DN
GP_CP0_DATA7_DP
GP_CP0_DATA6_DN
CP_GP0_DATA2_DN
CP_GP0_DATA2_DP
CP_GP0_DATA1_DN
CP_GP0_DATA1_DP
CP_GP0_DATA6_DP
GP_CP0_FLAG_DP
GP_CP0_CLK_DN
GP_CP0_CLK_DP
GP_CP0_DATA4_DP
GP_CP0_DATA3_DN
GP_CP0_DATA3_DP
GP_CP0_DATA2_DN
FSB_IMPED_PCAL
CP_GP1_FLAG_DN
CP_GP1_DATA6_DP
CP_GP1_DATA5_DN
CP_GP1_DATA5_DP
CP_GP1_DATA4_DN
CP_GP1_DATA4_DP
CP_GP1_DATA3_DN
CP_GP1_DATA2_DN
CP_GP1_DATA0_DP
CP_GP1_DATA0_DN
CP_GP1_DATA1_DP
CP_GP1_DATA1_DN
CP_GP1_DATA2_DP
CP_GP0_DATA0_DN
CP_GP0_FLAG_DP
CP_GP0_CLK_DN
CP_GP0_CLK_DP
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
SN74LVC1G125
VCC
GND OE_N
IN OUT
SN74LVC1G125
VCC
GND OE_N
IN OUT
SN74LVC1G125
VCC
GND OE_N
IN OUT
IN
IN
IN
IN
IN
IN
OUT
VIDEO DECOUPLING
GPU, VIDEO + PCIEX + EEPROM + JTAG
[PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG] K713/73XENON_RETAIL
13
13
29
33
46
46
28
29
33
33
33
28
29
29
29
12
33
13
13
13
34 34
13
33
29
13
13
29
20 21 22 23 24 25 26 27
13
13
33
33
29
34 56
13
12
12
12
Wed Aug 24 09:27:07 2005
21 R3C28
21 R4D3
21 R4D4
2
1
R5P3
2
1
R5C10
2
1R4C7
2
1
R4C6
1
FT2P13
1
FT2P14
2
1
R2E4
1 DB4D1
2
1
R4D2
2
1
R4D1
2
1
R2D10
2
1
R2E3
2
1
R2E2
2
1
R2D9
21 R4R3
65
43
21
J5C2
R4C3
R5C5
R5C8
2 1R4C5
2 1R4C4
3
8
2
5
6
7
4
1
U4C1 2
1
C5C3
2
1
R4F6
2
1
R2E1
21 R4T1
21 R4R8
21 R5D1
87
65
43
21
J2D2
A11
G13
G11
G12
D12
E12
E13
G16
E16
E15
G17
E14
E11 D14
D15
B15
A15
A14
D13
B13
A13
B12
B17
A17
D16
B16
A16
A12
D11
B14
D10
C10
B23
A23
B27
A27
B22
A22
B26
A26
A28
B28
B21
C22
C23
A25
A24
G10
G9
AN13
AG11
V8
AG16
B11
G14
G15
U4D1
21 R5D2
C3C2 C4R2 C4R26 C4R1
21
C5D1
21
C4D3
21
C4D2
21
C4D1
X02056-010
IC2 OF 12
GPU_SPI_SI
GPU_SPI_WP_N
402
562
EMPTY
X800552-001
EMPTY
V_1P8
EMPTY
402
CH
402
1K
5%
EMPTY
1K
5%
402
402
GPU_PIX_CLK_1X
.1UF
6.3V
PEX_GPU_SB_L0_DN
EMPTY402
1%49.9
GPU_CLK_DP
GPU_CLK_DN
EMPTY
49.9 1%
402
1%
ANA_PIX_CLK_2X_DP
GPU_TEMP_P
1%
CH V_GPUPCIE
CH
1%
V_MEM
X5R
805
20%
6.3V
10UF
X5R
402 402
PEX_PCAL
1.47K
402
V_MEM
GPU_TRST
402
40.2
GPU_TCLK
PEX_SB_GPU_L1_DP
PEX_SB_GPU_L1_DN
PEX_SB_GPU_L0_DP
PEX_ICAL
ANA_PIX_CLK_2X_DN
EDRAM_TEMP_P
EDRAM_TEMP_N
GPU_TEMP_N
1.5K
1%
CH
EMPTY
G
P
U
_S
C
A
N
_B
U
F
F
_E
N
_N
PEX_SB_GPU_L0_DN
CH402
2K
GPU_SPI_CS_N
GPU_SPI_CLK
GPU_SPI_SO
GPU_TMS
GPU_TRST_ED
GPU_SPI_SO_R
GPU_RST_N GPU_RST_DONE
PEX_GPU_SB_L1_DP_C
PEX_GPU_SB_L0_DP_C
PEX_GPU_SB_L0_DN_C
GPU_SROM_EN_PSRO_OUT
MEM_CALB
GPU_SPI_SI
PEX_GPU_SB_L1_DN_C
PEX_GPU_SB_L0_DP
GPU_VSYNC_OUT
GPU_SPI_CS_N
GPU_SPI_SO
GPU_HSYNC_OUT
MEM_RST
GPU_SPI_CLK
GPU_SPI_WP_N
GPU_SPI_CLK_R
GPU_TDI
GPU_TDO
MEM_CALA
5%
402
CH
1K1K
CH
5%
402
6.3V
X5R
402
.1UF
10%
6.3V
10%
X5R
.1UF
1%
X5R
402
10%
X5R
.1UF
402
1%
X5R
10%
6.3V
.1UF
1
0
2
3
4
6
5
7
8
9
10
12
11
14
13
V_1P8
5%
402
CH
10K
5%
CH
402
10K
402
CH
5%
10K
CH
10K
402
5%
1.5K
CH
1%
402
TP
V_MEM
CH
402
1%
1.5K
CH
402
402
1%
402
CH
1.5K
CH
1%
5%
CH402
1K
1K
402 CH
5%
.1UF
10%
6.3V
402
1K
CH
5%
10K 5%
402
V_1P8
CH
5%10K
V_1P8
402
X5R
10%
X5R
.1UF
6.3V
PEX_NCAL
6.3V
10%
PEX_GPU_SB_L1_DN
PEX_GPU_SB_L1_DP
402
PIX_DATA<14..0>
402
40.2
DBG_LED3
1%
CH
1.5K
V_MEM
1.27K
CH402
XENON_FABK
GPU_SPI_CS_N_R
.1UF
10%
6.3V
GPU_SPI_SI
MEM_SCAN_BOT_EN_BUFF
MEM_SCAN_TOP_EN_BUFF
MEM_SCAN_EN_BUFF
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2X4HDR
IN
IN
GPU VERSION 57
PEX_RX1_DN
PEX_RX0_DP
PEX_RX0_DN
PEX_RX1_DP
PEX_ICAL
PIX_CLK_IN_DP
ED_THERMD_N
ED_THERMD_P
NB_THERMD_P
NB_THERMD_N
PIX_CLK_IN_DN
PIX_DATA2
PIX_DATA3
PIX_DATA4
PIX_DATA5
PEX_NCAL
PEX_PCAL
RST_IN_N*
NB_CLK_DN
PIX_DATA8
PIX_DATA9
PIX_DATA12
PIX_DATA11
PIX_DATA10
PIX_DATA7
PIX_DATA6
PIX_DATA1
PIX_DATA0
VSYNC_OUT
SROM_EN_PSRO_OUT
SROM_SI
SROM_SCLK
SROM_CS
SROM_SO
MEM_RST
MEM_SCAN_EN
MEM_SCAN_OEN_A
MEM_SCAN_OEN_B
PEX_TX0_DN
PIX_CLK_OUT
MEM_CALA
MEM_CALB
TCLK
TDO
TDI
TRST_ED
TRST
TMS
RST_DONE
PEX_TX1_DP
PEX_TX1_DN
PEX_TX0_DP
PIX_DATA14
PIX_DATA13
HSYNC_OUT
NB_CLK_DP
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
FTPFTP
IN
OUT
OUT
2X3HDR
IN
IN
IN
AT25020A
GND
SDO
VCC
WP_N*
CS_N*
HOLD_N*
SDI
SCK
OUT
OUT
OUT
OUT
OUT
OUT
MEMORY CONTROLLER B, DECOUPLING
MEMORY CONTROLLER A, DECOUPLING
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B]
GPU, MEMORY CONTROLLER 0 PARTITION A & B
K714/73XENON_RETAIL
2223
2223
2021
2021
2021
2021
2021
2021
2021
2021
20 21
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
2021
21
21
20
20 21
20 21
21
20 21
2021
2021
2021
2021
2021
2021
2021
2021
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
23
22
22
232223
22 23
22 23
22 23
22 23
22
23
2223
2223
2223
2223
2223
2223
20
20
22 23
22 2320 21
20 21
Wed Aug 24 09:27:08 2005
2
1
R4T3
2
1
C4T40
2
1
R4T4
2
1 C4T45
AJ9
AP20
AP14
AK19
AM12
AK6
AP13
AM18
AL15
AK17
AJ14
AK7
AJ18
AH18
AK15
AH11
AH15
AK11
AP19
AN19
AH13
AL18
AN20
AN18
AM20
AN17
AL20
AP15
AN15
AM15
AN14
AK12
AN16
AL13
AP17
AM13
AH16
AK20
AK16
AH20
AH17
AJ19
AJ13
AH12
AP18
AP16
AM17
AK14
AK9
AL10
AH10
AK10
AN12
AP12
AN6
AK8
AP10
AM10
AP5
AP8
AN11
AP9
AN10
AP11
AN9
AN8
AN7
AN4
AP7
AP4
AN5
AP6
U4D1
2
1
R4T6
2
1
R4T7
C4T35
C4R3
C4T27 C4T41
C4T29 C4T32
C4T43
C4T42 C4T44
2
1
R5E1
2
1 C5E1
2
1
R5E2
2
1 C4T46
2
1
R4T8
2
1
R4T5
AF33
AP30
AN22
AK30
AM22
AG33
AP21
AN26
AP24
AN28
AJ24
AF31
AK28
AK29
AK25
AH21
AH25
AK21
AN27
AP28
AH23
AP27
AP29
AL25
AP31
AM25
AP32
AM23
AP23
AL23
AN23
AK22
AN25
AP22
AP25
AN21
AH26
AN32
AK26
AN31
AN29
AN30
AJ23
AH22
AP26
AN24
AK27
AK24
AH34
AF34
AM33
AM34
AL33
AL34
AG34
AF32
AH30
AH33
AG30
AJ30
AK33
AJ33
AK34
AM32
AJ34
AE30
AF28
AK32
AE29
AE34
AE33
AF29
U4D1
C4T47
C4T33 C5T3
C4T31
C5T4 C5T1
C4T34 C5T2 C4T39
X02056-010
IC4 OF 8
X02056-010
IC3 OF 8
MB_DQ1
MB_DQ0
XENON_FABK
MA_DQ17
MA_DQ16
MA_WDQS2
.22UF
6.3V
.22UF
402
10%
6.3V
X5R
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
10%
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
6.3V
V_MEM
549
MA_DQ29
.22UF
10%
6.3V
X5R
402
.22UF
X5R
402
6.3V
10%
.22UF
6.3V
402
X5R
10%
.22UF
6.3V
X5R
402
10%
.22UF
6.3V
X5R
402
10%
.22UF
402
10%
6.3V
X5R
.22UF
6.3V
10%
X5R
402
.22UF
X5R
10%
6.3V
402
V_MEM
MA_DQ10
MA_DQ11
MA_DQ12
MA_DQ13
MB_VREF1
MA_RAS_N
MB_VREF0
MA_RDQS0
MA_DM0
MA_WDQS0
MA_DQ1
MA_DQ0
MA_DQ3
MA_DQ2
MA_DQ4
MA_DQ6
MA_DQ5
MA_DQ7
MA_DM1
MA_WDQS1
MA_RDQS1
MA_DQ8
MA_DQ9
MA_DQ15
MA_DQ14
MA_DM2
MA_RDQS2
MA_DQ18
MA_DQ19
MA_DQ21
MA_DQ20
MA_DQ22
MA_DQ28
MA_DQ27
MA_DQ26
MA_CLK1_DP
MA_CLK1_DN
MA_CLK0_DP
MA_WE_N
MA_CAS_N
MA_CS1_N
MA_CKE
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DQ31
MA_DQ30
MA_DM3
MA_DQ23
MB_DM0
MB_RDQS0
MB_WDQS0
MB_DQ3
MB_DQ2
MB_DQ4
MB_DQ6
MB_DQ5
MB_DQ7
MB_DM1
MB_WDQS1
MB_RDQS1
MB_DQ8
MB_DQ10
MB_DQ9
MB_DQ12
MB_DQ11
MB_DQ13
MB_DQ15
MB_DQ14
MB_DM2
MB_RDQS2
MB_WDQS2
MB_DQ16
MB_DQ17
MB_DQ18
MB_DQ19
MB_DQ21
MB_DQ20
MB_DQ22
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_CLK1_DN
MB_CLK0_DP
MB_CLK0_DN
MB_CLK1_DPMB_DQ23
MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS0_N
MB_CS1_N
MB_WDQS3
MB_RDQS3
MB_DM3
MB_DQ31
MB_DQ30
MB_DQ29
MA_VREF1
MA_CLK0_DN
MA_CS0_N
MA_VREF0
MB_A<12..0>
MB_BA<2..0>MA_BA<2..0>
MA_A<12..0>
1.27K
1%
402
CH
.1UF
10%
6.3V
X5R
402
549
1%
402
CH
.1UF
10%
402
X5R
6.3V
402
CH
1%
1.27K
1%
CH
402
V_MEM
V_MEM
1206
X5R
10%
10UF
0
1
2
2
0
1
3
4
5
CH
402
1.27K
1%
7
X5R
6.3V
.1UF
402
10%
1%
549
402
CH
X5R
.1UF
10%
6.3V
402
V_MEM
6
9
8
11
10
1.27K
CH
402
1%
CH
402
549
1%
V_MEM
1206
6.3V
10%
10UF
X5R
12
0
1
2
1
0
2
3
4
5
6
7
9
8
11
10
12
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
OUT
OUT
IN
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
BI
BI
BI
BI
OUT
BI
BI
BI
OUT
OUT
IN
BI
BI
BI
BI
BI
BI
GPU VERSION 57
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_CLK1_DN
MB_CLK0_DP
MB_CLK0_DN
MB_CLK1_DPMB_DQ23
MB_BA0
MB_CKE
MB_WE_N*
MB_CAS_N*
MB_RAS_N*
MB_CS0_N*
MB_CS1_N*
MB_WDQS1
MB_DQ17
MB_DQ18
MB_RDQS1
MB_DM1
MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_WDQS3
MB_RDQS3
MB_DQ22
MB_DQ21
MB_DQ19
MB_DQ16
MB_WDQS2
MB_DM3
MB_RDQS2
MB_DM2
MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0
MB_VREF1
MB_VREF0
MB_A9
MB_A8
MB_A7
MB_A6
MB_A5
MB_A4
MB_A3
MB_A2
MB_A1
MB_A0
MB_BA2
MB_DQ20
MB_A10
MB_A11
MB_A12
MB_BA1
MB_DQ31
MB_DQ30
MB_DQ29
OUT
OUT
OUT BI
BI
OUT
IN
OUT
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
BI
BI
BI
BI
BI
BI
GPU VERSION 57
MA_DQ28
MA_DQ27
MA_DQ26
MA_CLK1_DP
MA_CLK1_DNMA_CLK0_DP
MA_CLK0_DN
MA_RDQS2
MA_WDQS2
MA_A8
MA_A7
MA_A6
MA_WE_N*
MA_CAS_N*
MA_RAS_N*
MA_CS0_N*
MA_CS1_N*
MA_CKE
MA_DQ12
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DM3
MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_DM2
MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0
MA_VREF1
MA_VREF0
MA_A9
MA_A5
MA_A4
MA_A3
MA_A2
MA_A1
MA_A0
MA_BA2
MA_BA1
MA_BA0
MA_A10
MA_A11
MA_A12
BI
BI
OUT
IN
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
MEMORY CONTROLLER D, DECOUPLING
PAGE_TITLE=[GPU, MEMORY CONTROLLER C + D]
MEMORY CONTROLLER C, DECOUPLING
GPU, MEMORY CONTROLLER 1 PARTITION C & D
K715/73XENON_RETAIL
24 25
2627
2627
2425
2425
24 25
2425
24
24
25
25
24
2627
2425
2425
2425
26
27
26 27
26 27
26 27
26 27
2627
25
24 25
24 25
24 25
2425
2627
2627
2627
2627
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
27
27
26
26
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2627
2425
2425
2425
2425
2425
2425
26 27
26 2724 25
Wed Aug 24 09:27:10 2005
2
1
R4R5
2
1 C4R25
2
1 C4R10
2
1
R4R2
2
1
R4R1
2
1
R4R4
E7
T1
K1
M7
D2
G1
E10
P2
M1
K5
G5
E9
L7
M3
H2
B2
H5
C2
R1
R3
F2
R2
R4
N4
T2
N3
U1
L1
K4
L2
K3
E5
N2
K2
N1
J2
J6
N6
J5
N7
L5
M5
F5
E2
P1
M2
K7
G2
E6
B3
J1
H1
F1
E1
A8
E8
B4
A3
B9
B6
D1
A5
A4
C1
B5
A6
B7
A10
A7
B10
A9
B8
U4D1
2
1 C4R23
2
1 C4R66
2
1
C3R5
2
1
C4R38
2
1 C4T12
2
1 C4R32
2
1
C4R51
2
1
C4T14
2
1
C4R48
2
1
R4T2
2
1 C4T36
2
1
C4R64
2
1
R4R7
2
1
R4R6
2
1
R3T2
AH1
AD2
V3
AB7
R7
AF1
U2
AC2
Y1
Y5
U5
AL1
AA7
AB3
V7
P6
V6
P5
AC3
AC4
U3
AC1
AD1
AB1
AE2
AA2
AE1
W2
W1
Y2
V4
R5
Y4
V1
AA1
V2
W6
AC7
W5
AC6
AA5
AB5
T5
T7
AB2
Y3
Y7
U7
AH5
AG1
AD6
AD5
AE4
AE3
AK1
AJ1
AG5
AH2
AJ5
AF5
AE5
AF2
AF7
AE7
AG2
AM1
AJ2
AK5
AL2
AM2
AM3
AK2
U4D1
2
1
C4T7
2
1
C4T28
2
1
C4R31
2
1
C4R12
2
1
C4R15
2
1
C4R61
2
1
C4R19
2
1
C4T38
2
1
C4R50
X02056-010
IC6 OF 8
X02056-010
IC5 OF 8
2
MC_BA<2..0>
MD_DQ23
MD_RDQS3
XENON_FABK
V_MEM
V_MEM
V_MEM
.22UF
6.3V
402
X5R
402
CH
MC_DQ0
MC_DQ4
6.3V
402
.22UF
6.3V
X5R
402
10%
.22UF
402
X5R
6.3V
10%
.22UF
402
X5R
6.3V
10%
.22UF
402
X5R
6.3V
10%
.22UF
402
X5R
6.3V
10%
.22UF
402
X5R
6.3V
10%
.22UF
X5R
10%
.22UF
X5R
6.3V
10%
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
402
.22UF
6.3V
10%
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
10%
X5R
MC_RAS_N
MC_DQ6
MD_VREF1
MC_CLK0_DN
MC_CLK0_DP
MC_CLK1_DN
MC_CLK1_DP
MC_CS0_N
MD_DM0
MC_DQ5
MC_DQ3
MC_DM0
MD_CS0_N
MD_CS1_N
MD_RAS_N
MD_CAS_N
MD_WE_N
MD_CKE
MD_DM1
MC_CS1_N
MC_CAS_N
MC_WE_N
MC_CKE
MC_DQ2
MD_WDQS1
MD_DQ2
MD_DQ1
MD_DQ0
MC_DQ23
MC_DQ20
MC_DQ31
MC_DQ30
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3
MC_DQ22
MC_DQ21
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DQ14
MC_DQ13
MC_DQ11
MC_DQ10
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1
MC_DQ7
MC_DQ1
MC_WDQS0
MC_RDQS0
MD_CLK1_DP
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN
MD_DQ30
MD_DQ29
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_WDQS0
MD_RDQS0
MD_DQ20
MD_DQ19
MD_DQ31
MD_DQ28
MD_DQ27
MD_DQ26
MD_DM3
MD_DM2
MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_RDQS1
MD_DQ7
MD_DQ5
MD_DQ4
MD_DQ3
MD_WDQS3
MD_DQ24
MD_DQ25
MD_DQ22
MD_DQ21
MD_DQ6
MC_DQ9
MC_DQ12
MC_DQ15
MC_DQ29
MC_DQ28
MC_VREF1
MC_VREF0
MD_VREF0
MC_DM2
MD_BA<2..0>
MD_A<12..0>MC_A<12..0>
CH
1%
402
1.27K
402
549
CH
1%
CH
402
1%
549
V_MEM
12
11
V_MEM
12
11
10UF
6.3V
10%
X5R
1206
V_MEM
1
0
0
2
1
2
5
3
4
7
402
1.27K
CH
1%
X5R
402
10%
.1UF
6.3V
X5R
10%
6.3V
.1UF
1%
402
1.27K
CH
549
1%
402
402
CH
1%
549
6
9
10
8
1206
X5R
6.3V
10%
10UF
1
0
0
1
2
5
4
3
7
6
9
10
8
CH
1%
1.27K
402402
X5R
10%
6.3V
.1UF
402
.1UF
10%
6.3V
X5R
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
OUT
IN
OUT
BI
BI
OUT
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
BI
BI
GPU VERSION 57
MD_DQ30
MD_DQ29
MD_DQ28
MD_CLK1_DP
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN
MD_A12
MD_A11
MD_A10
MD_CAS_N*
MD_RAS_N*
MD_CS0_N*
MD_CS1_N*
MD_WE_N*
MD_CKE
MD_BA0
MD_A9
MD_A8
MD_A3
MD_A4
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_WDQS0
MD_RDQS0
MD_DM0
MD_VREF1
MD_VREF0
MD_DQ23
MD_DQ22
MD_DQ31
MD_DQ27
MD_RDQS3
MD_DM3
MD_DM2
MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1
MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_A7
MD_A6
MD_A5
MD_A2
MD_A1
MD_A0
MD_BA2
MD_BA1
MD_WDQS3
MD_DQ24
MD_DQ18
MD_DQ19
MD_DQ21
MD_DQ20
MD_DQ25
MD_DQ26
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
BI
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
IN
OUT
OUT
BI
BI
BI
BI
BI
IN
BI
OUT
OUT
BI
GPU VERSION 57
MC_DQ30
MC_DQ24
MC_WDQS3
MC_CLK1_DP
MC_CLK1_DN
MC_CLK0_DP
MC_CLK0_DN
MC_A9
MC_A8
MC_A7
MC_A6
MC_CAS_N*
MC_RAS_N*
MC_CS1_N*
MC_CS0_N*
MC_WE_N*
MC_CKE
MC_A3
MC_A2
MC_DQ23
MC_DQ20
MC_DQ29
MC_DQ31
MC_DQ28
MC_DQ27
MC_RDQS3
MC_DM3
MC_DQ22
MC_DQ21
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2
MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1
MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0
MC_VREF1
MC_VREF0
MC_A5
MC_A4
MC_A1
MC_A0
MC_BA2
MC_BA1
MC_BA0
MC_A10
MC_A11
MC_A12
MC_DQ10
MC_DQ11
MC_DQ12
MC_DQ25
MC_DQ26
BI
BI
BI
BI
BI
IN
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
[PAGE_TITLE=GPU, PLL POWER + FSB POWER]
GPU, PLL POWER + FSB POWER
K716/73XENON_RETAILWed Aug 24 09:27:10 2005
2
1
C5R19
2
1
C4R68
2
1
C4T48
2
1
C4D6
2
1 C5R7
2
1 C4R8
21
FB4D1
2
1
C4D5
2
1
C4D4
21
FB5R1
2
1
C5R13
2
1 C4R5
21
FB4R1
2
1
C4R4
21
FB4T1
2
1
C4T30
C5R15
C4R7
C4R6
C26
C24
R32
T27
U28
U31
V27
V30
W28
AA27
AB28
AB32
AC27
AD28
W32
AD31
K28
K31
L27
M28
M32
N27
P28
P31
R28
Y28
Y31
C27
C25
B24
AG9
F34
A19
A21
B25
AG10
G34
A18
A20
U4D1
C4T37
X02056-010
IC8 OF 12
XENON_FABK
V_PVDDA_ED
V_PVDDA_FSB
V_PVDDA
V_PVDDA_MEM
X7R
0.01UF
402
16V
10%
402
X7R
16V
0.01UF
10%
6.3V
X5R
603
10%
2.2UF
603
X5R
6.3V
10%
2.2UF
10%
2.2UF
6.3V
X5R
603
X5R
10%
2.2UF
603
6.3V
V_GPUPCIE
6.3V
402
X5R
.1UF
10%
402
.1UF
6.3V
X5R
10%
X7R
402
0.01UF
16V
10%
V_GPUCORE
120
0.2A
0.5 DCR
FB
603
402
.1UF
6.3V
X5R
10%
0.01UF
X7R
16V
10%
402
V_GPUPCIE
V_GPUCORE
120
0.2A
0.5 DCR
FB
603
402
.1UF
X5R
6.3V
10%
10%
402
.1UF
6.3V
X5R
0.2A
0.5 DCR
120 FB
603
.1UF
402
6.3V
X5R
10%
120
0.2A
0.5 DCR
FB
603
402
10%
X5R
.1UF
6.3V
0.01UF
10%
X7R
16V
402
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
GPU VERSION 57
VDD_FSB0
VDD_FSB1
VDD_FSB2
VDD_FSB3
VDD_FSB4
VDD_FSB5
VDD_FSB6
VDD_FSB7
VDD_FSB8
VDD_FSB9
VDD_FSB10
VDD_FSB11
VDD_FSB12
VDD_FSB13
VDD_FSB14
VDD_FSB15
VDD_FSB16
VDD_FSB17
VDD_FSB18
VDD_FSB19
VDD_FSB20
VDD_FSB21
VDD_FSB22
VDD_FSB23
VDD_FSB24
PVSSA_FSB
PVDDA_FSB
PVSSA_PEX
PVDDA_MEM
VSS_BSB0
VDD_BSB0
PVDDA_PEX
PVSSA_ED
PVDDA_ED
PVSSA_MEM
PVDDA
PVSSA
VDD_BSB1
VSS_BSB1
[PAGE_TITLE=GPU, CORE POWER + MEM POWER]
GPU, CORE POWER + MEM POWER
K717/73XENON_RETAILWed Aug 24 09:27:11 2005
L3
L8
L14
L15
L16
L19
L20
L21
L28
M4
Y11
M8
M14
M15
M16
M19
M20
M21
M27
M31
N14
Y12
N15
N16
N19
N20
N21
N28
N29
N30
P3
P8
Y13
P11
P12
P13
P17
P18
P22
P23
P24
P27
P32
Y17
R6
R11
R12
R13
R17
R18
R22
R23
R24
R27
Y18
R31
T4
T8
T11
T12
T13
T17
T18
T22
T23
Y22
T24
U6
U14
U15
U16
U19
U20
U21
U27
U32
Y23
V5
V14
V15
V16
V19
V20
V21
W4
W8
W11
Y24
W12
W13
W17
W18
W22
W23
F21
W24
F24
F26
F28F31
G4
G7
G18
G20
G27
G29
W27
G33
H3
H6
H8
H9
H11
H13
H15
H17
H19
W31
H21
H23
H25
H28
J4
J8
J28
K6
K27
K32
Y6
Y27
Y32
U4D1
D20
D22
D30
D32
D34
E17
E19
E21
E31
F17
W16
F18
F20
F23
F25
F27
F29
F30
G19
G28
G32
W19
H12
H14
H16
H18
H20
H22
H24
H26
H27
J27
W20
L11
L12
L13
L17
L18
L22
L23
L24
M11
M12
W21
M13
M17
M18
M22
M23
M24
N11
N12
N13
N17
Y14
N18
N22
N23
N24
P14
P15
P16
P19
P20
P21
Y15
R14
R15
R16
R19
R20
R21
T14
T15
T16
T19
Y16
T20
T21
U11
U12
U13
U17
U18
U22
U23
U24
Y19
V11
V12
V13
V17
V18
V22
AA14
AA15
AA16
AA19
AA20
AA21
AB11
AB12
AB13
AB17
V23
AB18
AB22
AB23
AB24
AC11
AC12
AC13
AC17
AC18
AC22
V24
AC23
AC24
AD11
AD12
AD13
AD17
AD18
AD22
AD23
AD24
W14
B18
B20
C19
C21
C29
C31
C33
C34
D17
D18
W15
Y20
Y21
U4D1
AF27
AF30
AG4
AG7
AG13
AG15
AG17
AG20
AG23
AG25
P4
AG28
AG32
AH3
AH6
AH8
AH9
AH14
AH19
AH24
AH27
P7
AH29
AH31
AJ4
AJ7
AJ11
AJ12
AJ16
AJ21
AJ22
AJ26
R8
AJ28
AJ32
AK3
AK13
AK23
AK31
AL4
AL6
AL8
AL11
T3
AL14
AL17
AL21
AL24
AL28
AL30
AL32
AM5
AM7
AM9
T6
AM16
AM19
AM26
AM27
AM29
AM31
AN2
AP3
C3
C5
U4
C7
C9
C12
C14
C16
C18
D4
D6
D8
E3
U8
F4
F7
F9
F11
F13
F15
G3
G6
G8
H4
W3
H7
H10
J3
J7
K8
L4
L6
M6
AA4
AA6
N5
AB6
AC5
AC8
AD4
AD7
AE8
AE28
AE31
AF3
AF6
N8
W7
Y8
U4D1
A1
AA3
AA8
AA11
AA12
AA13
AA17
AA18
AA22
AA23
AA24
AB4
AB8
AB14
AB15
AB16
AB19
AB20
AB21
AB27
AB31
AC14
AC15
AC16
AC19
AC20
AC21
AC30
AD3
AD8
AD14
AD15
AD16
AD19
AD20
AD21
AD27
AD32
AE6
AE27
AE32
AF4
AF8
AG3
AG6
AG8
AG12
AG14
AG18
AG19
AG21
AG22
AG24
AG26
AG27
AG29
AG31
AH4
AH7
AH28
AH32
AJ3
AJ6
AJ8
AJ10
AJ15
AJ17
AJ20
AJ25
AJ27
AJ29
AJ31
AK4
AK18
AL3
AL5
AL7
AL9
AL12
AL16
AL19
AL22
AL26
AL27
AL29
AL31
AM4
AM6
AM8
AM11
AM14
AM21
AM24
AM28
AM30
AN3
AN33
B19
B33
C4
C6
C8
C11
C13
C15
C17
C20
C28
C32
D3
D5
D7
D9
D19
D21
D31
E4
E18
E20
E22
E30
E32
F3
F6
F8
F10
F12
F14
F16
F19
U4D1
X02056-010
IC
12 OF 12
BGAX02056-010
IC
11 OF 12
BGA
X02056-010
IC10 OF 12
BGA
X02056-010
IC9 OF 12
BGA
XENON_FABK
V_GPUCOREV_GPUCORE
V_MEMV_MEM
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
GPU VERSION 51
VSS65
VSS59
VSS60
VSS53
VSS54
VSS55
VSS48
VSS49
VSS52
VSS51
VSS50
VSS43
VSS47
VSS46
VSS38
VSS41
VSS42
VSS40
VSS39
VSS28
VSS30
VSS29
VSS27
VSS23
VSS26
VSS25
VSS24
VSS22
VSS17
VSS18
VSS20
VSS21
VSS19
VSS12
VSS13
VSS16
VSS15
VSS14
VSS7
VSS8
VSS11
VSS10
VSS9
VSS2
VSS3
VSS6
VSS5
VSS4
VSS1
VSS0
VSS31
VSS33
VSS34
VSS35
VSS36
VSS37
VSS120
VSS118
VSS113
VSS112
VSS111
VSS110
VSS109
VSS107
VSS108
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS94
VSS95
VSS89
VSS90
VSS88
VSS86
VSS87
VSS83
VSS84
VSS85
VSS81
VSS82
VSS78
VSS79
VSS80
VSS77
VSS76
VSS75
VSS73
VSS74
VSS66
VSS32
VSS44
VSS45
VSS58
VSS93
VSS92
VSS91
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS63
VSS62
VSS57
VSS56
VSS114
VSS115
VSS116
VSS122
VSS121
VSS119
VSS117
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS61
VSS64
GPU VERSION 57
VDD_CORE136
VDD_CORE137
VDD_CORE138 VDD_CORE68
VDD_CORE67
VDD_CORE139
VDD_CORE32
VDD_CORE31
VDD_CORE33
VDD_CORE1
VDD_CORE2
VDD_CORE3
VDD_CORE0
VDD_CORE6
VDD_CORE7
VDD_CORE8
VDD_CORE5
VDD_CORE4
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE10
VDD_CORE9
VDD_CORE16
VDD_CORE17
VDD_CORE18
VDD_CORE15
VDD_CORE14
VDD_CORE21
VDD_CORE22
VDD_CORE23
VDD_CORE20
VDD_CORE19
VDD_CORE24
VDD_CORE26
VDD_CORE27
VDD_CORE28
VDD_CORE25
VDD_CORE29
VDD_CORE30
VDD_CORE34
VDD_CORE36
VDD_CORE37
VDD_CORE38
VDD_CORE39
VDD_CORE35
VDD_CORE41
VDD_CORE42
VDD_CORE44
VDD_CORE43
VDD_CORE40
VDD_CORE47
VDD_CORE48
VDD_CORE49
VDD_CORE46
VDD_CORE45
VDD_CORE52
VDD_CORE53
VDD_CORE54
VDD_CORE51
VDD_CORE50
VDD_CORE57
VDD_CORE58
VDD_CORE59
VDD_CORE56
VDD_CORE55
VDD_CORE62
VDD_CORE63
VDD_CORE64
VDD_CORE61
VDD_CORE60
VDD_CORE69
VDD_CORE66
VDD_CORE65
VDD_CORE103
VDD_CORE71
VDD_CORE72
VDD_CORE73
VDD_CORE70
VDD_CORE76
VDD_CORE77
VDD_CORE78
VDD_CORE75
VDD_CORE74
VDD_CORE81
VDD_CORE82
VDD_CORE83
VDD_CORE80
VDD_CORE79
VDD_CORE86
VDD_CORE87
VDD_CORE88
VDD_CORE85
VDD_CORE84
VDD_CORE91
VDD_CORE92
VDD_CORE93
VDD_CORE90
VDD_CORE89
VDD_CORE94
VDD_CORE96
VDD_CORE97
VDD_CORE98
VDD_CORE95
VDD_CORE99
VDD_CORE101
VDD_CORE102
VDD_CORE100
VDD_CORE104
VDD_CORE106
VDD_CORE107
VDD_CORE108
VDD_CORE109
VDD_CORE105
VDD_CORE111
VDD_CORE112
VDD_CORE113
VDD_CORE114
VDD_CORE110
VDD_CORE117
VDD_CORE118
VDD_CORE119
VDD_CORE116
VDD_CORE115
VDD_CORE122
VDD_CORE123
VDD_CORE124
VDD_CORE121
VDD_CORE120
VDD_CORE125
VDD_CORE126
VDD_CORE127
VDD_CORE128
VDD_CORE129
VDD_CORE130
VDD_CORE131
VDD_CORE132
VDD_CORE133
VDD_CORE134
VDD_CORE135 GPU VERSION 57
VDD_MEM105
VDD_MEM104
VDD_MEM103
VDD_MEM102
VDD_MEM108
VDD_MEM107
VDD_MEM106
VDD_MEM99
VDD_MEM100
VDD_MEM101
VDD_MEM98
VDD_MEM97
VDD_MEM94
VDD_MEM95
VDD_MEM96
VDD_MEM93
VDD_MEM84
VDD_MEM85
VDD_MEM86
VDD_MEM79
VDD_MEM80
VDD_MEM81
VDD_MEM78
VDD_MEM77
VDD_MEM74
VDD_MEM75
VDD_MEM76
VDD_MEM73
VDD_MEM72
VDD_MEM71
VDD_MEM68
VDD_MEM69
VDD_MEM70
VDD_MEM67
VDD_MEM66
VDD_MEM63
VDD_MEM64
VDD_MEM65
VDD_MEM62
VDD_MEM61
VDD_MEM58
VDD_MEM59
VDD_MEM60
VDD_MEM57
VDD_MEM56
VDD_MEM82
VDD_MEM83
VDD_MEM51
VDD_MEM41
VDD_MEM38
VDD_MEM39
VDD_MEM40
VDD_MEM37
VDD_MEM36
VDD_MEM33
VDD_MEM34
VDD_MEM35
VDD_MEM32
VDD_MEM31
VDD_MEM28
VDD_MEM29
VDD_MEM30
VDD_MEM26
VDD_MEM23
VDD_MEM25
VDD_MEM22
VDD_MEM18
VDD_MEM19
VDD_MEM20
VDD_MEM17
VDD_MEM16
VDD_MEM15
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM11
VDD_MEM10
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM6
VDD_MEM5
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM1
VDD_MEM0
VDD_MEM21
VDD_MEM24
VDD_MEM87
VDD_MEM88
VDD_MEM89
VDD_MEM90
VDD_MEM91
VDD_MEM92
VDD_MEM27
VDD_MEM111
VDD_MEM110
VDD_MEM109
VDD_MEM42
VDD_MEM46
VDD_MEM47
VDD_MEM48
VDD_MEM49
VDD_MEM50
VDD_MEM55
VDD_MEM54
VDD_MEM53
VDD_MEM52
VDD_MEM43
VDD_MEM44
VDD_MEM45
GPU VERSION 51
VSS189
VSS188
VSS186
VSS259
VSS260
VSS257
VSS258
VSS254
VSS255
VSS256
VSS252
VSS253
VSS249
VSS250
VSS251
VSS248
VSS247
VSS246
VSS244
VSS241
VSS238
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS226
VSS227
VSS224
VSS225
VSS223
VSS221
VSS222
VSS219
VSS220
VSS218
VSS216
VSS217
VSS213
VSS214
VSS215
VSS211
VSS212
VSS208
VSS209
VSS210
VSS207
VSS206
VSS205
VSS203
VSS204
VSS202
VSS201
VSS200
VSS199
VSS198
VSS196
VSS197
VSS236
VSS237
VSS239
VSS240
VSS242
VSS243
VSS245
VSS187
VSS184
VSS183
VSS182
VSS181
VSS179
VSS180
VSS178
VSS177
VSS176
VSS175
VSS174
VSS172
VSS173
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS159
VSS160
VSS158
VSS156
VSS157
VSS154
VSS155
VSS153
VSS151
VSS152
VSS148
VSS149
VSS150
VSS146
VSS147
VSS143
VSS144
VSS145
VSS142
VSS141
VSS140
VSS138
VSS139
VSS137
VSS136
VSS135
VSS134
VSS133
VSS131
VSS132
VSS162
VSS161
VSS185
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
[PAGE_TITLE=GPU, DECOUPLING]
GPU, DECOUPLING
K718/73XENON_RETAILWed Aug 24 09:27:12 2005
2 1
C6E2
2 1
C6E1
2 1
C6R47
2 1
C5R20
2 1
C5D2
2 1
C5D5
2 1
C5D6
2 1
C5D4
2 1
C5D3
2 1
C4R69
2 1
C4R67
21
C4R49
21
C4R39
21
C4R18
21
C4R52
21
C4T3
21
C4T1
21
C4T16
21
C4R42
21
C4T11
21
C4R57
21
C4T9
21
C4T6
21
C4R59
21
C4R34
21
C4R36
21
C4T20
21
C4R47
21
C4R55
21
C4T2
21
C4R63
21
C4R54
21
C4R56
21
C4R43
21
C4R62
21
C4T15
21
C4T10
21
C4R58
21
C4R35
21
C4T8
21
C4R46
21
C4T21
21
C4T5
21
C4T18
21
C4T19
21
C4T24
21
C4T4
21
C4T25
21
C4T26
21
C4R44
21
C4T23
21
C4R41
21
C4R53
21
C4R37
21
C4R17
21
C4R21
21
C4R22
21
C4R20
21
C4R11
21
C4R16
21
C4R28
21
C5R17
21
C4R13
21
C4R14
21
C5R14
21
C4R9
21
C5R8
21
C4R40
21
C4R24
21
C5R12
2 1
C5R10
2 1
C4T17
2 1
C4R29
2 1
C5R4
2 1
C5R5
2 1
C4R30
2 1
C5R6
2 1
C5R11
2 1
C5R3
2 1
C5R1
21
C5R2
21
C5R16
21
C5R9
10%
402
X5R
6.3V
.1UF
X5R
10%
6.3V
X5R
.1UF
6.3V
10% 10%.1UF
X5R
402
4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
4.7UF 10%
6.3V
X5R
805
4.7UF 10%
6.3V
X5R
805
10%
.1UF
4.7UF 10%
6.3V
X5R
805
4.7UF 10%
6.3VX5R
805
4.7UF 10%
6.3V
X5R
805
4.7UF 10%
6.3V
805
6.3V
10%
X5R
805
4.7UF 10%
6.3V
X5R
805
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
805
X5R
6.3V
10%4.7UF
V_GPUCORE
402
402
.1UF
6.3V
10%.1UF
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
6.3V
.1UF 10%
X5R
6.3V
402
.1UF 10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
6.3V
.1UF 10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
6.3V
.1UF
402
10%
X5R
.1UF
402
6.3V
10%
X5R
402
10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
6.3V
X5R
6.3V
.1UF
402
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
.1UF
6.3V
402
10%
X5R
402
.1UF
.1UF
402
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
6.3V
402
.1UF 10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
6.3V
X5R
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
.1UF
402
6.3V
10%
X5R
402
6.3V
.1UF 10%
X5R
.1UF
6.3V
402
10%
X5R
402
.1UF
6.3V
10%
X5R
402
.1UF
6.3V
10%
X5R
402
6.3V
.1UF 10%
X5R
.1UF
6.3V
402
10%
X5R
402
.1UF
6.3V
X5R
402
6.3V
X5R
10%
V_GPUCORE
402
6.3V
.1UF 10%
X5R
XENON_FABK
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
[PAGE_TITLE=DUAL ETHERNET PHY] K719/73XENON_RETAIL
4639
19
39 19 44
19
39 44
39 44
39 44
39 44
39 44
39 44
3339
3936
3936
3936
3936
3936
3936
3936
3639
3639
3639
3639
3639
3936
3936
3639
3639
19
391944
3936
Wed Aug 24 09:27:13 2005
2
1 C1N14
2
1
R1B12
2
1 C1N6
1
DB1N1
2
1
28
27
26
25
23
24 3
4
15
16
17
18
20
21
19
10
32
31
6
5
8
22
9
13
14
12
33
30
29
7
11
U1B1
2
1
R1N8
2
1 C1N7
2 1
FB1N1
2
1 C1N8
XENON_FABK
.1UF
10%
402
EMPTY
6.3V
1%
EMPTY
1.27K
402
EMPTY
805
20%
10UF
6.3V
0.1DCR
603
EMPTY60
0.5A
10UF
10%
6.3V
EMPTY
1206
V_1P8
ENET_CLK EMPTY
X801554-001 LCC32
EMPTY
.1UF
10%
6.3V
402
TP
402
5%
EMPTY
4.7K
ENET_AVDD
V_ENET
E
N
E
T_
R
D
A
C
ENET_AVDD
ENET_LINK_N
ENET_ACT_N
ENET_RX_DP
ENET_RX_DN
ENET_TX_DP
ENET_TX_DN
ENET_REF_CLK2_OUT
ENET_RST_N
MII_RX_CLK
MII_RXER
MII_RXDV
MII_RXD3
MII_RXD2
MII_RXD1
MII_TX_CLK
MII_TXEN
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_COL
MII_CRS
MII_MDC_CLK_OUT
MII_MDIO
ENET_AVDD
V_ENET
MII_RXD0
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
BI
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
BCM5241
REGVDDOUT
REGVDDIN
MDIO
TXD0
TXD1
RXD0/PHYAD0
RXD2/F100
RXD1/ANEN
RXD3/ISOLATE
RX_ER/TEST1
RX_DV/TEST0
RXC
RESET_N
XTALO2
RDN
RDP
TDN
TDP
ACT#
LINK#
AVDD
OVDD1
OVDD2
TXC
TX_EN
TXD3
TXD2
MDC_CLK_OUT
COL/ENERGYDET
CRS/LOWPWR0
RDAC
GND
XTALI2
OUT
OUT
OUT
OUT
MEMORY PARTITION A, TOP
CHIP SELECT = 0, MIRROR FUNCTION = 0
MEMORY A, TOP, DECOUPLING
[PAGE_TITLE=MEMORY PARTITION A, TOP]
PARTITION A DECOUPLING
K720/73XENON_RETAIL
1421
1421
1421
14 21
14 21
14 21
14 21
14 21
14 21
20 21
1321222324252627
14
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
1221222324252627
2021
21
14
1421
1421
1421
14
12222426
14 21
14 21
14 21
14 21
21 14
14 21
14 21
14 21
21 14
14 21
14 21
14 21
14 21
14 21
14 21
14 21
21 14
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
21 14
14 21
14 21
14 21
14 21
Wed Aug 24 09:27:13 2005
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
J12
J1
V3
L12
L1
G12
G1
A10
V10
A3
V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1
K12
K1
V2
M12
M1
V11
F12
F1
A11
A2
J3
J2
U4F1
A4
H9
P2
P11
D11
D2
H1
H12
V4
V9
P3
P10
D10
D3
H3
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F9
J11
J10
H4
F4
H10
G9
G4
M9
K11
L9
K10
H11
K9
M4
K3
L4
K2
H2
K4
U4F1
2
1
C4F12 C3F3 C4F9 C4F11 C4F7 C3F1 C4F1 C4F6 C4F3
2
1
R3F1
2
1
R4F3
2
1
R4F4
2
1
R4U5
2
1
R4U4
C4U9
V_MEM
V_MEM
10UF
10%
6.3V
X5R
V_MEM
402
60.4
1%
CH
60.4
402
1%
CH
V_MEM
243
CH
402
1%
.1UF
402
X5R
6.3V
10%
10
11
9
7
402
1%
549
CH
8
6
5
4
3
0
1
2
1
1%
CH
1.27K
402
2
0
MA_BA<2..0>
V_MEM
MA_A<11..0>
MA_CKE
MA_DQ19
MA_WDQS2
MA_DQ9
MA_DQ8
MA_DM1
MA_DQ7
MEM_A_VREF1
MEM_RST
MA_CLK0_DN
MA_DQ23
MA_DM3
MA_DQ21
MA_DQ16
MA_WDQS3
MA_DQ24
MA_DQ13
MA_DQ20
MEM_SCAN_EN
MEM_A_VREF1
MEM_A_VREF0
MA_CLK0_DP
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS0_N
MEM_SCAN_TOP_EN
MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_RDQS3
MA_DQ22
MA_DQ18
MA_DQ17
MA_RDQS2
MA_DM2
MA_DQ15
MA_DQ14
MA_DQ12
MA_DQ11
MA_DQ10
MA_WDQS1
MA_RDQS1
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0
MA_ZQ_TOP
MA_DQ25
MA_DQ27
MA_DQ26
1206
X5R
6.3V
10%
402
.22UF
X5R
402
10%
6.3V
.22UF
6.3V
10%
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
X5R
402
10%
6.3V
X5R
402
.22UF
X5R
6.3V
10%
402
.22UF
10%
6.3V
X5R
402
.22UF
6.3V
10%
.22UF
XENON_FABK
IC
X801995-006
IC
X801995-006
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
OUT
IN
IN
BI
IN
BI
BI
BI
BI
BI GDDR136
MF=0VDDQ<21>
VSSQ<18>VDDQ<18>
VDDQ<11>
VDDQ<16> VSSQ<16>
VSSQ<19>
NC<0>
NC<1>
VSS<0>
VSS<1>
VSS<2>
VSS<3>
VSS<4>
VSS<5>
VSS<6>
VSS<7>
VSSQ<0>
VSSQ<1>
VSSQ<2>
VSSQ<3>
VSSQ<4>
VSSQ<5>
VSSQ<6>
VSSQ<7>
VSSQ<8>
VSSQ<9>
VSSQ<10>
VSSQ<11>
VSSQ<12>
VSSQ<13>
VSSQ<14>
VSSQ<15>
VSSQ<17>
VSSA<0>
VSSA<1>
VDDA<0>
VDDA<1>
VDD<0>
VDD<1>
VDD<2>
VDD<3>
VDD<4>
VDD<5>
VDD<6>
VDD<7>
VDDQ<0>
VDDQ<1>
VDDQ<2>
VDDQ<3>
VDDQ<4>
VDDQ<5>
VDDQ<6>
VDDQ<7>
VDDQ<8>
VDDQ<9>
VDDQ<10>
VDDQ<12>
VDDQ<13>
VDDQ<14>
VDDQ<15>
VDDQ<17>
VDDQ<19>
VDDQ<20>
GDDR136
MF=0
DQ26
DQ27
DQ25
ZQ
DM0
RDQS0
WDQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
RDQS1
WDQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2
RDQS2
WDQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
RDQS3
WDQS3
DQ24
DQ28
DQ29
DQ30
DQ31
MF
CS_N/CAS_N
RAS_N/BA2
CAS_N/CS_N
WE_N/CKE
CKE/WE_N
BA0/BA1
BA1/BA0
BA2/RAS_N
A0/A4
A1/A5
A2/A6
A3/A9
A4/A0
A5/A1
A6/A2
A7/A11
A8/A10
A9/A3
A10/A8
A11/A7
RESET
CLK_DN
CLK_DP
VREF0
VREF1
SCAN_EN
BI
IN
IN
OUT
BI
MEMORY PARTITION A, BOTTOM
MEMORY A, BOTTOM, DECOUPLING
CHIP SELECT = 1, MIRROR FUNCTION = 1
[PAGE_TITLE=MEMORY PARITION A, BOTTOM] K721/73XENON_RETAIL
1420
1420
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
20 14
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
20 14
14 20
14 20
14 20
14 20
14 20
20 14
14 20
20 14
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
14 20
1320222324
252627
14
20 21
14
20
2120
12202223242526
27
14
14 20
14 20
14 20
14 20
14 20
12232527
1420
1420
1420
1420
Wed Aug 24 09:27:14 2005
2
1
R4F2 C4F2
2
1
R4F1
C3U2 C4U8 C4U11 C4U6
A4
H9
P2
P11
D11
D2
H1
H12
V4
V9
P3
P10
D10
D3
H3
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F9
J11
J10
H4
F4
H10
G9
G4
M9
K11
L9
K10
H11
K9
M4
K3
L4
K2
H2
K4
U4U1
C3U1 C4U1 C4U5 C4U2
2
1
R3U1
2
1
R4U2
2
1
R4U3
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
J12
J1
V3
L12
L1
G12
G1
A10
V10
A3
V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1
K12
K1
V2
M12
M1
V11
F12
F1
A11
A2
J3
J2
U4U1
V_MEM
V_MEM549
CH
1%
402
X5R
402
6.3V
10%
.1UF1.27K
1%
CH
402
60.4
402
CH
1%
V_MEM
60.4
1%
CH
402
402
243
CH
1%
11
10
9
7
8
6
4
5
2
3
1
0
2
1
0
MA_BA<2..0>
V_MEM
MA_A<11..0>
MA_DQ12
MA_DQ1
MA_DQ0
MA_WDQS0
MA_DM0
MA_DQ14
MA_DQ11
MA_DQ10
MA_DM3
MA_RDQS3
MA_WDQS3
MA_DQ24
MA_DQ25
MA_DQ9
MA_DQ8
MA_DM1
MA_DQ15
MA_DQ30
MA_RDQS0
MA_DQ5
MA_WDQS2
MA_DQ17
MA_DQ19
MA_WDQS1
MA_RDQS1
MA_ZQ_BOT
MA_DQ4
MA_RDQS2
MA_DQ22
MA_DQ13
MA_DQ31
MA_DQ18
MA_DQ7
MA_DQ3
MA_DQ23
MA_DQ20
MA_DQ2
MA_DQ6
MA_DQ29
MA_DQ21
MEM_RST
MA_CLK1_DN
MEM_A_VREF0
MA_CS1_N
MEM_A_VREF1
MEM_A_VREF0
MEM_SCAN_EN
MA_CLK1_DP
MA_DQ28
MA_DQ27
MA_DQ26
MA_DM2
MA_DQ16
MEM_SCAN_BOT_EN
MA_RAS_N
MA_CAS_N
MA_WE_N
MA_CKE
10%
X5R
6.3V
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
XENON_FABK
IC
X801995-006
IC
X801995-006
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GDDR136
MF=1
DQ28
ZQ
DM0
RDQS0
WDQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2
RDQS2
WDQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
RDQS3
WDQS3
DQ24
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
MF
A6/A2
A9/A3
A0/A4
A1/A5
A2/A6
A11/A7
A10/A8
A3/A9
A8/A10
A7/A11
RESET
CLK_DN
CLK_DP
RDQS1
WDQS1
VREF0
VREF1
SCAN_EN
CAS_N/CS_N
BA2/RAS_N
CS_N/CAS_N
CKE/WE_N
WE_N/CKE
BA1/BA0
BA0/BA1
RAS_N/BA2
A4/A0
A5/A1
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
OUT
IN
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
GDDR136
MF=1VDDQ<21>
VSSQ<19>
VDDQ<20>
VDDQ<19>
VDDQ<11>
VDDQ<12>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
NC<0>
NC<1>
VSS<0>
VSS<1>
VSS<2>
VSS<3>
VSS<4>
VSS<5>
VSS<6>
VSS<7>
VSSQ<0>
VSSQ<1>
VSSQ<2>
VSSQ<3>
VSSQ<4>
VSSQ<5>
VSSQ<6>
VSSQ<7>
VSSQ<8>
VSSQ<9>
VSSQ<10>
VSSQ<11>
VSSQ<12>
VSSQ<13>
VSSQ<14>
VSSQ<15>
VSSQ<16>
VSSQ<17>
VSSQ<18>
VDD<3>
VDD<4>
VDD<5>
VDD<6>
VDD<7>
VDDQ<0>
VDDQ<1>
VDDQ<2>
VDDQ<3>
VDDQ<4>
VDDQ<5>
VDDQ<13>
VDDQ<14>
VDDQ<15>
VDDQ<16>
VDDQ<17>
VDDQ<18>
VSSA<0>
VSSA<1>
VDDA<0>
VDDA<1>
VDD<0>
VDD<1>
VDD<2>
BI
BI
BI
BI
BI
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
OUT
IN
BI
CHIP SELECT = 0, MIRROR FUNCTION = 0
MEMORY PARTITION B, TOP
MEMORY B, TOP, DECOUPLING
PARTITION B DECOUPLING
[PAGE_TITLE=MEMORY PARITION B, TOP] K722/73XENON_RETAIL
1423
1423
22 23
14 23
14 23
14 23
23 14
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
23 14
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
23 14
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
14 23
23 14
14 23
14 23
14 23
14 23
12202426
14
1423
1423
1423
1423
132021232425
2627
14
23
2223
12202123242526
27
14
14 23
14 23
14 23
Wed Aug 24 09:27:14 2005
2
1 C5F6
C4F10 C5F5 C4F8
A4
H9
P2
P11
D11
D2
H1
H12
V4
V9
P3
P10
D10
D3
H3
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F9
J11
J10
H4
F4
H10
G9
G4
M9
K11
L9
K10
H11
K9
M4
K3
L4
K2
H2
K4
U5F1
C4F5 C4F4 C5F2 C5F3 C5F4
2
1
R4F5
2
1
R5F3
2
1
R5F4
2
1
R5U3 C5U5
2
1
R5U4
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
J12
J1
V3
L12
L1
G12
G1
A10
V10
A3
V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1
K12
K1
V2
M12
M1
V11
F12
F1
A11
A2
J3
J2
U5F1
V_MEM
V_MEM
X5R
6.3V
10%
1206
10UF
V_MEM
402
1%
60.4
CH
402
60.4
CH
1%
V_MEM
402
CH
1%
243
549
CH
1%
402
11
10
8
9
X5R
10%
402
6.3V
.1UF
6
7
5
3
4
2
1
0
2
CH
1%
402
1.27K
1
0
MB_BA<2..0>
V_MEM
MB_A<11..0>
MEM_B_VREF1
MB_DQ27
MB_DQ25
MB_ZQ_TOP
MB_DM0
MB_RDQS0
MB_WDQS0
MB_DQ0
MB_DQ1
MB_DQ2
MB_DQ3
MB_DQ4
MB_DQ5
MB_DQ6
MB_DQ7
MB_DM1
MB_RDQS1
MB_WDQS1
MB_DQ8
MB_DQ9
MB_DQ10
MB_DQ11
MB_DQ12
MB_DQ13
MB_DQ14
MB_DQ15
MB_DM2
MB_RDQS2
MB_WDQS2
MB_DQ16
MB_DQ17
MB_DQ18
MB_DQ19
MB_DQ20
MB_DQ21
MB_DQ22
MB_DQ23
MB_DM3
MB_RDQS3
MB_DQ28
MB_DQ29
MB_DQ30
MB_DQ31
MEM_SCAN_TOP_EN
MB_CS0_N
MB_RAS_N
MB_CAS_N
MB_WE_N
MB_CKE
MEM_RST
MB_CLK0_DN
MEM_B_VREF0
MEM_B_VREF1
MEM_SCAN_EN
MB_CLK0_DP
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
6.3V
X5R
402
.22UF
402
10%
6.3V
X5R
.22UF
10%
402
6.3V
X5R
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
402
.22UF
X5R
10%
XENON_FABK
MB_DQ26
MB_DQ24
MB_WDQS3
IC
X801995-006
IC
X801995-006
DRAWING
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GDDR136
MF=0
DQ26
DQ27
DQ25
ZQ
DM0
RDQS0
WDQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1
RDQS1
WDQS1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM2
RDQS2
WDQS2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM3
RDQS3
WDQS3
DQ24
DQ28
DQ29
DQ30
DQ31
MF
CS_N/CAS_N
RAS_N/BA2
CAS_N/CS_N
WE_N/CKE
CKE/WE_N
BA0/BA1
BA1/BA0
BA2/RAS_N
A0/A4
A1/A5
A2/A6
A3/A9
A4/A0
A5/A1
A6/A2
A7/A11
A8/A10
A9/A3
A10/A8
A11/A7
RESET
CLK_DN
CLK_DP
VREF0
VREF1
SCAN_EN
IN
OUT
BI
IN
BI
BI
BI
BI
BI
BI
BI
IN
OUT
BI
BI
IN
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
BI
GDDR136
MF=1VDDQ<21>
VSSQ<19>
VDDQ<20>
VDDQ<19>
VDDQ<11>
VDDQ<12>
VDDQ<10>
VDDQ<9>
VDDQ<8>
VDDQ<7>
VDDQ<6>
NC<0>
NC<1>
VSS<0>
VSS<1>
VSS<2>
VSS<3>
VSS<4>
VSS<5>
VSS<6>
VSS<7>
VSSQ<0>
VSSQ<1>
VSSQ<2>
VSSQ<3>
VSSQ<4>
VSSQ<5>
VSSQ<6>
VSSQ<7>
VSSQ<8>
VSSQ<9>
VSSQ<10>
VSSQ<11>
VSSQ<12>
VSSQ<13>
VSSQ<14>
VSSQ<15>
VSSQ<16>
VSSQ<17>
VSSQ<18>
VDD<3>
VDD<4>
VDD<5>
VDD<6>
VDD<7>
VDDQ<0>
VDDQ<1>
VDDQ<2>
VDDQ<3>
VDDQ<4>
VDDQ<5>
VDDQ<13>
VDDQ<14>
VDDQ<15>
VDDQ<16>
VDDQ<17>
VDDQ<18>
VSSA<0>
VSSA<1>
VDDA<0>
VDDA<1>
VDD<0>
VDD<1>
VDD<2>
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
IN
BI
BI
BI
BI
OUT
BI
IN
IN
BI
MEMORY B, BOTTOM, DECOUPLING
[PAGE_TITLE=MEMORY PARTITION B, BOTTOM]
CHIP SELECT = 1, MIRROR FUNCTION = 1
MEMORY PARTITION B, BOTTOM
K723/73XENON_RETAIL
1422
1422
14 22
14 22
1422
1422
1422
1422
14
12202122242526
27
2322
22
14 22
22 14
14
14
12212527
14 22
14 22
14 22
14 22
14 22
14 22
14 22
22 14
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
14 22
22 23
22 14
14 22
1320212224
252627
14 22
14 22
22 14
Wed Aug 24 09:27:15 2005
2
1
R5F2 C5F1
2
1
R5F1
C4U10 C5U4 C4U7
A4
H9
P2
P11
D11
D2
H1
H12
V4
V9
P3
P10
D10
D3
H3
A9
B10
B11
G3
F2
F3
E2
T3
T2
C3
R3
R2
M3
N2
L3
M2
T10
T11
R10
R11
C2
M10
N11
L10
M11
G10
F11
F10
E11
C10
C11
B3
B2
N3
N10
E10
E3
F9
J11
J10
H4
F4
H10
G9
G4
M9
K11
L9
K10
H11
K9
M4
K3
L4
K2
H2
K4
U5U1
C4U4 C4U3 C5U1 C5U2 C5U3
2
1
R4U1
2
1
R5U2
2
1
R5U1
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
J12
J1
V3
L12
L1
G12
G1
A10
V10
A3
V1
R12
R9
R4
R1
N12
N9
V12
N4
N1
J9
J4
E12
E9
E4
E1
C12
C9
C4
C1
A12
A1
K12
K1
V2
M12
M1
V11
F12
F1
A11
A2
J3
J2
U5U1
V_MEM
V_MEM
1%
549
CH
402
402
X5R
10%
.1UF
6.3V
1.27K
402
1%
CH
V_MEM
402
CH
1%
60.4
402
CH
1%
60.4
1%
CH
402
243
11
10
9
8
7
6
5
4
3
2
0
1
2
1
0
MB_BA<2..0>
V_MEM
MB_A<11..0> MB_DQ31
MB_DM2
MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS1_N
MEM_SCAN_EN
MEM_B_VREF0
MEM_B_VREF1
MB_WDQS0
MB_RDQS0
MB_CLK1_DP
MB_CLK1_DN
MEM_SCAN_BOT_EN
MB_DQ22
MB_DQ21
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_DM3
MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_DM0
MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ9
MB_DQ8
MB_WDQS1
MB_DM1
MB_ZQ_BOT
MEM_B_VREF0
MB_RDQS1
MB_DQ10
MEM_RST
MB_DQ23
MB_DQ20
10%
6.3V
X5R
402
.22UF
10%
X5R
402
6.3V
.22UF
10%
402
10%
6.3V
X5R
.22UF
10%
6.3V
402
.22UF
X5R
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
.22UF
402
X5R
6.3V
.22UF
XENON_FABK
MB_RDQS3
IC
X801995-006
IC
X801995-006
PAGEMICROSOFT REV
CONFIDENTIAL
PROJECT NAME
DRAWING
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GDDR136
MF=1
DQ28
ZQ
DM0
RDQS0
WDQS0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM1