Artigo_1D_PWM

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008 3239
Simple Unified Approach to Develop a Time-Domain
Modulation Strategy for Single-Phase
Multilevel Converters
Jose I. Leon, Member, IEEE, Ramon Portillo, Student Member, IEEE, Sergio Vazquez, Student Member, IEEE,
Jose J. Padilla, Leopoldo G. Franquelo, Fellow, IEEE, and Juan M. Carrasco, Member, IEEE
Abstract—Single-phase power converters are widely used in
power applications as photovoltaics and fuel-cell power condition-
ers. In addition, multilevel converters are a well-known solution in
order to achieve high-quality output waveforms in power systems.
In this paper, a time-domain duty-cycle computation technique
for single-phase multilevel converters named 1DM is presented.
The proposed technique is based on geometrical calculations with
outstanding simplicity and generality. The proposed modulation
technique can be easily applied to any multilevel converter topol-
ogy carrying out the necessary calculations. The most common
multilevel converter topologies have been studied in this paper
as examples to introduce the proposed modulation strategy. Any
other multilevel converter topology could be studied, and the
corresponding 1DM could be easily developed. In addition, the
well-known optimized voltage balance strategy for voltage capaci-
tor control using the redundant switching states of the system is
applied working with the proposed 1DM method, showing that
both techniques are compatible. Experimental and simulation
results for several single-phase multilevel converters are shown to
validate the proposed modulation technique.
Index Terms—Modulation, multilevel systems, power
conversion.
I. INTRODUCTION
POWER CONVERSION is, nowadays, a deeply studiedtopic by academies and industries due to the power de-
mand and the integration of power sources in the electrical grid
or in stand-alone applications. Mainly, these power converters
are three-phase systems; however, several applications, such
as photovoltaics, present a single-phase configuration [1], [2].
Photovoltaic systems are renewable energy sources, where the
solar energy is transformed to dc power that has to be converted
into ac, and usually, this dc/ac conversion is done thanks to
the use of a single-phase power converter. Therefore, different
single-phase converter topologies and control strategies have
been used in photovoltaics or other applications, improving
factors such as voltage regulation or maximum power point
tracking [3], [4]. In recent years, multilevel converters have
Manuscript received February 27, 2008; revised June 11, 2008. First pub-
lished July 9, 2008; last published August 29, 2008 (projected). This work
was supported by the Spanish Science and Education Ministry under Project
TEC2006-03863.
The authors are with the Department of Electronic Engineering, Escuela
Superior de Ingenieros, University of Seville, 41092 Seville, Spain (e-mail:
jileon@gte.esi.us.es).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2008.928141
been applied to medium- and high-power systems thanks to
their advantages when working with higher power ratings and
energy quality improvements [5]–[9]. This paper is devoted
to multilevel single-phase power converters and, specifically,
to their modulation techniques. In [10] and [11], interesting
surveys of the most common single-phase multilevel converters
are presented.
Pulsewidth modulation (PWM) and space-vector modulation
(SVM) are the most used high-frequency modulation tech-
niques. PWM is based on the generation of the modulated
signal, comparing the reference signal with different triangular
carriers (N − 1 carriers for an N -level converter) [12]. SVM
takes advantage of the representation of the possible output
voltages of the power converter and generates the reference
voltage (represented in a vectorial diagram) by a linear com-
bination of the possible states of the converter using the nearest
three vectors method for three-phase systems [13]–[15] and,
in general, the M + 1 nearest space vectors for the M -phase
systems [16].
This is the follow-up paper to our presentation at the ISIE07
conference [17] and ICIT08 [18] including a study of the most
common multilevel converter topologies and a complete revi-
sion optimizing the flow diagram of the proposed modulation
technique to minimize the computational cost of the modulation
algorithm. The proposed modulation strategy is called 1DM and
is a duty-cycle computation between the two nearest voltage
levels of the power converter in order to generate the reference
voltage with a minimum distortion.
II. PROPOSED MODULATION TECHNIQUE FOR
SINGLE-PHASE MULTILEVEL CONVERTERS
The control region of a single-phase power converter can be
represented only using one component calculating the output
voltage with respect to a reference point (Vphase − 0) for every
possible switching state (also called switching state) in each
phase [17], [18]. Therefore, the proposed modulation technique
is called 1DM. It must be noticed that the reference point
depends on the multilevel converter topology. The proposed
1DM technique independently follows the same steps of the
single-phase multilevel converter topology. These steps are the
following.
1) Determination of the 1-D control region of the single-
phase multilevel converter setting the position of the
possible switching states on the control region.
0278-0046/$25.00 © 2008 IEEE
3240 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
2) Normalization of the reference output voltage. This
normalization depends on the specific power converter
topology.
3) Search for the normalized reference output voltage on the
1-D control region. The result of this step is the determi-
nation of the switching sequence and the corresponding
duty cycles of the two nearest switching states to the
normalized reference voltage.
Following these steps, any conventional or hybrid multilevel
converter topology can be studied, and its corresponding par-
ticularization of the 1DM method can be easily developed. As
examples, the most common multilevel converter topologies,
which are diode-clamped converters (DCCs), flying capacitor
converters (FCCs), and cascaded H-bridge converters (CHBs),
have been studied.
A. 1DM Technique for Multilevel DCCs
For single-phase DCCs, the reference point is the middle
point of the dc link. The possible switching states of the power
converter are labeled using a couple of factors SASB denoting
the state of phases A and B, respectively. The phase state
is equal to zero if the lowest possible output phase voltage
is achieved. For a single-phase power converter, each phase
achieves N levels, and the factor SP defined for phase P can
take values from 0 to N − 1. For instance, in the five-level
single-phase DCC (see Fig. 1), each phase can obtain three
different output voltage levels (−E, 0, E), and therefore, SA
and SB can take values from zero to two.
Using the output line-to-line voltage (VAB) as the control
component of the modulation algorithm, the control region of
the single-phase converter can be reduced to a 1-D representa-
tion [17]–[19]. To illustrate, the control region of a single-phase
five-level DCC, where VC1 = VC2 = E, is shown in Fig. 2.
Some redundant switching states appear in the system because
the same output voltage VAB can be achieved using different
switching states. This redundancy is shown in Fig. 2 using
shadowed text for the redundant switching states. Multilevel
converters are known by the characteristic of the redundancies
which can be used for capacitor voltage balancing, switching
frequency reduction, common mode voltage elimination, un-
der fault operation, etc. Using the proposed way to represent
the control region, the switching states’ redundancy is clearly
shown. This fact is important because previous works related
to time-domain duty-cycle calculationsdo not consider this in-
formation directly. From Fig. 2, it is clear that in the multilevel
single-phase case, the modulation method uses the two nearest
switching states to the reference one to generate the switching
sequence. These nearest two switching states are, in fact, the
nearest voltage levels of the power converter.
Thus, the proposed 1DM method has to determine the nearest
two switching states and their corresponding duty cycles. As in
[20]–[24], these calculations are done thanks to a geometrical
search of the reference voltage minimizing the computational
cost of the algorithm. The flow diagram of the proposed 1DM
technique for a five-level single-phase converter is shown in
Fig. 3, where the operator floor(x) rounds x to the nearest
Fig. 1. (a) Five-level single-phase DCC. (b) Five-level single-phase FCC.
(c) Two-cell single-phase CHB.
Fig. 2. 1-D control region for a five-level single-phase DCC.
integer toward minus infinity. The proposed modulation method
determines the switching sequence, and among the possible
redundant switching states, the minimum voltage levels are
chosen. The proposed modulation strategy is based on an
iterative geometrical search of the position of the normalized
reference voltage a determined using the following expression:
a =
VABref
E
. (1)
LEON et al.: APPROACH TO DEVELOP MODULATION STRATEGY FOR SINGLE-PHASE MULTILEVEL CONVERTERS 3241
Fig. 3. Proposed 1DM algorithm for a single-phase N -level DCC.
The calculation of the corresponding duty cycles is done,
generating the reference voltage VABref as a linear combination
of the two nearest output voltage levels of the 1-D control
region.
The switching sequence is formed by two switching states
stateA1–stateB1 and stateA2–stateB2, with duty cycles t1 and
t2, respectively. Factors stateA1 and stateA2 are the switching
states of phase A of the single-phase DCCs. Factors stateB1 and
stateB2 are the switching states of phase B of the single-phase
DCCs. The proposed 1DM algorithm represented in Fig. 3
is a generalized modulation algorithm that can be applied to
a single-phase DCCs with any number of levels. The search
for the nearest two switching states is done using geometrical
properties, and the same number of calculations is needed to
determine the switching sequence and the corresponding duty
cycles, independent of the number of levels of the converter.
Only a few simple calculations are needed, and the computa-
tional cost is very low.
The redundancy property present in the 1-D control region of
the DCCs is not taken into account in the proposed 1DM tech-
nique shown in Fig. 3. One possible redundant switching state
between the redundant ones is used. For instance, if the mod-
ulation algorithm determines that switching states 10 and 21
are present in the switching sequence, then by default, switch-
ing state 10 would be used. Thus, after determining the switch-
ing sequence and the duty cycles, an optimization strategy
can be used in order to improve other features of the power
converter as the number of commutations or the dc-link voltage
balance using the redundancy property [17].
B. 1DM Technique for Multilevel FCCs
For single-phase FCC, the reference point is also the virtual
middle point of the dc link. As in the DCC case, the possible
switching states of the power converter are labeled using a
couple of numbers SASB denoting the state of phases A and B,
respectively, where the phase state is equal to zero if the lowest
possible output phase voltage is achieved. This way, the 1-D
control region shown in Fig. 2 and the 1DM algorithm shown in
Fig. 3 are also valid for the five-level FCC if the flying capacitor
voltages VCA and VCB are equal to E volts. The only difference
lies in the generation of the control signals for the power
Fig. 4. 1-D control region for a five-level single-phase CHB with E volts in
each H-bridge.
Fig. 5. Flow diagram of the 1DM for the two-cell single-phase CHB assuming
voltage E in each H-bridge.
semiconductors to achieve each output phase state (VP0 for
phase P ) because it depends on the used multilevel converter
topology. For instance, to obtain phase state 1 in phase P
in a single-phase five-level converter (which means that the
phase voltage is equal to zero) of the DCC topology, power
semiconductors SWP2 and SWP3 have to be switched on.
On the other hand, if the five-level FCC is used, power semi-
conductors SWP1 and SWP3 or SWP2 and SWP4 have to be
switched on.
C. 1DM Technique for Multilevel CHBs
In order to introduce the 1-D control region for multilevel
CHB, the two-cell case shown in Fig. 4 is studied. The output
phase voltage VAB depends on the output voltage of each
H-bridge of the converter. Each H-bridge can obtain three
different output voltages, which are −VCi, 0, and VCi, defined
as H-bridge states 0, 1, and 2, respectively. Considering that the
phase voltage is composed of the sum of the H-bridge output
voltages, for the two-cell CHB case, five output voltages can be
achieved assuming that VC1 = VC2 = E. It is possible to repre-
sent the control region and their corresponding output voltages
for the two-cell CHB. The output phase voltage VAB is plotted
in the 1-D representation alongside the corresponding states
which produce them [17]. This is shown in Fig. 4, where the
control region for the two-cell CHB is represented. In this fig-
ure, state XY corresponds to the upper H-bridge having state X
and the lower H-bridge having state Y . The flow diagram of the
proposed 1DM technique for the five-level single-phase CHB
with E volts in each H-bridge is shown in Fig. 5. This method
determines the switching sequence, and among the possible
redundant switching states, the minimum voltage levels are
chosen. It must be noticed that the proposed 1DM is also
very simple and very low cost computationally. The switching
3242 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
Fig. 6. Control region of a three-cell single-phase CHB with a dc voltage ratio of 6 : 2 : 1 (VC1 = 2VC2 = 6VC3 = 6E).
sequence is formed by two switching states upper1–lower1 and
upper2–lower2, with duty cycles t1 and t2, respectively. Factors
upper1 and upper2 are the switching states of the upper cell of
the two-cell CHB. Factors lower1 and lower2 are the switching
states of the lower cell of the converter.
D. 1DM Technique for Multilevel Asymmetric Topologies
The proposed 1DM strategy can be adapted to be used in
multilevel converters where the dc voltages have been con-
figured in order to maximize the number of output voltage
levels. Asymmetric FCC topologies, where the flying capacitors
have different voltages compared with the conventional solution
shown in Fig. 1, have been presented [25]. On the other hand,
asymmetric CHBs, where the dc voltages of each cell are not
equal, are common solutions increasing the number of levels at
the expense of losing modularity [9]. Using these asymmetric
hybrid multilevel converter topologies, the quality of the output
waveforms is increased. However, the redundancy property,
which is very useful for controlling the voltages in the dc side, is
lost. The calculations carried out to develop the 1DM strategies
for conventional multilevel converters can be repeated, taking
into account the features of the applied asymmetric hybrid
topology. Any voltage in the flying capacitors or any other volt-
age ratio or number of H-bridges in the CHB can be considered.
The design of the 1DM for any hybrid or asymmetric multilevel
converter follows these steps:
1) determination of the output voltages for each possible
switching state of the converter;
2) 1-D control region representation;
3) design of the flow diagram carrying out a geometrical
search of the normalized reference voltage a.
An example of the 1-D control region for a three-cell single-
phase CHB with a dc voltage ratio of 6 : 2 : 1 (VC1 = 2VC2 =
6VC3 = 6E) is shown in Fig. 6. The flow diagram for the
determination of the switching sequence and the dutycycles
could be easily developed, making a geometrical search of the
normalized reference voltage a inside the control region. In
this case, each state XY Z corresponds to the upper H-bridge
having state X , the middle H-bridge having state Y , and the
lower H-bridge having state Z.
Another example has been studied, considering the FCC
shown in Fig. 1 where the flying capacitor voltages are VCA =
VCB = 2E/3. In this case, the number of output voltage levels
is seven, and the redundancy property is still present. The
flow diagram of the 1DM technique for this power converter
is shown in Fig. 7. The number of calculations is the same
compared with the 1DM shown in Fig. 3 for the conventional
FCCs. The definition of the position of the normalized reference
Fig. 7. Flow diagram of the 1DM for the FCC where the flying capacitor
voltages are VCA = VCB = 2E/3.
voltage a has been changed in order to minimize the necessary
calculations
a =
3VABref
2E
. (2)
Another example has been studied considering the two-cell
CHB shown in Fig. 1, where the dc voltage ratio of 3 : 1 (VC1 =
3VC2 = 3E) is applied. In this case, the reference voltage is in
the range −4E−4E, and therefore, the ai factor takes values
from the set (−4, −3, −2, −1, 0, 1, 2, 3). The flow diagram of
the 1DM technique for this power converter is shown in Fig. 8.
The number of calculations has increased compared with the
1DM flow diagram shown in Fig. 5 for the dc voltage ratio of
1 : 1; however, the algorithm is still very simple.
III. EXPERIMENTAL AND SIMULATION RESULTS
A. 1DM Technique Experimental Results
1) 1DM Technique Applied to DCCs and FCCs: The pro-
posed 1DM method has been experimentally tested using a
single-phase 50-kVA five-level DCC shown in [17], controlled
by a TMS320VC33 Texas Instruments digital signal processor
(DSP). It is considered a 50-Hz sinusoidal reference voltage
(Vref) modulation index m = 1, with the dc-link voltage (2E)
equal to 900 V, C1 = C2 = 3300 µF, and the switching fre-
quency equal to 5.6 kHz.
In Fig. 9, the output voltage VAB connecting a resistive load
R = 62 Ω is shown. It can be seen that the 1DM works perfectly
by generating the modulated signal. In this case, only the lower
switching states are used, and the redundancy property is not
taken into account. Two separate dc sources are in charge of
fixing the dc voltage of each part of the dc link (E = 450 V).
LEON et al.: APPROACH TO DEVELOP MODULATION STRATEGY FOR SINGLE-PHASE MULTILEVEL CONVERTERS 3243
Fig. 8. Flow diagram of the 1DM for the two-cell single-phase CHB assuming
a voltage ratio of 3 : 1, which means that VC1 = 3VC2 = 3E.
Fig. 9. Experimental results using the proposed 1DM for the single-phase
five-level DCC. Output voltage VAB (Math channel) using the proposed 1DM
technique. VA0 (channel 1) and VB0 (channel 2) are represented, and VAB is
calculated as VA0 − VB0.
2) 1DM Technique Applied To CHB: The proposed 1DM
method has been experimentally tested using a single-phase
5-kVA two-cell CHB, controlled by a TMS320VC33 Texas
Instruments DSP considering a 50-Hz sinusoidal reference volt-
age (Vref), modulation index m = 1, C1 = C2 = 2200 µF, and
the switching frequency equal to 5.6 kHz. In Fig. 10, the output
voltage VAB with no load is shown, considering different dc
Fig. 10. Experimental results using the proposed 1DM for the single-phase
two-cell CHB. Output voltage VAB using the proposed 1DM technique
(a) with a dc voltage ratio of 1 : 1 (VC1 = VC2 = 20 V) and (b) with a dc
voltage ratio of 3 : 1 (VC1 = 3VC2 = 60 V).
Fig. 11. Harmonic spectrum of the output voltage VAB using the proposed
1DM technique (a) with a dc voltage ratio of 1 : 1 (VC1 = VC2 = 20 V) and
(b) with a dc voltage ratio of 3 : 1 (VC1 = 3VC2 = 60 V).
voltage ratios. These dc voltage ratios are 1 : 1 (VC1 = VC2 =
20 V) and 3 : 1 (VC1 = 3VC2 = 60 V), and the corresponding
results are shown in Fig. 10(a) and (b), respectively. The
harmonic spectra of these voltages are, respectively, shown in
Fig. 11(a) and (b). It must be noticed that any other dc voltage
ratio can be studied and applied to the power converter. It can be
3244 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
TABLE I
OPTIMIZATION STRATEGY TO CHOOSE THE REDUNDANT SWITCHING
STATES IN ORDER TO MINIMIZE THE dc-LINK UNBALANCE FOR
A SINGLE-PHASE FIVE-LEVEL DCC
Fig. 12. Experimental results of the dc-link voltage balance using the
proposed 1DM technique under nonlinear load connection. (a) dc voltages
(in volts) VC1 and VC2. (b) Detail of the output current (in amperes).
TABLE II
dc VOLTAGE UNBALANCE CASES TO STUDY IN FCC
seen that the 1DM works perfectly by generating the modulated
signal. In this case, the lower switching states are also used, and
the redundancy property is not taken into account.
B. Voltage Balancing Control Method for Diode-Clamped
Single-Phase Multilevel Converters
As was presented in [26], [27], and, particularly, in [28]
for single-phase converters, the dc-link voltage balance can
be properly achieved using the redundancy properties of the
single-phase multilevel converter. These techniques use the
redundant states to control the dc voltage balance, and they
TABLE III
REDUNDANT SWITCHING STATES’ ELECTION IF THE PHASE CURRENT IS
POSITIVE DEPENDING ON THE INSTANTANEOUS dc VOLTAGE UNBALANCE
FOR THE SINGLE-PHASE HYBRID FCC (VCA = VCB = E)
TABLE IV
REDUNDANT SWITCHING STATES’ ELECTION IF THE PHASE CURRENT IS
NEGATIVE DEPENDING ON THE INSTANTANEOUS dc VOLTAGE
UNBALANCE FOR THE SINGLE-PHASE HYBRID FCC (VCA = VCB = E)
will be applied in this section to demonstrate that they can be
used with the proposed 1DM technique. In all the multilevel
converter topologies, the dc voltage error is defined as the V
LEON et al.: APPROACH TO DEVELOP MODULATION STRATEGY FOR SINGLE-PHASE MULTILEVEL CONVERTERS 3245
Fig. 13. 1DM technique for a single-phase FCC with dc voltage control. The control objective is to achieve VCA = VCB = 200 V starting from an unbalanced
situation (VCA = 150 V, VCB = 250 V). The total dc-link voltage is forced to be equal to 400 V. (a) dc voltages of each H-bridge. (b) Output-modulated
voltage.
that is the difference between the measured dc voltage and its
desired reference.
1) 1DM With dc Voltage Balance Applied to DCCs: The
balancing control algorithm for a single-phase five-level DCC
is summarized in Table I where, depending on the sign of the
load current flowing from A to B (IAB) and the sign of the
unbalance (∆V = VC1 − VC2) that defined VC1 and VC2 in
Fig. 1, the redundant medium switching states are chosen. The
proposed 1DM method with the voltage balancing optimization
has been experimentally tested using the previously described
50-kVA five-level DCCs. In order to show the good perfor-
mance of the proposed modulation technique and the voltage
balance control, a single-phase nonlinear load (L plus a passive
diode full bridge plus RC circuit; L = 7 mH, R = 180 Ω, and
C = 2200 µF) is connected to the ac output of the three-phase
DCCs. In order to test the balancing algorithm using the redun-
dancy property, a 150-V initial unbalance is imposed in the dc
link when the dc-link voltage is maintained at 800 V. The exper-
imental results are shown in Fig. 12, and it can be seen that the
dc-link capacitor voltages achieve the voltage balance in 0.3 s
when the proposed methods are applied even when starting
from an unbalanced situation.
It has to be noticed that the balancing control strategy is
extremely simple and that using the TMS320VC33 DSP run-
ning at 50 MHz, the computational cost is approximately 5 µs.
The number of redundant switching states increases with the
number of levels, and they can be used to control the dc-
link balance using control algorithm similar to other previous
methods for multilevel converters [26]–[28].
2) 1DM With dc Voltage Balance Applied to FCCs: The
capacitors of the FCCs have a natural balancing capability when
TABLE V
REDUNDANT SWITCHING STATE ELECTION FOR A TWO-CELL CHB
DEPENDING ONTHE SIGN OF THE PHASE CURRENT AND THE
INSTANTANEOUS dc VOLTAGE UNBALANCE WITH
A VOLTAGE RATIO OF 1 : 1
they are used in the classic configuration with phase-shifted
PWM and are not controlled [29]. For other configurations
(different dc voltage ratios) and other modulation strategies,
the voltages of the flying capacitors in the FCC have to be
controlled to obtain the desired output voltages. As in the
DCCs, all the possible switching states can be studied to know
the best redundant switching state to be applied to control the
dc voltages of the power converter [30]. As an example, a study
for the FCC, where the flying capacitor voltages are VCA =
VCB = E, is introduced. All the possible cases depending
on the instantaneous dc voltage unbalance are summarized in
Table II.
In Tables III and IV, the election of the best redundant
state to be used in the switching sequence is presented. It
must be noticed that in the FCC with VCA = VCB = E, phase
state 1 can be achieved by two different switching combi-
nations (SWP1, SWP3 ON−SWP2, SWP4 OFF and SWP1,
3246 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 9, SEPTEMBER 2008
Fig. 14. 1DM technique for a single-phase two-cell CHB with dc voltage control. The control objective is VC1 = VC2 = 250 V. (a) dc voltages of each
H-bridge. (b) Output-modulated voltage.
SWP3 OFF−SWP2, SWP4 ON). In Tables III and IV, the
power semiconductors to be switched on are shown in each case
to obtain phase state 1. Simulation results are presented to show
the good performance of the proposed 1DM technique with the
dc voltage control for FCC converters. The total dc voltage of
the FCC is equal to 2E = 400 V. The desired voltage of the fly-
ing capacitors is equal to E = 200 V(VCA = VCB = 200 V).
The FCC is connected to an RL load (L = 2 mH, R = 10 Ω).
An initial voltage unbalance is imposed in the flying capacitors
(VCA = 175 V, VCB = 225 V) when the dc-link voltage is
forced to be equal to 400 V. At that moment, the proposed
1DM with the dc voltage control begins to be executed, and
the dc voltage unbalance is avoided. The dc voltages of the
flying capacitor and output-modulated voltages are shown in
Fig. 13(a) and (b), respectively.
3) 1DM With dc Voltage Balance Applied to CHB: There is
no need to balance the dc voltages when isolated dc sources are
used to feed the CHB and the converter works as a controlled
inverter. The dc-link balancing technique is necessary only
when all the H-bridges are not fed by individual sources [31] or
if the CHB topology is considered as a regenerative rectifier. A
similar method to achieve the desired dc voltages in the single-
phase two-cell CHB with a dc voltage ratio of 1 : 1 using the
proposed 1DM strategy is presented. The effect of each switch-
ing state on the dc capacitor voltages can be determined. All the
possibilities are summarized in Table V, where the redundant
switching states are chosen depending on the signs of the output
current IAB and the dc voltage unbalance. Some simulation
results are represented to show the good performance of the
proposed technique. The considered dc voltage ratio target is
1 : 1 (equal dc voltages in each H-bridge VC1 = VC2 = 250 V).
Applying Table V, the results of connecting resistive loads to
the single-phase two-cell CHB (50 and 20 Ω in the upper and
lower H-bridges, respectively) are shown in Fig. 14. The dc
voltages of each H-bridge and the output-modulated voltage
are shown in Fig. 14(a) and (b), respectively. First, the 1DM
strategy is applied without applying the dc voltage ratio control
technique. In 0.7 s, the voltage balance control technique is
applied, with the 1DM method achieving the dc voltage ratio
control. The dc voltage balance is perfectly achieved.
IV. CONCLUSION
In this paper, a simple and generalized modulation method
for single-phase multilevel converters has been presented,
achieving output signals with high quality with extremely
simple calculations. The reference vector is achieved as the
averaged value between the two nearest output voltage levels
of the power converter. This is the follow-up paper of our
presentation on the ISIE07 conference [17] and ICIT08 [18]
including the study of the most common multilevel converter
topologies (DCCs, FCCs, CHBs, and asymmetric topologies)
and a complete revision, optimizing the flow diagram of the
proposed modulation technique to minimize the computational
cost of the modulation algorithm. The proposed modulation
strategy, which is called 1DM, has a very low computational
cost because it is based on simple geometrical calculations. The
novelty of the proposed modulation method lies on its extreme
simplicity and its facility to be extended to any multilevel
power converter such as hybrid converters presented in [32]
or new converter topologies. The graphical representation of
the modulation problem is introduced as a powerful tool to
LEON et al.: APPROACH TO DEVELOP MODULATION STRATEGY FOR SINGLE-PHASE MULTILEVEL CONVERTERS 3247
develop the simple 1DM technique. Only a few very simple
calculations are needed to develop the 1DM strategy for any
multilevel power converter, and the necessary calculations to
determine the switching sequence and the duty cycles are very
simple.
In addition, the proposed way to represent the control region
of the single-phase power converter directly shows the possible
switching states’ redundancy to generate the reference voltage.
These redundancies can be used for several objectives, and
as an example, the control strategy based on the well-known
redundancy property has been applied to the proposed 1DM
technique. This way, it is demonstrated that this conventional
control technique can be applied to the proposed 1DM tech-
nique easily. Some examples have been introduced; however,
any topology of the power converter could be studied in order
to develop its 1DM method and its balance control technique.
Other control strategies considering the switching states’ re-
dundancy can be applied to the proposed 1DM technique. For
instance, a selection criterion can be used to choose among
the redundant switching states, minimizing the commutations
of the switching sequence. Moreover, instead of using the two
nearest switching states of the control region, the switching
sequence could be formed by the nearest switching states but,
this time, minimizing the commutations. The 1DM technique,
only considering the other voltage levels, would eliminate the
switching states which introduce a higher number of commuta-
tions. However, in general, the minimization of the number of
commutations would be achieved at the expense of an increase
of the output voltage ripple.
Experimental and simulation results are shown to validate
the proposed methods for the most common multilevel power
converters (DCCs, FCCs, and CHBs). This way, the good
performance of the modulation technique and the voltage bal-
ancing control strategy has been shown.
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Jose I. Leon (S’04–M’07) was born in Cádiz, Spain,
in 1976. He received the B.S., M.S., and Ph.D.
degrees in telecommunications engineering from the
University of Seville (US), Seville, Spain, in 1999,
2001, and 2006, respectively.
He is with the US, where, in 2002, he was with
the Power Electronics Group working on research
and development projects and where he is currently
an Associate Professor with the Department of Elec-
tronic Engineering, Escuela Superior de Ingenieros.
His research interests include electronic power sys-
tems, and modeling, modulation, and control of power electronics converters
and industrial drives.
Ramon Portillo (S’06) was born in Seville, Spain, in
1974. He received the M.S. degree in industrial engi-
neering from the University of Seville (US), Seville,
in 2002, where he is currently working toward the
Ph.D. degree in electrical engineering in the Power
Electronics Group.
Since 2001, he has been with the US, where he
was with the Power Electronics Group working in
research and development projects and since 2002,
has been an Associate Professor with the Department
of Electronic Engineering, Escuela Superior de In-
genieros. His research interests include electronic power systems applied to
energy conditioning and generation, power quality in renewable generation
plants, applications of fuzzy systems in industry and wind farms, and modeling
and control of power electronic converters and industrial drives.
Sergio Vazquez (S’04) was born in Seville, Spain,
in 1974. He received the B.S. and M.S. degrees in
industrial engineering from the University of Seville
(US), Seville, in 2003 and 2006, respectively.
Since 2002, he has been with the US, where he
was with the Power Electronics Group working in
research and development projects and where he is
currently an Assistant Professor with the Department
of Electronic Engineering, Escuela Superior de In-
genieros. His research interests include electronic
power systems; modeling, modulation, and control
of power electronic converters and industrial drives; and power quality in
renewable generation plants.
Jose J. Padilla wasborn in Cordova, Spain, in
1983. He received the B.S. degree in industrial elec-
tronics engineering from the University of Cordova,
Cordova, in 2004. He is currently working toward the
B.S. degree in telecommunications engineering in
the Department of Electronic Engineering, Escuela
Superior de Ingenieros, University of Seville (US),
Seville, Spain.
Since 2007, he has been with the Power Electron-
ics Group, US, working on research and development
projects. His research interests include electronic
power systems, modulation, control, and experimental testing of power elec-
tronic converters.
Leopoldo G. Franquelo (M’84–SM’96–F’05) was
born in Málaga, Spain. He received the M.Sc. and
Ph.D. degrees in electrical engineering from the Uni-
versity of Seville (US), Seville, Spain, in 1977 and
1980, respectively.
Since 1978, he has been with the US, where he
was as a Research Assistant, an Associate Professor
in 1982, and has been a Professor since 1986. From
1998 to 2005, he was the Director of the Department
of Electronic Engineering. His technical interests
started with microprocessor industrial electronics ap-
plications in 1978, evolving into electronics power applications and, in the
1990s, to application-specific IC design for the control of power converters. His
current research interests include modulation techniques for multilevel inverters
and its application to power electronic systems for renewable energy systems.
He is leading a large research and teaching team in Spain. In the last five
years, his group activity can be summarized as 40 publications in international
journals and 165 in international conference proceedings, ten patents, and as
advisor for ten Ph.D. dissertations and 96 research and development projects.
Dr. Franquelo was the Vice President of the IEEE Industrial Electronics
Society Spanish Chapter (2002–2003) and a member-at-large of the IEEE
Industrial Electronics Society AdCom (2002–2003). He was the Vice-President
for conferences of the IEEE Industrial Electronics Society (2004–2007), in
which he has also been a Distinguished Lecturer since 2006. He has been an
Associate Editor for the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
since 2007. Since January 2008, he has been the President Elect of the IEEE
Industrial Electronics Society.
Juan M. Carrasco (M’97) was born in San Roque,
Spain. He received the M.Eng. and Dr.Eng. de-
grees in industrial engineering from the University
of Seville (US), Seville, Spain, in 1989 and 1992,
respectively.
From 1990 to 1995, he was an Assistant Profes-
sor with the Department of Electronic Engineering,
Escuela Superior de Ingenieros, US, where he is cur-
rently an Associate Professor. He has been working
for several years in the power electronic field where
he was involved in the industrial application of the
design and development of power converters applied to renewable energy
technologies. His current research interests are in distributed power generation
and the integration of renewable energy sources.