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01 sega_service_manual_-_sega_saturn_pal_-_no _013-1_june_1995


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Prévia do material em texto

llfliA" SERVICE MANUAL 
SEGA SATURN (PAL) 
NO. 013- 1 
ISSUED JUNE, 1995 
CONTENTS 
1. SPECIFICATIONS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 3 
2. IDENTIFYING PARTS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 4 
3. ACCESSORIES· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 5 
4. IDENTIFICATIONS AND LOCATIONS OF CIRCUIT BOARDS · · · · 5 
5. DISASSEMBLY PROCEDURE································· 6 
6. CD DRIVE MAINTENANCE AND ADJUSTMENT· · · · · · · · · · · · · · · · 8 
7. BLOCK DIAGRAM · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 11 
8. SCHEMATIC DIAGRAMS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 13 
9. CIRCUIT BOARD DIAGRAMS · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 27 
10. PARTS SPECIFICATIONS .. ··· .. · .. · .. ··· .... ····· .. ···· .. · .. 32 
11. EXPLODED VIEW & PARTS LIST · .. · · .. · · ...... · .. · ...... · .. 70 
11-1. Exploded View··········································· 70 
11-2. Mechanical Parts List · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 71 
11-3. Electrical Parts List · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 72 
11-4. Accessories/Package list · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · 77 
Sega Enterprises, Ltd. 
PROTECTION OF EYES FROM LASER BEAM DURING SERVICING 
This set employs laser. Therefore, be sure to follow carefully the instructions below when servicing. 
Warning 
When servicing, do not approach the laser exit with the eye too closely. In case it is necessary to confirm laser beam emission. 
Be sure to observe from a distance of more than 30 em from the surface of the objective lens on the optical pick-up block. 
£ Cautio"' Invisible laser radiation when open and interlocks defeated avoid exposure to beam 
Caution 
Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous 
radiation exposure. 
This console is classified as a CLASS 1 LASER product. 
SAFETY PRECAUTIONS 
Notice: Comply with all cautions and safety related notes located on or inside the cabinet and on the chassis. 
I. When replacing a chassis in the console, all the protective devices must be put back in place, such as barriers, non-metallic 
knobs, adjustment and compartment covers/shields, isolation resistors/capacitors, etc. 
' When service is required, observe the original lead-dress. Extra precautions should be taken to assure correct lead dress in 
the high voltage circuit. 
3. Always use the manufacturer's replacement components. Especially critical components as indicated on the circuit diagram 
should not be replaced by other manufacturer's. Furthermore, where a short-circuit has occurred, replace those components 
that indicate evidence of overheating. 
PRODUCT SAFETY NOTICE 
Many electrical and mechanical parts have special safety-related characteristics. These are often not evident from visual 
inspection nor can the protection afforded by them necessarily be obtained by using replacement components rated for higher 
voltage, wattage, etc. Replacement parts which have these special safety characteristics are identified in this Service Manual. 
Electrical components having such features are identified by marking with a it, in the parts list in this Service Manual. The use 
of a substitute replacement component which does not have the same safety characteristics as the SEGA recommended 
replacement one, shown in the parts list in this Se[Vice Manual, may create shock, fire, or other hazards. Product Safety is 
continuously under review and new instructions are issued from time to time. 
CAUTION ON FUSE REPLACEMENT 
Caution: For continued protection against risk of fire, replace only with same type, amperage, volt fuse. 
Attention: Afin d'assurer une protection permanente contre tout risque d'amon;age electrique, replacer uniquement 
par un fusible de meme type et de amperes volts. 
8 This symbol indicates a Fast Operating Type Fuse . 
.8. This symbol indicates a Time Lag Type Fuse. 
-2-
Audio CD: 
SATURN 
COMPATABILITY 
The normal audio Compact Disc is playable on the Saturn machine, and can be 
altered with all the effects of a modern Hi-fi and more. Surround sound, vocal 
cut-out for Karaoke, program sequence of tracks and shuffle to name but a few. 
You need no extra equipment to play music CDs on your Saturn. 
CD+G: 
CD and Graphics are a format where simple visuals can appear on the screen 
that relate to the music. These visuals might include stills of the band, or other 
pictures. You need to buy no extra equipment to use CD+G on your Saturn. 
CD+EG: 
CD and extended graphics is a new medium ready to be utilised by the music 
community. It is basically an enhanced version of what is described above in 
CD+G. You need no extra equipment to use CD+EG on your Saturn. 
MPEG: 
MPEG is the standard industry format for compressing Full Motion Video 
footage. This means that the footage takes up less disk space, and when it is to 
be viewed, the MPEG program decodes the footage and plays it on screen. The 
MPEG add-on is needed in order to use the MPEG video CDs and Philips CDi. 
At the current rate of compression one movie can fit on two CDs. 
', I 
Developed by Philips, CDi is an interactive CD format that can be used in a 
variety of educational and entertainment purposes. Using video footage and CD 
quality sound CDi has become an industry leader in the field of interactive fun._ 
The MPEG add-on is required to access the full range of CDi software 
Kodak Photo CD: 
Photos stored on CD have theoretically infmite life, are always picture perfect 
and will never fade or be otherwise damaged. The Saturn can access Kodak 
Photo CDs with the use of another Saturn CD which allows the user to see 
display the photos in various ways. There are many Kodak Photo CD stores 
open in the major cities. 
Frame Buffering: A technique to maximise graphic display performance 
by letting the graphics processor chip "set aside" images it has 
already calculated, allowing it to work on enerating the next fraction 
of a seconds visual images, all while the screen is still busy painting 
the last fraction of a second's display. 
Playfields: The background(s), anything that is on screen that it not a . 
sprite. When two playfields (layers of bacground) are contolled 
properly, parrallax scrolling can result.The Sega Saturn has a whole 
chip dedicated to controllingbackgrounds (the VDP2 or Video 
Display Processor 2") that can generate 5 distict layers of 
background at the same time. 
Polygons/Second: (1000's of) The number of polygons of a given size that 
can be drawn on the screen in one second. This figure does not 
include the size of the polygons, nor their texturing, shading, or 
lighting. 
Realtime: An important adjective that usually indicates the game display 
is being re-calculated every second, taking into account the full 
effects of the player's actions. When reffering to a game's response 
or speed, it means the game responds instantly to the player's 
commands. 
Render: Drawing 3D graphical objects on a computer or game machine. 
"BUG" and "Clockwork Knight" are filled with beautifully rendered 
characters. 
Texture Mapping: Copying a bit-map onto the faces of selected polygons 
to give the illusion of surface texture. "Daytona USA" is a great 
example of a texture mapped game. 
Wireframe: A connect the dots approach to showing graphical objects by 
drawing lines between sets of points that make up a geometric 
outline. 
Dynamic Perspective: Constantly changing the point of view ("camera 
angle") so that the players feel that they are weaving in and around 
the on-screen action. Typically requires strong scaling and rotational 
capabilities. This can be seen on SegaSports games on Saturn. 
1. SPECIFICATIONS 
Ratings 
Model MK - 80200-50 
Power supply AC220-240 V 50/60 Hz 
Power consumption Approx. 20W 
Operating environment 
Temperature 5 °C to 35 °C 
HumiditylO% to 80% RH (no condensation) 
Dimensions 
260 mm(W) X 230 mm(L) X 83 mm(H) 
(10.2 inches) x (9.0 inches) x (3.2 inches) 
Specifications 
Master 32bit RISC SH2 (28.4 MHz, 25MIPS) 
CPU Slave 32bit RISC SH2 (28.4 MHz, 25MIPS) 
Sound 68ECOOO (11.3 MHz) 
Work RAM 16 Mbit 
Video RAM 12 Mbit 
Sound RAM 4Mbit 
Memories 
CD Buffer RAM 4Mbit 
IPLROM 4Mbit 
Backup RAM 256 Kbit 
Resolution 320 x 224 dot etc. 
Graphics Colors 1024/2048 (16,770,000 simultaneous transmission) 
Sprite Enlargement, Reducation, Rotation, Transformation 
5 screen maximum 
XY Scroll 4 
Rotation 2 
Enlargement I reduction 2 
Scroll 
Windo~ 2 
Vertical cell scroll 
Special features Lateral line scroll 
Enlargement I reduction 
Polygons Specialized hardware 
Wire frame 
CG Functions 
Special features Flat shading 
Gouraud shading 
32 channels 
Sound PCM & FM sound source 
16 bit sampling 
Sampling rate 44.1 kHz max. 
AudioDSP 
CD-ROM Intelligent double-speed CD drive 
[Note] Characteristics and specifications may be changed without notice. 
-3-
2. IDENTIFYING PARTS 
2-1. Front View of Console 2-3. Control pad 
OPEN Button Cartridge Slot 
ACCESS Light 
CONTROL PORT 1 CONTROL PORT 2 
2-2. Back View of Console 
Master Reset Switch 
DIRECTIONAL Button START Button 
2 
RIGHT SHIFT Button 
A Button 
B Button 
C Button 
POWER Jack 
AN OUT Jack 
-4-
3. ACCESSORIES 
Positive Side 
B 
Lithium Battery (CR2032) RGB Cable 
AC Cable [UK] AC Cable [SOE] AC Cable [AUSTRALIA] 
4. IDENTIFICATIONS AND LOCATIONS OF CIRCUIT BOARDS 
CD Drive Unit 
P. SW Board 
Main Board 
R. SW Board 
Fig. 4-1 
-5-
5. DISASSEMBLY PROCEDURE 
5-1. Top Case Removal 
1) Remove six screws ® and then the top case in the 
direction of the arrow. 
Fig. 5-1 
5-2. CD Compartment lid Removal 
1) Remove two screws ® and then the bracket lid CD 
spring. 
2) Remove spring © . 
3) Remove two screws@ and then the oil dumper. 
4) Push the lever in the direction of arrow ® to 
release the boss and then push the lever in the 
direction of arrow ® to remove the CD compart-
ment lid. 
Fig. 5-2 
5·3. CD Drive Unit Removal 
1). Disconnect two connectors and one flat cable. 
2) Remove the CD drive unit in the direction of arrow 
©. 
Fig. 5-3 
5-4. SH-1 Board Removal 
-6-
l) Remove four screws ® and then the top shield 
plate. 
2) Remove screw CD and release three tabs, then lift 
the SH-1 board in the direction of arrow Q) to 
remove it. 
Fig. 5-4 
5-5. Main Board Removal 
1) Remove four screws ® holding the CD drive 
unit supports. 
2) Remove five screws © and then the main board. 
Fig. 5-5 
5·6. Power, Power Indicator and 
R. SW Boards Removal 
I) Remove three screws If@ and then the power 
board. 
2) Remove screw ® and then the power indicator 
board. 
3) Remove two screws @ and then the R. SW board. 
R.SWBoard 
Fig. 5-6 
-7-
6. CD DRIVE MAINTENANCE AND ADJUSTMENT 
6-1. Maintenance of Pickup 
I) Checking the laser diode 
As the laser diode wears out, the RF level 
(amplitude of eye pattern) becomes lower. 
Check that the RF level is 0.8V - l.4Vp-p during 
maintenance. If the RF level is less that 0.8Vp-p 
then the pickup should be replaced. 
2) Variable resistor on the APC board 
The variable resistor attached to the pickup on the 
APC board is used to adjust the output power of the 
laser. This adjustment is done at the facto!}' and 
can not be performed in the field. If the laser's 
output power is low, the laser diode has worn out 
and should be replaced. Adjusting this variable 
resistor may cause damage to the laser diode. 
6-2. Laser Pickup Replacement 
Procedure 
-8-
Turn the power switch off and unplug the power 
cord from the AC outlet. 
1 
Replace the pickup. 
1 
Set the door close detection switch to on 
manually and turn the power switch on. Check 
that the laser emits light for approx. 3 seconds 
and the pickup lens moves up and down. 
[Note] Be careful not to bring your eyes too 
near to the laser and do not look straight 
at it as this is dangerous. 
l 
Check the FE bias. 
I 
Adjust the focus gain. 
1 
Adjust the TE balance. 
l 
Adjust the tracking gain. 
I 
f 
Check that the eye pattern waveform can be 
observed at the RF test point. (0.8-1.4Vp-p) 
I 
i 
Replacement complete 
[Note] Since the adjutments influence each other, 
it may be necessal}' to repeat them 2 to 3 
times. times. 
Adjustment Preparation 
Apply markings to the positions of the variable resistors 
before adjustment. If the adjustment are out of the 
specifidtions, the following symptoms may occur. 
[Focus gain] 
If the focus adjustment is too low the pickup lens will not 
be able to focus properly and the disk will not rotate. If the 
adjustment is too high portions of a track may be skipped 
and noise will increase. 
[Tracking gain] 
If the tracking adjustment is too low the drive is more 
susceptable to shocks or bumps, portions of a track may be 
skipped or the disk time counter may stop. 
If the adjustment is too high the pickup lens may oscillate 
leading to unstable or distorted sound. 
The focus and tracking adjustments are done so as to 
mutually satisfy conflicting characteristics. 
6-3. Test equipment and tools 
necessary for adjustment 
I. Oscilloscope 
2. DC voltmeter 
3. Non-metallic adjustment screwdriver 
4. Test CD (A-BEC TCD-792A) 
6-4. CD Drive Unit Adjustment Proce-
dure 
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Fig. 6-2 
Oscilloscope 
Fig. 6-3 
' r----------------- '-------------------------------------------------------··---------------------------------------
R104 R111 R113 R118 R114 
t:rn ~ L@] I BPij I F. OFFI FE IN. GND 
Fig. 6-1 
-9-
6-4-1. FE (Focus Error) bias adjustment 
and focus gain adjustment 
I. Connect the oscilloscope to test point FE IN as 
shown in Fig. 6-2. 
2. Turn the power switch on and set the CD drive to 
the stop mode. 
3. Adjust Rll4 (FE bios) so the DC voltage at the 
test point (FE IN) is OV. 
4. Play the first track of the test CD and adjust 
Rill (Focus gain) so the DC voltage is - 7mV. 
6-4-2. FE balance and tracking gain 
adjustments 
I. Connect the oscilloscope to test point BP IN as 
shown in Fig. 6-3. 
2. Turn the power switch on and play the first track 
of the test CD. 
3. After play has begun, connect the TEST pin to 
GND. 
4. Adjust RI04 (FE balance) so the center voltage 
of the waveform is OV. 
5. Adjust Rll3 (tracking gain) so the amplitude of 
the wavefonn is 0.4V as in Fig. 6-4. 
Fig. 6-4 
-10-
2 
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6 
7. BLOCK DIAGRAM 
CLOCK! 
POWER 
SUPPLY 
BOARD 
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CONNECTOR 
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LEFT. ROTATE MAGNIFY AND REDUCE 
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012 ~2 --~CO:;!I~2 -1 
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CRill Rill !OK 
CVAIT Rll4 NOT USED 
CIRLO RIIS NOT USED 
CIRLI Rll6 NOT USED 
ciRL2 Rill NOT USED 
CIRLl Rll8 NOT USED 
BRLS Rl19 NOT USED 
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73 SCAI6 
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105 SCDO 
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- 31-
11. PARTS SPECIFICATIC•It.JS 
IC1/2 
IC H06417095F28 QFP HITACHI 
Parts No.: 315-0922A 
•Top View 
108 
109 
i 
i 
! 
I 
i 
i 
114 i 
• Description 
73 
HD6417095 
38 
i 
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37 
IG H06417095SF28 QFR HITACHt 
Parts No. : 315-0998 
No. 1/0 Pin Name 
1 Dll 
2 1/0 012 Data bus 
3 013 
4 VCCl Power supply (SV) 
5 1/0 014 Data bus 
6 VSSI Power supply (OV) 
7 015 
8 016 ·---
9 l/0 017 Data bus ·-
10 018 --
11 019 
12 VCC2 Power supply (SV) 
13 1/0 D20 Data bus 
14 - VSS2 Power supply (OV) 
15 D21 
16 1/0 D22 Data bus --
17 D23 
18 VCC3 Power supply (SV) 
19 1/0 D24 Data bus -· 
20 - VSS3 Power supply (OV) 
21 D25 --
22 1/0 D26 Data bus --
23 D27 
·-· 
24 - VCC4 Power supply (SV) ·-
25 l/0 D28 Data bus 
26 - VSS4 Power supply (OV) 
27 D29 ·--
28 I!O D30 Data bus 
29 031 
30 AO ---
31 1/0 AI Address bus 
32 A2 
33 - vsss Power supply (OV) 
34 A3 ---
35 A4 --
36 AS 
37 
1/0 A6 
-- Address bus 
---
38 A7 
39 A8 -
40 - vccs Power supply (SV) . 
-32-
Function 
-
No. 1/0 Pin Name Function 
41 1/0 A9 Address bus 
42 - YSS6 Power supply (OV) 
43 A10 
44 All 
45 I/0 A12 Address bus 
46 A13 
47 Al4 
48 - YCC6 Power supply (5Y) 
49 1/0 A15 Address bus 
50 - YSS7 Power supply (OY) 
51 Al6 
52 I/0 Al7 Address bus 
53 A18 
54 - VCC7 Power supply (5Y) 
55 1/0 Al9 Address bus 
56 - YSS8 Power supply(OY) 
57 A20 
58 1/0 A21 Address bus 
59 A22 
60 - VCC8 Power supply (5Y) 
61 1!0 A23 Address bus 
62 - VSS9 Power supply (OY) 
63 A24 
64 1/0 A25 Address bus 
65 A26 
66 0 DACKO DMACO acknowledge 
67 - YCC9 Power supply (5Y) 
68 0 DACK1 DMACl acknowledge 
69 - VSSIO Power supply (OY) 
70 I DREQO DMACO request 
71 I DREQ1 DMAClrequest 
72 0 cso I Chip select 0 
73 0 CS1 Chip select I 
74 0 CS2 Chip select 2 
75 0 CS3 Chip select 3 
76 I/0 BS Bus cycle start 
77 1/0 RD/WR Read/write 
78 - YSSll Power supply (OY) 
79 0 RAS, CE RAS for DRAM/SDRAM, CE for PSRAM 
80 0 CAS,OE CAS for SDRAM/OE for PSRAM 
81 0 CASHH, DQMUU, WE3 Each memory most significant byte select signal 
82 0 CASHL, DQMUL, WE2 Each memory 2nd significant byte select signal 
83 0 CASLH, DWMLU, WEI Each memory 3rd significant byte select signal 
84 - YCClO- Power supply (5Y) 
85 0 CASLL, DQMLL, WEO Each memory least significant byte select signal 
86 - YSS12 Power supply (OY) 
87 0 RD Read pulse 
88 0 CKE SDRAM clock enable control 
89 I WAIT Hardware wait request 
90 0 BEN Reserve 
91 - YSS13 Power supply (OY) 
92 I BACK, BRLS Bus right permission in slave mode/Bus right acknowledge in master mode. 
93 0 BREQ,BGR Bus right request in slave mode/Bus right acknowledge in master mode 
94 0 WDTOYF Watch dog timer output 
95 0 FTOB Free-running timer output B 
96 - VCC11 Power supply (SY) 
97 0 FTOA Free-running timer output A 
98 - VSS14 Power supply (OY) 
99 I FTI Free-running timer input 
100 I FTC! Free-running timer clock input 
101 I RXD Serial data input 
102 0 TXD Serial data output 
103 1!0 SCK Serial clock input/output 
-33-
No. 1/0 Pin Name Function 
104 - VCC(PLL)I2 Power supply (5V) of built-in PLL 
105 I MDO Operation mode pin 
106 - VSS(PLL)I5 Power supply (OV) of built-in PLL 
107 I MDI Operation mode pin 
108 
0 
CAP! 
External capacitor connection pin for PLL 
109 CAP2 
110 I MD2 Operation mode pin 
Ill 0 CKPACKN Clock pause acknowledge output 
112 I CKPREQN Clock pause request input 
113 - VCC13 Power supply (5V) 
114 - N.C Not connected. 
115 - VSS16 Power supply (OV) 
116 - N.C Not connected. 
117 I MD3 Operation mode pin 
118 I/0 CKIO System clock input/output 
119 
I 
MD4 
Operationmode pin 
120 MD5 
121 - VSSI7 Power supply (OV) 
122 I RES Reset 
123 - VCC14 Power supply (5V) 
124 0 IVECF Interrupt vector fetch cycle 
125 I NMI Non-maskable interrupt request 
126 IRL3 
127 
I IRL2 External interruput factor input 
128 IRLI 
129 IRLO 
130 
I/0 
DO 
Data bus 131 Dl 
132 - VCC15 Power supply (5V) 
133 I/0 D2 Data bus 
134 - VSS18 Power supply (OV) 
135 D3 
136 
1/0 
D4 
Data bus 137 D5 
138 D6 
139 - VCCI6 Power supply (5V) 
140 1!0 D7 Data bus 
141 - VSSI9 Power supply (OV) 
142 D8 
143 1!0 D9 Data bus 
144 DIO 
-34-
• Block Diagram 
~ 
MULT 
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(/) 
(/) 
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DIRECT 
_____/ ;; 
CONTROLLER -
MEMORY 
ACCESS 
CONTROLLER r--; OpERATION (X2 CHANNELS) MODE 
CONTROLLER 
OSCILLATOR 
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EXTERNAL BUS 
INTERFACE 
0 0 
-35-
IC3/4/11 4-Mbit SDRAM 
IC HM5241605TT-17 TSOP 
Parts No.: 315-0928-17 
IC UPD4504161 GS-A 12 TSOP 
Parts No.: 315-1022-12 
• Top View & Pin Layout 
1/05 
VssO 
1/06 
1/07 
CAS 1 
AS 
Vee 
• Block Diagram 
0::: 
w 
0 
0 
(.) 
w 
0 
z 
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(.) 
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If) 
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Vss 
1/015 
1/014 
VssO 
1/013 
1/012 
VeeO 
1/011 
1/010 
1Vssa 
1/09 
1/08 
VeeO 
NC 
DQMU 
CLK 
CKE 
NC 
GND 
A7 
A6 
A5 
A4 
Vss 
MEMORY ARRAY 
BANKO 
512 X 256 X HI bit 
•Pin Name 
Pin Name 
A0-A9 
I/00-I/015 
AO -A7 
cs 
RAS 
CAS 
WE 
DQMU 
DQML 
CLK 
CKE 
Ycc 
Yss 
YccO 
YssO 
NC 
0::: 
w 
0 
0 
(.) 
w 
0 
z 
::!!: 
::> 
-' 
0 
(.) 
-36-
IC HM5241605TT-15 TSOP 
Parts No. : 315-0928-15 
Function 
Address inputs 
Row addresses AO-A8 
Column addresses AO-A 7 
Bank select address A9 
Data inputs/outputs 
Chip select 
Row address strobe command 
Column address strobe command 
Write enable 
High-order byte input/output mask 
Low-order byte input/output mask 
Clock input 
Clock enable 
Power supply 
Ground 
Power supply of l/0 pins 
Ground of I/0 pins 
Not connected 
AO -A9 
MEMORY ARRAY 
BANK1 
512 X 256 X 16 bit 
CONTROL LOGIC & 
TIMTING GENERATOR 
ICS SCU {Custom Gate Array) 
IC CUSTOM CHIP SCU QFP 
Pans No.: 315-5688 
•Top View 
52 
53 
• Description 
No. 1/0 
I -
2 1!0 
3 1/0 
4 1/0 
5 1/0 
6 I/0 
7 I/0 
8 1!0 
9 -
10 I/0 
11 -
12 I/0 
13 I/0 
14 1!0 
15 1/0 
16 0 
17 0 
18 0 
19 -
20 0 
21 -
22 0 
157 
104 
156 
I 
I 
105 
Name 
VSS 
AD4 
ADS· 
AD6 
AD7 
AD8 
AD9 
ADIO 
VDD 
ADII 
vss 
AD12 
AD13 
AD14 
ADIS 
AAO 
AAl 
AA2 
vss 
AA3 
VDD 
AA4 
• Block Diagram 
INT 
f--
'---z:-----1~ 
<••n••••••••·••••·ln.·••••••·•••••••••• p-> CPU 1/F 
A-Bus 
1/F DMA 
-
TIMER .__ :: -1-_:-+---ilB 
B-Bus 
1/F 
DSP 
Function 
GND 
A-bus data bit 4 
A-bus data bit 5 
A-bus data bit 6 
A-bus data bit 7 
A-bus data bit 8 
A-bus data bit 9 
A-bus data bit 10 
Power supply +5V 
A-bus data bitll 
GND 
A-bus data bit 12 
A-bus data bit 13 
A-bus data bit 14 
A-bus data bit 15 
A-bus address bit 0 
A-bus address bit 1 
A-bus address bit 2 
GND 
A-bus address bit 3 
Power supply +5V 
A-bus address bit 4 
-37-
No. 1/0 Pin Name Function 
23 0 AA5 A-bus address bit 5 
24 0 AA6 A-bus address bit 6 
25 0 AA7 A-bus address bit 7 
26 0 AA8 A-bus address bit 8 
27 - VSS GND 
28 0 AA9 A-bus address bit 9 
29 0 AAIO A-bus address bit 10 
30 0 AAll A-bus address bit 11 
31 - VDD Power supply +5V 
32 0 AA12 A-bus address bit 12 
33 0 AA13 A-bus address bit 13 
34 0 AA14 A-bus address bit 14 
35 - vss GND 
36 0 AA15 A-bus address bit 15 
37 0 AA16 A-bus address bit 16 
38 0 AA17 A-bus address bit 17 
39 0 AA18 A-bus address bit 18 
40 0 AA19 A-bus address bit 19 
41 - VDD Power supply +5V 
42 0 AA20 A-bus address bit 20 
43 - vss GND 
44 0 AA21 A-bus address bit 21 
45 0 AA22 A-bus address bit 22 
46 0 AA23 A-bus address bit 23 
47 0 AA24 A-bus address bit 24 
48 0 AFCO A-bus function code bit 0 
49 0 AFCI A-bus function code bit 1 
so 0 AAS A-bus address strobe 
51 0 ACSO A-bus chip select 0 
52 ' - VSS GND 
53 0 ACSI A-bus chip select 1 
54 0 ACS2 A-bus chip select 2 
55 - VDD Power supply +5V 
56 I AWAIT A-bus external wait 
57 I All:«) A-bus external interrupt factor 
58 I TEST Test mode selection (normally, input "H") 
59 0 ARD A-bus read pulse 
60 0 AWRU A-bus byte 0 (AD15-8) write pulse 
61 0 AWRL A-bus byte 1 (AD7-0) write pulse 
62 - VSS GND 
63 0 ATIMO A-bus external access timing 0 
64 0 A TIM I A-bus external access timing 1 
65 0 ATIM2 A-bus external access timing 2 
66 1/0 BDO B-bus address/data bit 0 
67 1/0 BDl B-bus address/data bit 1 
68 1/0 BD2 B-bus address/data bit 2 
69 - VDD Power supply +5V 
70 1/0 BD3 B-bus address/data bit 3 
71 - VSS GND 
72 1/0 BD4 B-bus address/data bit 4 
73 1/0 BD5 B-bus address/data bit 5 
74 1/0 BD6 B-bus address/data bit 6 
75 1/0 BD7 B-bus address/data bit 7 
76 1/0 BD8 B-bus address/data bit 8 
77 I/0 BD9 B-bus address/data bit 9 
78 1/0 BDlO B-bus address/data bit 10 
79 - VDD Power supply +5V 
80 1/0 BOll B-bus address/data bit 11 
81 - vss GND 
82 I/0 BD12 B-bus address/data bit 12 
83 1/0 BD13 B-bus address/data bit 13 
84 I/0 BD14 B-bus address/data bit 14 
-38-
No. I 1/0 Pin Name Functior:. 
85 I I/0 BOIS B-bus address/data bit 15 
86 I IROL Light pen interrupt 
87 I IRQV VDP2•V blank interrupt 
88 ' I IRQH VDP2•H blank interrupt 
89 I BRDY2 VDP2 data ready 
90 0 BCS2 VDP2 chip select 
91 0 BADDT · B-bus address/data switching signal 
92 - VSS GND 
93 0 BDTEN B-bus data enable 
94 - VDD +SV Power supply 
95 0 BCSS SCSP chip select 
96 I BRDYS SCSP data ready 
97 I IRQS SCSP interrupt 
98 0 BCSI VDPI chip select 
99 I BRDY1 VDPI data ready 
100 I IR1)1 VDPI interrupt 
101 1/0 CAD C-bus address bit 0 
102 1/0 CAl C-bus address bit 1 
103 1/0 CA2 C-bus address bit 2 
104 - vss GND 
105 - VDD +SV Power supply 
106 I/0 CA3 C-bus address bit 3 
107 1/0 CA4 C-bus address bit 4 
108 1/0 CAS C-bus address bit 5 
109 1/0 CA6 C-bus address bit 6 
110 - VSS GND 
Ill 1/0 CA7 C-bus address bit 7 
112 1/0 CAS C-bus address bit 8 
113 1/0 CA9 C-bus address bit 9 
114 1/0 CAlO C-bus address bit 10 
115 - VSS GND 
116 1/0 CAll C-bus address bit 11 
117 - VDD +SV Power supply 
118 1/0 CA12 C-bus address bit 12 
119 1/0 CA13 C-bus address bit 13 
120 1/0 CA14 C-bus address bit 14 
121 - vss GND 
122 I/0 CA15 C-bus address bit 15 
123 I/0 CA16 C-bus address bit 16 
124 I/0 CA17 C-bus address bit 17 
125 I/0 CA18 C-bus address bit 18 
126 I/0 CA19 C-bus address bit 19 
127 - VDD +SV Power supply 
128 l/0 CA20· C-bus address bit 20 
129 - vss GND 
130 1/0 CA21 C-bus address bit 21 
131 1/0 CA22 C-bus address bit 22 
132 l/0 CA23 C-bus address bit 23 
133 1/0 CA24 C-bus address bit 24 
134 1!0 coo C-bus data bit 0 
135 l/0 CDl C-bus data bit 1 
136 1/0 CD2 C-bus data bit 2 
137 - VSS GND 
138 1/0 CD3 C-bus data bit 3 
139 - VDD +SV Power supply 
140 1/0 CD4 C-bus data bit 4 
141 1/0 CDS C-bus data bit 5 
142 I/0 CD6 C-bus data bit 6 
143 1/0 CD7 C-bus data bit 7 
144 - vss GND 
145 1/0 CDS C-bus data bit 8 
146 1/0 CD9 C-bus data bit 9 
-39-
No. 1/0 P.in"Name Function 
147 1/0 COlO C-bus data bit I 0 
148 1/0 COil C-bus data bit 11 
149 - VOO +5V Power supply 
ISO 1/0 CDI2 C-bus data bit 12 
151 - VSS GNO 
152 1/0 CDI3 C-bus data bit 13 
153 1!0 CDI4 C-bus data bit 14 
154 1/0 CDIS C-bus data bit 15 
155 1/0 C016 C-bus data bit 16 
!56 1/0 CDI7 C-bus data bit 17 
157 - vss GND 
!58 1/0 CDI8 C-bus data bit 18 
!59 1!0 CDI9 C-bus data bit 19 
160 - VOO +5V Power supply 
161 1/0 C020 C-bus databit 20 
162 1/0 C02! C-bus data bit 21 
163 1/0 C022 C-bus data bit 22 
164 - VSS GND 
165 1!0 CD23 C-bus data bit 23 
166 1!0 C024 C-bus data bit 24 
167 1/0 CD25 C-bus data bit 25 
168 1/0 CD26 C-bus data bit 26 
169 1!0 CD27 C-bus data bit 27 
170 - VOO +5V Power supply 
171 1/0 CD28 C-bus data bit 28 
172 - VSS GNO 
173 1!0 CD29 C-bus data bit 29 
174 I/0 CD30 C-bus data bit 30 
175 1/0 CD31 C-bus data bit 31 
176 I CCSI C-bus chip select 1 
177 I CCS2 C-bus chip select 2 
178 0 CCS3 C-bus chip select 3 
179 - VSS GND 
180 I RESET Initial reset 
181 I CLK28 System clock 
182 1/0 CRDWR C-bus read/write 
183 I CRO C-bus read pulse 
184 - VDO +5V Power supply 
185 1!0 CDQMUU SDRAM byte 0 (CD31-24) write pulse 
186 IJO CDQMUL SDRAM byte I (C023-I6) write pulse 
187 I/0 CDQMLU SDRAM byte 2 (CD! 5-8) write pulse 
188 I/0 C:DQMLL SDRAM byte 3 (C07-0) write pulse 
189 - VSS GND 
190 0 RAS ·- SDRAMRAS 
191 0 CAS SDRAMCAS 
192 0 CWAIT C-bus external wait 
193 - VDO +5V Power supply 
194 I CIVECF C-bus interrupt vector fetch sycle 
195 0 CIRLO C-bus external interrupt factor 0 
196 0 CIRLI C-bus external interrupt factor 1 
197 0 CIRL2 C-bus external interrupt factor 2 
198 0 CIRL3 C-bus external interrupt factor 3 
199 - VSS GND 
200 0 CBREO C-bus right request 
201 I CBACK C-bus right acknowiedge 
202 I MIREQ System manager interrupt 
203 0 AA25 A-bus address bit 25 
204 I/0 ADO A-bus data bit 0 
205 l/0 AD! A-bus data bit I 
206 I/0 AD2 A-bus data bit 2 
207 1!0 AD3 A-bus data bit 3 
208 - VDO +5V Power supply 
-40-
IC6 DCC 
IC CUSTOM CHIP DCC QFP 
Parts No. : 315-5778 
•Top View 
80 
81 
100 
•Pin Name 
No. 1/0 
I 
I I 
2 0 
3 0 
4 0 
5 -
6 0 
7 0 
8 I 0 
9 0 
10 0 
II 0 
12 0 
13 0 
14 0 
15 -
16 -
17 0 
18 0 
19 0 
20 0 
21 0 
22 0 
23 0 
24 0 
25 -
26 -
27 I 
28 I 
29 I 
30 I 
31 I 
32 I 
33 I 
34 I 
Name 
TESTl 
TESTO 
BEN 
BDIR 
VSS 
DAO 
DAI 
DA2 
DA3 
DA4 
DAS 
DA6 
DA7 
DA8 
vss 
VDD 
DRASO 
DRASl 
DRAS2 
DRAS3 
DUCAS 
DLCAS 
DWE 
DOE 
vss 
VDD 
Al 
A2 
A3 
A4 
A5 
A6 
A7 
AS 
51 
30 
50 
I 
I 
! 
I 
31 
No. 
35 
36 
37 
38 
39 
40 
41 
42 
43 
44 
45 
46 
47 
48 
49 
50 
51 
52 
53 
54 
55 
56 
57 
58 
59 
60 
61 
62 
63 
64 
65 
66 
67 
68 
1/0 
I 
I 
I 
I 
I 
-
-
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
I 
-
0 
0 
-
I 
I 
I 
-
I 
I 
I 
0 
-
-
I 
I 
-41-
Name No. 1/0 Name 
A9 69 I I WEO 
AlO 70 - vss 
All 71 0 BACK 
Al2 72 0 EXBACK 
A13 73 0 BRLS 
VSS 74 - VSS 
VDD 75 I BGR 
A14 76 I I BREQ 
Al5 77 I I EXBREQ 
Al6 78 0 MFT1 
A17 79 0 SFTl 
Al8 80 - VDD 
A19 81 I I CK 
A20 82 - VSS 
A2l 83 I RESET 
A22 84 I BS 
A23 85 I EWT 
A24 86 0 IOCE 
vss 87 0 EXT CEO 
IREQl 88 0 EXTCEI 
IREQ2 89 0 EXTCE2 
VDD 90 - vss 
IVECF 91 - VDD 
RD/WR 92 I HINT 
RD 93 I VINT 
vss 94 I DECON 
CS2 95 0 ROMCE 
CSl 96 0 SMPCCE 
cso 97 0 SRAMCE 
WAIT 98 0 MOE 
VDD 99 0 MWR 
vss 100 - vss 
WTIN 
WEI 
IC7 IPL ROM 
OS SATURN IPL-ROM PAL DIP 
Parts No.: EPR-17933 
Parts No.: MPR-17933 
• Top View & Pin Layout 
010 
03 
011 
ICS BACKUP RAM 
AS 
AS 
A10 
A11 
A12 
A13 
A14 
A15 
A16 
1 BY'i'E 
GND 
D151A-1 
07 
014 
06 
013 
05 
012 
D4 
IC CXK58267 AM-1 OL SOP 
Parts No. : 315-0948-10 
IC SRM20257LLM1 0 SOP 
Parts No. : 315-0965-10 
II Block Diagram 
A14 
A13 
A12 
A11 
AS 
AS 
A7 
AS 
AS 
A 10 o+++.f':5l5:t==f 
A4 
A3 
A2 
A1 
AO 
CE1 o----or-...., 
CE20•---t 
•Pin Name 
A0-Al7 Address inputs 
CE Chip enable 
OE Output enable 
GND Ground 
BYTE 
DO-DIS Data inputs/outputs 
Vee +SV power supply 
IC UPD43257B-1 OLL SOP IC M5M5255BFP-12LL SOP 
Parts No. : 315-0930-10 Parts No.: 315-0964-10 
IC UM62257M-70LL SOP 
Parts No.: 315-1002-70 
II Top View & Pin Layout 
A14 vee 
WE 
A13 
Vee AS 
MEMORY AS 
MATRIX A11 
512 X 512 CE2 
GND 
CE1 
1 II OS 
1101 1/07 
1102 1106 
1/03 1105 
GND 
I!OGATE 
COLUMN 
DECODER • Description 
Name Function 
AO-Al4 Address inputs 
1!01-I/08 Data inputs/outputs 
CEl, CE2 Chip enable inputs 
WE Write enable input 
Vee +5V power supply 
1101 1108 GND Ground 
-42-
IC9 SMPC 
IC CUSTOM CHIP SMPC QFP 
Parts No.: 315-5744 
•Top View 
64 52 
19 
20 32 
• Description 
No. 1/0 Name 
1 R70 -
2 R71 
3 R72 
1!0 
4 R73 
5 R50 
6 R51 
I 
7 R52 
8 R53 
9 - TEST 
10 OSCl 
I!O 
11 OSC2 
12 - GND 
13 X2 
1!0 
14 XI 
15 RESET 
16 - vee 
17 I cs 
18 I R/W 
19 AI 
20 A2 
21 A3 
22 
I/0 
A4 
23 AS 
24 A6 
25 DBO 
26 DBI 
27 DB2 
28 DB3 
29 
l!O 
DB4 
30 DBS 
31 DB6 
32 DB7 
I 51 
I 
33 
Function 
Not connected. 
Reset control 
Jumper configuration input 
Not connected ~GND 
Clock 3 
Ground 
Clock 4 
Master reset input 
Power 
Chip select input 
Read/write input 
Address bus 
Data bus 
-43-
No. 1/0 
33 
34 
35 
36 I/0 
37 
38 
39 
40 
41 
42 
43 I/0 
44 
45 
46 
47 I 
48 I 
49 
50 
l/0 
51 
52 -
53 
54 
55 
56 
57 
1/0 
58 
59 
60 
61 
62 
1/0 
63 -
64 
Name Function 
PIOOA 
Pl01A 
PI02A 
PI03A Control pad 
PI04A 
PI OSA 
PI06A 
PIOOB 
PIOlB 
PI02B 
PI03B Control pad 
PI04B 
PIOSB 
PI06B 
EXL Input 
INTO/D13 Input 
INT2!R01 Backup RAM reset control 
DO 
Reset control 
Dl 
D2 Not connected. 
D3 
D4 
DS 
D6 
Reset control 
D7 
D8 
D9 
DlO 
R60 
Reset control 
R61 
R62 
Not connected. 
R63 
IC10 VDP1 
IC CUSTOM CHIP VDP1 QFP IC CUSTOM CHIP VDP1 S QFP 
Parts No. : 315-5689 Parts No. : 315-5883 
•Top View 
126 
127 
I 
I 
I 
I 
• Description 
No. 
I 
2 
3 
4 
5 
6 
7 
8 
9 
10 
11 
12 
13 
14 
15 
16 
17 
18 
19 
20 
21 
22 
23 
24 
25 
26 
27 
28 
29 
30 
31 
32 
33 
34 
35 
36 
37 
38 
39 
40 
1/0 
-
0 
-
0 
0 
0 
-
0 
0 
-
0 
0 
I 
-
-
-
-
0 
0 
0 
-
0 
' -
0 
-
0 
85 
84 
43 
42 
Name Function 
Ne Not connected. 
VRAMA7 
VRAMA8 Address bus (VRAM) 
VRAMA9 
VSS Ground for 1/0 pin 
veLK Clock (VRAM) 
VUDQM Upper byte input/output mask(VRAM) 
VLDQM Lowerbyte input/output mask(VRAM) 
VSS Ground for internal circuit 
veASN Column address asserted (VRAM) 
VRASN Row address asserted (VRAM) 
vee Power supply 
VWEN Write enable (VRAM) 
veSN Chip select (VRAM) 
MeLK Master clock 
RESETN Reset 
vss Ground for 1/0 pin 
esN Chip select 
ADN Address/data select 
DTEN Data enable 
IRON Interrupt request 
READYN Ready 
VBUSO 
VBUSl Address/data bus (Syscon) 
VBUS2 
vss Ground for 1!0 pin 
VBUS3 
VBUS4 
VBUS5 Address/data bus (Syscon) 
VBUS6 
VRUS7 
vee Power supply 
VBUS8 
VBUS9 
Address/data bus (Syscon) 
VBUSlO 
VBUSll 
vss Ground for internal circuit 
VBUS12 
VBUS13 Address/data bus (Syscon) 
VBUS14 
-44-
No. I 110 Name Function 
4! ! 0 VBUS15 Address/data bus (Syscon) 
42 NC 
Not connected. -
43 NC 
44 FOAO 
45 0 FOAl Address bus (FBO) 
46 FOA2 
47 I - VSS Ground for 1/0 pin 
48 0 FOA3 Address bus (FBO) 
49 I 0 FOA4 Address bus 
50 0 FOAS Frame buffer (FBO) 
51 0 FOA6 Address bus (FBO) 
52 - vee Power supply 
53 FOA7 
54 0 FOA8 Address bus (FBO) 
55 FOA9 
56 0 FOCSN Chip select (FBO) 
57 - vss Ground for internal circuit 
58 0 FOWEN Write enable (FBO) 
59 0 FOCLK Clock (FBO) 
60 0 FRRASN Row address asserted (FBO) 
6! 0 FOCASN Column address asserted (FBO) 
62 0 FOLDQM Lower byte input/output mask (FBO) 
63 0 FOUDQM Upper byte input? output mask (FBO) 
64 - vss Groun for 1/0 pin 
65 FODO 
66 FODl 
67 0 FOD2 Data bus (FBO) 
68 FOD3 
69 FOD4 
70 - vss Ground for internal circuit 
71 FODS 
72 
0 
FOD6 
Data bus (FBO) 
73 FOD7 
74 FOD8 
75 - vee Power supply 
76 FOD9 
77 
0 
FODIO 
Data bus (FBO) 
78 FODll 
79 FODI2 
80 - vss Ground for I/0 pin 
81 FOD13 
82 0 FOD14 Data bus (FBO) 
83 FOOlS 
84 NC 
Not connected. -
85 NC 
86 FIDO 
87 0 FlDl Data bus (FBI) 
88 F1D2 
89 - vss Ground for I/0 pin 
90 FlD3 
91 
0 
FID4 
Data bus (FBI) 
92 FIDS 
93 FID6 
94 - vee Power supply 
95 FID7 
96 
0 
FID8 
Data bus (FBI) 
97 FlD9 
98 FIDlO 
99 - vss Ground for internal circuit 
100 FIDll 
101 FID12 
102 0 FID13 Data bus (FB 1) 
103 FlD14 
104 FID15 
-45-
No. 1/0 N~me Function 
105 - VSS Ground for 1/0 pin 
106 0 FICLK Clock (FBI) 
107 0 FICSN Chip select (FBI) 
108 0FIWEN Write enable (FBI) 
109 0 FIRASN Row address asserted (FBI) 
110 0 FICASN Column address asserted (FBI) 
Ill 0 FlLDQM Lower byte input/output mask (FB 1) 
112 - vss Data bus (FB l) 
113 0 FIUDQM Lower byte input/output mask (FB 1) 
114 FIAO 
115 0 FlAl Address bus (FBI) 
116 FIA2 
117 - vee Power supply 
118 FIA3 
119 0 FIA4 Address bus (FBI) 
120 FlA5 
121 0 FIA6 Address bus (FB 1) 
122 - VSS Ground for I/0 pin 
123 0 FIA7 
124 0 F1A8 Address bus (BF1) 
125 0 FIA9 
126 
NC Not connected. -
127 
128 - HTIMN Horizontal sync timing 
129 - VTIMN Vertical sync timing 
130 0 V2CLK Video clock (1!2 MCLK) 
131 - vss Ground for 1/0 pin 
132 0 VOUTO 
133 0 VOUTI 
Display start address/video data 
134 0 VOUT2 
135 0 VOUT3 
136 - vee Power supply 
137 0 VOUT4 Display start address/video output data 
138 0 VOUT5 
139 0 VOUT6 Video output data 
140 0 VOUT7 
141 - vss Ground for internal circuit 
142 0 VRAMDO 
143 0 VRAMDI 
144 0 VRAMD2 VRAM data bus 
145 0 VRAMD3 
146 0 VRAMD4 
147 - VSS Ground for 1!0 pin 
148 0 VRAMD5 
149 0 VRAMD6 
150 0 VRAMD7 
VRAM data bus 
151 0 VRAMD8 
152 0 VRAMD9 
153 0 VRAMDlO 
154 - VSS Ground for internal circuit 
155 0 VRAMD11 
156 0 VRAMD12 
VRAM data bus 
157 0 VRAMD13 
158 0 VRAMD14 
159 - vee Power suppiy 
160 0 VRAMDI5 VRAM data bus 
161 0 VRAMAO 
162 0 VRAMAI 
163 0 VRAMA2 
164 0 VRAMA3 VRAM address bus 
165 0 VRAMA4 
166 0 VRAMA5 
167 0 VRAMA6 
168 - NC Not connected. 
-46-
IC12/13/15/16 
IC UPD4502161G5-A12 TSOP NEC 
Parts No.: 315-0910-12 
IC HM5221605TT-17 TSOP HITACHI 
Parts No.: 315-1017-17 
IC LC382161T-17 TSOP SANYO 
Parts No. :315-1012-17 
• Top View & Pin Layout •Pin Name 
Vss A0-A9 Address inputs 
0015 
0014 
DQO-DQ5 Data inputs/outputs 
Vss CLK System clock input 
0013 CKE Clock enable 
0012 
Vee 7 Vee cs Chip select 
004 0011 RAS Row address strobe command 
005 0010 
1Vss CAS Col/ address strobe command 
009 WE W ritre enable 
008 
Vee DQML,DQMU DQ mask enable 
NC 
OOMU 
Vee Supply voltage 
CAS 1 CLK Vss.GND Ground 
CKE NC No connection 
NC 
GNO 
AS 1 GNO 
A7 
A6 
AS 
A3 A4 
Vee Vss 
• Description 
No. 1/0 Pin Name Function 
l' 7, 13, 25, 38, 44, - vee Power supply of internal circuits. 
50 
4, 10,26,41,47,50 - vss Ground pins. 
2, 3, 5, 6, 8, 9, 11' 
12, 39, 40, 42, 43, l/0 DQ1-DQ16 l/0 pins are the same as conventional DRAM. 
45,46,48,49 
DQMU controls upper byte and DQML controls lower byte input/output 
buffers. In read mode, DQMU, DQML control output buffer impedance like 
conventional OE. If DQMU, DQML is high, output buffers become high 
14,36 I DQML,DQMU 
impedance. If DQMU, DQML is low, output buffers become low imedance. 
If DQMU, DQML is low, output buffers become low impedance. 
And when device in write mode, DQMU, DQML control word mask. If 
DQMU, DQML is high input data is not written to memory cell. If DQMU, 
DQML is low input data is written to memory cell. 
WE CAS RAS have the same names with conventional DRAM. But these pins 
15, 16, 17 I WECASRAS have different definitions with conventional ones. All of these pins only define 
command cycle definition. For detail information see command table. 
CS low start the command input cycle. When CS is high, all input are not 
18 I cs referenced. But even if CS is high, internal operations i.e. bank active or burst 
are not changed. 
19 I A9 
A9 is bank select signal (BS). In command cycle, A9=low select bank A and 
A9=high select bank B. 
-47-
No. 1/0 Pin Name Function 
Row address (AX0-AX6, AX8) is detennined by A0-A8 level at the bank 
active command cycle CLK rising edge. (AX7 is don't care.) 
Column address (A YO-A Y7) is detennined by AO-A 7 level at read or write 
command cycle CLK rising edge. And this column address become bun;t 
20,21-24,27-30 I AO-A8 access start address. A8 define precharge mode command cycle, both banks are 
prechareged. But A8=low in when A8=high in precharge command cycle, only 
one bank that is selected A9 (BS) is precharged. And when A8=high in read or 
write command cycle, the precharge cycle start automatically after the last data 
in bun;t accessing. 
31,32 - GND Ground 
33,37 - NC Not connected. 
CKE detennine next CLK is valid or not. If CKE is high next CLK rising edge 
is valid. But if CKE is low, next CLK is invalid. If CLK rising edge is invalid, 
34 I CKE 
internal clock is not asserted and J.l PD4504161 becomes halt operation. 
And when J.l PD4502161 does not in bun;t mode and CKE is negated, 
J.l PD4502161 enter power down mode. During power down mode CKE must 
keep low level. 
35 I CLK 
CLK is the master clock input pin. The other inputs signals are referenced at 
CLK rising edge. 
IC14 VDP2 
IC CUSTOM CHIP VDP2 QFP YAMAHA IC CUSTOM CHIP VDP2 QFP HH IC CUSTOM CP VDP2 S QFP YAMAHA 
Parts No. : 315-5690 Parts No. : 315-5690-02 Parts No. : 315-5890 
•Top View 
120 
121 
160 
81 
40 
80 
I 
I 
41 
• Block Diagram 
scu 
I Bus control 
Scroll picture block 
Normal Rotation 
picture t--<r- picture coordinate coordinate 
calculation calculation 
i 
Pattern Window name fo-< f.- control control 
Character I-< f.- Line picture control control 
VRAM Dot data 
control r-1 control 
VRAM 
-48-
VDP2 
~ " 
;1- -A 
'-.r-11 
-
HN counter & timing generator r 
Video process 
Color offset r----& shadow 
Color 
computing 1--
control 
Priority f---.-control 
Expanded 
picture circuit 
Output data 
control 
Color RAM 
Color RAM 
control 
Sprite 
control 
VDP1 
1--
I 
r--
f-
No. 1/0 "Pin Name Function 
1 I 0 RBCS VRAM-B chip select 
2 0 RBRAS VRAM-B row address strobe 
3 0 RBCAS VRAM-B column address strobe r 
4 0 RBWE VRAM-B write enable 
5 - vss GND 
6 0 RBLDM VRAM-B DQ low-order mask enable 
7 0 RBUDM VRAM-B DQ high-order mask enable 
8 0 RBAO VRAM-B address bit 0 
9 I 0 RBA1 VRAM-B address bit 1 
10 - VDD +5V power supply 
11 I 0 I RBA2 VRAM-B address bit 2 
12 0 RBA3 VRAM-B address bit 3 
13 0 RBA4 VRAM-B address bit 4 
14 0 RBA5 VRAM-B address bit 5 
15 - VSS GND 
16 0 RBA6 VRAM-B address bit 6 
17 0 RBA7 VRAM-B address bit 7 
18 0 RBA8 VRAM-B address bit 8 
19 0 RBA9 VRAM-B address bit 9 
20 1/0 VDO SYSCON interface data bit 0 
21 1!0 VOl SYSCON interface data bit 1 
22 1!0 VD2 SYSCON interface data bit 2 
23 I/0 VD3 SYSCON interface data bit 3 
24 - vss GND 
25 I/0 VD4 SYSCON interface data bit 4 
26 1!0 VD5 SYSCON interface data bit 5 
27 1/0 VD6 SYSCON interface data bit 6 
28 I/0 VD7 SYSCON interface data bit 7 
29 - VDD +5V power supply 
30 1!0 VD8 SYSCON interface data bit 8 
31 1!0 VD9 SYSCON interface data bit 9 
32 1/0 VDlO SYSCON interface data bit 10 
33 1!0 VDll SYSCON interface data bit 11 
34 1!0 VD12 SYSCON interface data bit 12 
35 1!0 VDl3 SYSCON interface data bit 13 
36 - vss GND 
37 1!0 VD14 SYSCON interface data bit 14 
38 1!0 VD15 SYSCON interface data bit 15 
39 I AD SYSCON interface address/data selection 
40 I DTEN SYSCON interface data enable 
41 0 READY SYSCON interface data ready 
42 I cs SYSCON interface chip select 
43 - VDD +5V power supply 
44 0 VINT · SYSCON interface vertical interrupt 
45 0 HINT SYSCON interface horizontal interrupt 
46 I EXLAT External latch strobe input 
47 I EXSYN External sync signal input 
48 1!0 EXBGO External input data bit 0 I Test input/output (in test mode) 
49 1!0 EXBG1 External input data bit 1 I Test input/output (in test mode) 
50 1!0 EXBG2 External input data bit 2 I Test input/output (in test mode) 
51 110 EXBG3 External input data bit 3 I Test input/output (in test mode) 
52 - VSS GND 
53 110 EXBG4 External input data bit 4 I Test input/output (in test mode) 
54 l/0 EXBG5 External input data bit 5 I Test input/output (in test mode) 
55 110 EXBG6 External input data bit 6 I Test input/output (in test mode) 
56 110 EXBG7 External input data bit 7 I Test input/output (in test mode) 
57 110 EXBG8 External input data bit 8 I Test input/output (in test mode) 
58 1/0 EXBG9 External input data bit 9 I Test input/output (in test mode) 
59 1/0 EXBG10 External input data bit 10 I Test input/output (in test mode)