electronics-10-00428-v2 (1)

Prévia do material em texto

<p>electronics</p><p>Article</p><p>A Novel DC Bias Suppression Strategy for Single-Phase</p><p>Full-Bridge DC-DC Arc Welding Converter</p><p>Yang Zhou , Bojin Qi * , Minxin Zheng * and Baoqiang Cong *</p><p>����������</p><p>�������</p><p>Citation: Zhou, Y.; Qi, B.; Zheng, M.;</p><p>Cong, B. A Novel DC Bias</p><p>Suppression Strategy for Single-Phase</p><p>Full-Bridge DC-DC Arc Welding</p><p>Converter. Electronics 2021, 10, 428.</p><p>https://doi.org/10.3390/electronics</p><p>10040428</p><p>Academic Editor: Emilio</p><p>Gomez-Lazaro</p><p>Received: 30 December 2020</p><p>Accepted: 29 January 2021</p><p>Published: 9 February 2021</p><p>Publisher’s Note: MDPI stays neu-</p><p>tral with regard to jurisdictional clai-</p><p>ms in published maps and institutio-</p><p>nal affiliations.</p><p>Copyright: © 2021 by the authors. Li-</p><p>censee MDPI, Basel, Switzerland.</p><p>This article is an open access article</p><p>distributed under the terms and con-</p><p>ditions of the Creative Commons At-</p><p>tribution (CC BY) license (https://</p><p>creativecommons.org/licenses/by/</p><p>4.0/).</p><p>School of Mechanical Engineering and Automation, Beihang University, Beijing 100191, China;</p><p>zhouyango@buaa.edu.cn</p><p>* Correspondence: qbj@buaa.edu.cn (B.Q.); zhminxin@buaa.edu.cn (M.Z.); congbq@buaa.edu.cn (B.C.)</p><p>Abstract: The high frequency transformer in single-phase full-bridge DC-DC converter is prone to</p><p>saturation because of the asymmetry of circuit parameters. Transformer saturation will increase</p><p>power consumption, accelerate the aging of winding insulation, and even damage power switches.</p><p>In order to prevent this risk, a DC bias suppression strategy is presented in this article, and the main</p><p>advantage of this strategy is that the problem of transformer saturation can be completely eliminated.</p><p>In this article, firstly, the DC bias and saturation mechanism of single-phase full-bridge DC-DC</p><p>converter are analyzed in detail, and the Maximum Integral Value of Volt-Second Product error</p><p>(MIVVSPE) is derived. Secondly, aiming at the saturation problem of single-phase full bridge DC-DC</p><p>converter, a new digital integral circuit is designed to evaluate the DC bias state of transformer, and a</p><p>DC bias suppression strategy is constructed to suppress the saturation of transformer. Furthermore,</p><p>different from the traditional current feedback control strategy, the DC bias suppression strategy</p><p>based on volt-second product error integral can be triggered before the transformer enters the</p><p>saturation state, and the transformer saturation can be completely suppressed. Finally, a 30 kW</p><p>single-phase full-bridge DC-DC converter for arc welding is established in lab. The experimental</p><p>results show that the new DC bias suppression strategy can effectively prevent the transformer from</p><p>entering the saturation state and improve the operation stability of single-phase full-bridge DC-DC</p><p>arc welding inverter.</p><p>Keywords: arc welding inverter; digital integrator; DC bias suppression strategy; high frequency</p><p>transformer; single-phase full-bridge DC-DC converter; saturation; volt-second product</p><p>1. Introduction</p><p>With the rapid development of power electronic technology, high efficiency low</p><p>voltage and high current arc welding inverter have been widely used in industrial pro-</p><p>duction [1,2]. The single-phase full-bridge DC-DC converter topology has higher power</p><p>processing capacity and makes better use of transformer core and power switch, which</p><p>fully meets the requirements of modern arc welding machine, and it has become a research</p><p>hotspot in the field of welding power supply [3–5].</p><p>The asymmetry of circuit parameters is one of the main reasons for DC bias of single-</p><p>phase full-bridge DC-DC converter. For example, the non-synchronization of the driving</p><p>signals and the difference of the turn on/off delay of IGBT will lead to unequal pulse width</p><p>in the transformer input voltage. Moreover, the difference in the on-state resistance of IGBT</p><p>will cause the asymmetry of the input voltage amplitude of the transformer. When the input</p><p>voltage of the transformer is asymmetrical in amplitude and pulse width, the volt-second</p><p>product on the primary side will enter an unbalanced state, and then the transformer will</p><p>operate in the DC bias state [6–8]. In most arc welding applications, the frequent short</p><p>circuit and no-load makes the DC bias more serious, which increases the risk of transformer</p><p>saturation and reduces the reliability of arc welding inverter [9].</p><p>In order to solve this problem, various methods have been proposed, which can</p><p>be divided into hardware topology optimization method [10–14] and software optimiza-</p><p>Electronics 2021, 10, 428. https://doi.org/10.3390/electronics10040428 https://www.mdpi.com/journal/electronics</p><p>https://www.mdpi.com/journal/electronics</p><p>https://www.mdpi.com</p><p>https://orcid.org/0000-0002-0164-767X</p><p>https://orcid.org/0000-0001-5627-085X</p><p>https://orcid.org/0000-0002-8999-8414</p><p>https://orcid.org/0000-0002-0961-0548</p><p>https://doi.org/10.3390/electronics10040428</p><p>https://doi.org/10.3390/electronics10040428</p><p>https://doi.org/10.3390/electronics10040428</p><p>https://creativecommons.org/</p><p>https://creativecommons.org/licenses/by/4.0/</p><p>https://creativecommons.org/licenses/by/4.0/</p><p>https://creativecommons.org/licenses/by/4.0/</p><p>https://doi.org/10.3390/electronics10040428</p><p>https://www.mdpi.com/journal/electronics</p><p>https://www.mdpi.com/2079-9292/10/4/428?type=check_update&version=2</p><p>Electronics 2021, 10, 428 2 of 20</p><p>tion method [15–24]. The hardware topology optimization method is to improve the</p><p>anti-DC bias ability by adjusting the structure and parameters of the hardware topology,</p><p>which belongs to the active suppression method. The “DC blocking capacitor” is usually</p><p>connected in series with the primary winding of the transformer to prevent DC bias. How-</p><p>ever, the DC bias suppression ability of the DC-blocking capacitor is proportional to the</p><p>capacity of the selected capacitor. When the capacity is small, the DC bias suppression</p><p>ability is stronger, but the partial voltage on the capacitor is also larger, which will reduce</p><p>the energy conversion efficiency of the inverter. When the capacity is large, it can only</p><p>restrain the DC bias caused by the slowly changing volt-second product imbalance, but has</p><p>little inhibitory effect on the DC bias caused by the fast-changing volt-second product</p><p>imbalance. In addition, It is also feasible to introduce an air-gap into the B− H circuit.</p><p>Because the permeability of the non-magnetic material is lower, it needs a higher H to</p><p>obtain the same B compared with the soft magnetic material. Therefore, the air-gap in-</p><p>creases the value of magnetization current and lowers the achievable flux density. However,</p><p>due to increased reluctance of an air gap the flux spreads into the surrounding medium</p><p>causing the flux fringing effect. It is generally an unwanted phenomenon which usually</p><p>increases proximity and eddy current loss in conductors located in the vicinity of the air</p><p>gap. The essence of the software optimization method is a closed-loop optimization control</p><p>strategy, where the control variable is the duty cycle of the full-bridge drive pulse, and the</p><p>feedback variable is the primary current of the transformer. When the transformer enters</p><p>the saturation state, a large current pulse will be generated in the primary current, and, if</p><p>the current pulse exceeds the reference current, the DC bias suppression strategy will be</p><p>triggered. Therefore, this method belongs to passive suppression method. In addition,</p><p>in the suppression strategy, the adjustment mode and depth of duty cycle do not depend</p><p>on the degree of saturation, and the feedback current is only used to trigger the adjustment</p><p>strategy; therefore, the software optimization method is blind and has poor reliability in</p><p>the treatment of transformer saturation.</p><p>The main contribution of this article is to analyze the saturation mechanism of trans-</p><p>former in detail, and the mathematical expression of the Maximum Integral Value of</p><p>Volt-Second Product Error (MIVVSPE) is derived. Then, on the basis of theoretical analy-</p><p>sis and mathematical derivation, a DC bias suppression method to prevent transformer</p><p>saturation is proposed. In the rest of the</p><p>paper, the mechanism of transformer satura-</p><p>tion is analyzed, and the MIVVSPE expression is derived in Section 2. The proposed DC</p><p>bias suppression strategy, including the circuit design method, is presented in Section 3.</p><p>Then, in Section 4, a 30 kW single-phase full-bridge DC-DC converter for arc welding is</p><p>established to verify the effectiveness of the suppression strategy. Finally, the conclusion of</p><p>the paper is drawn in Section 5.</p><p>2. Generation Mechanism of MIVVSPE</p><p>A circuit of the single-phase full-bridge DC-DC converter is depicted in Figure 1 [25].</p><p>It is composed of an inverter and a rectifier. The inverter consists of a high frequency</p><p>transformer TR and four IGBTs used as controllable switches Q1, Q2, Q3, and Q4, where,</p><p>in order to simplify the analysis process, the transformer is modeled by an ideal transformer,</p><p>and its magnetizing inductance Lm, the leakage inductances, and stray capacitances are</p><p>neglected. The transistors in each switching leg are driven by nonoverlapping voltages that</p><p>are out of phase by 180◦. The maximum duty cycle of the gate-to-source voltages is slightly</p><p>less than 44%. The waveforms of the gate-to-source voltages should not overlap each other</p><p>to avoid cross conduction [26]. When Q1 and Q4 are on, Q2 and Q3 are turned off, and the</p><p>current path is A (+) → Q1 → the primary side of transformer → Q4 → B (−), and the</p><p>voltage at the primary side is v1, Q2 and Q3 turn off, and bears forward voltage. When Q1</p><p>and Q4 are turned off, the voltage polarity at the primary side is reversed, and the stored</p><p>energy of the transformer is released through the freewheeling diode D3, capacitor Cin</p><p>and diode D2. At this moment, there is no voltage drop in Q2 and Q3, and Q1 and Q4 bear</p><p>forward voltage. In this process, the energy release is faster, and the voltage amplitude of</p><p>Electronics 2021, 10, 428 3 of 20</p><p>Q1 and Q4 will decay quickly. When the current on the primary side is zero, Q2 and Q3 are</p><p>turned on, and the current is reversed. When Q2 and Q3 are turned off again, the above</p><p>process will be repeated.</p><p>Q2 D2</p><p>Q1 Q3</p><p>Q4</p><p>D1 D3</p><p>D4</p><p>+</p><p>D6</p><p>D5</p><p>L</p><p>Cin</p><p>TR</p><p>N1:N2</p><p>A</p><p>B</p><p>+</p><p>−</p><p>+</p><p>−−</p><p>2i</p><p>1v</p><p>Inverter Rectifier</p><p>VTi</p><p>+</p><p>−</p><p>1Qv</p><p>2Qv</p><p>3Qv</p><p>4Qv</p><p>inv</p><p>outv</p><p>＋</p><p>－</p><p>＋</p><p>－</p><p>＋</p><p>－</p><p>＋</p><p>－</p><p>Cout</p><p>1Gv</p><p>4Gv2Gv</p><p>3Gv</p><p>Figure 1. The single-phase full-bridge DC-DC converter with a transformer center-tapped rectifier.</p><p>2.1. Saturation Mechanism Analysis</p><p>Figure 2 shows the key waveforms in the single-phase full-bridge DC-DC converter</p><p>with a transformer center-tapped rectifier for continuous conduction mode.</p><p>1ont</p><p>0</p><p>0</p><p>0</p><p>2ont</p><p>T</p><p>t</p><p>t</p><p>t</p><p>2T</p><p>2T</p><p>1v</p><p>( )b</p><p>( )a</p><p>0 t</p><p>0 t</p><p>2T</p><p>1V</p><p>1 2V</p><p>1V</p><p>1 2V</p><p>1V</p><p>1V−</p><p>( )c</p><p>( )d</p><p>( )e</p><p>T 3 2T</p><p>3 2T</p><p>T</p><p>3 2T</p><p>1ont</p><p>2ont</p><p>2ont</p><p>1ont 2ont</p><p>1ont</p><p>2 3,Q Qv v</p><p>1 4,Q Qv v</p><p>1 4,G Gv v</p><p>2 3,G Gv v</p><p>Figure 2. The key waveforms in the single-phase full-bridge DC-DC converter: (a,b) represent the</p><p>gating signals for Q1 and Q4, Q2, and Q3, respectively. (c,d) represent the across voltages of Q1 and</p><p>Q4, Q2, and Q3, respectively. (e) The voltage across the primary winding v1.</p><p>Electronics 2021, 10, 428 4 of 20</p><p>During the time interval 0 < t ≤ ton1, the switches Q1 and Q4, as well as the diode D5,</p><p>are on, whereas the switches Q2 and Q3, as well as the diode D6, are off, and the voltage</p><p>across the primary winding is:</p><p>v1 = vin − vQ1 − vQ4. (1)</p><p>Similarly, within time interval T/2 < t ≤ T/2 + ton2, the voltage across the primary</p><p>winding can be expressed as:</p><p>v1 = −</p><p>(</p><p>vin − vQ2 − vQ3</p><p>)</p><p>, (2)</p><p>where vQ1, vQ2, vQ3, and vQ4 represents the voltages across Q1, Q2, Q3, and Q4, respectively.</p><p>Assume that the IGBTs are ideal switches. Then, the on-resistance of IGBTs are equal,</p><p>such that vQ1 = vQ2 = vQ3 = vQ4; therefore, the amplitudes of v1 are equal during the</p><p>positive half-wave (Equation (1)) and the negative half-wave (Equation (2)). At the same</p><p>time, the turn on/off delay are the same, and there is no difference between gate drive</p><p>signals, so that the pulse width is also equal ton1 = ton2=D0T, where D0 = T/ton1 = T/ton2</p><p>represents the duty cycle of v1. Therefore, the volt-second product can be expressed as:</p><p>v̄ =</p><p>∫ T</p><p>0</p><p>v1dt =</p><p>∫ D0T</p><p>0</p><p>v1dt +</p><p>∫ (T/2+D0T)</p><p>T/2</p><p>v1dt=0. (3)</p><p>According to Equation (3), the magnetic induction can be expressed as:</p><p>B =</p><p>∫ T</p><p>0</p><p>v1</p><p>N1 AE</p><p>dt =</p><p>∫ D0T</p><p>0</p><p>v1</p><p>N1 AE</p><p>dt +</p><p>∫ (T/2+D0T)</p><p>T/2</p><p>v1</p><p>N1 AE</p><p>dt=0, (4)</p><p>where AE represents the cross-sectional area of the transformer core, and N1 represents the</p><p>number of turns of the primary side of the transformer.</p><p>However, in most applications, the circuit parameters of single-phase full-bridge</p><p>DC-DC converter are often asymmetric, such as the slight difference in gate drive signals,</p><p>turn-on/turn-off delay, and on-resistance of IGBTs. The asymmetry of the gate drive</p><p>signals or the difference in turn on/off delay of IGBTs will result in pulse width imbalance.</p><p>As shown in Figure 3a, the turn-off delay of Q1 and Q4 is greater than that of Q2 and Q3, so</p><p>that the positive pulse width is increased to ton1 = (D0 + ∆D)T. And the non-uniformity</p><p>in on-resistance of IGBTs will lead to the across voltages vQ1∼vQ4 to be unequal, according</p><p>to Equations (1) and (2), and it will result in amplitude unbalance. As shown in Figure 3b,</p><p>the on-resistance of Q1 and Q4 is less than that of Q2 and Q3, so that the positive amplitude</p><p>of v1 is increased to V1 + ∆V. If the above two unbalance conditions exist at the same</p><p>time, the voltage across the primary winding is shown in Figure 3c. Furthermore, when</p><p>the negative imbalance occurs, the change of the amplitude and pulse width of v1 in the</p><p>negative half wave is the same as that in the positive half wave of v1 in Figure 3.</p><p>1v</p><p>0</p><p>iT</p><p>1ont 2ont 1ont 2ont 2ont1ont</p><p>1v 1v</p><p>0 0t t t</p><p>( )c( )a ( )b</p><p>T</p><p>2T</p><p>T</p><p>2T</p><p>T</p><p>2T</p><p>1V</p><p>1V− 1V−1V−</p><p>1V 1V</p><p>iT iT</p><p>DT</p><p>DT</p><p>1V V+ </p><p>1V V+ </p><p>V V</p><p>Figure 3. The voltage across the primary winding under positive unbalanced conditions: (a) The pulse</p><p>width imbalance. (b) The amplitude unbalance. (c) Both pulse width and amplitude are unbalanced.</p><p>Electronics 2021, 10, 428 5 of 20</p><p>If the inverter meets the unbalance condition shown in Figure 3, the volt-second</p><p>product will produce an error in the switching period Ti:</p><p>v̄i =</p><p>∫ (D0+∆D)T</p><p>0 V1dt +</p><p>∫ (T/2+D0T)</p><p>T/2 (−V1)dt = V1 · ∆DT, Figure 3a</p><p>v̄i =</p><p>∫ D0T</p><p>0 (V1 + ∆V)dt +</p><p>∫ (T/2+D0T)</p><p>T/2 (−V1)dt = ∆V · D0T, Figure 3b</p><p>v̄i =</p><p>∫ (D0+∆D)T</p><p>0 (V1 + ∆V)dt +</p><p>∫ (T/2+D0T)</p><p>T/2 (−V1)dt = (V1 + ∆V)∆DT + ∆V · D0T, Figure 3c</p><p>. (5)</p><p>Therefore, the magnetic induction error in the switching period Ti can be expressed as:</p><p>Bi =</p><p>∫ T</p><p>0</p><p>v1</p><p>N1 AE</p><p>dt =</p><p>1</p><p>N1 AE</p><p>v̄i > 0. (6)</p><p>When Bi > 0, the B − t curve is no longer symmetrical about zero axis and shift</p><p>to the positive direction, and the transformer enters positive DC bias state. Moreover,</p><p>as the volt-second product error ∆v̄i in Equation (5) continues to accumulate in the positive</p><p>direction, the deviation degree of the B− t curve becomes larger and larger, and the DC</p><p>bias degree of transformer is also getting deeper and deeper. As shown in Figure 4b,</p><p>the positive maximum +Bm and negative maximum −Bm increase with the deviation of</p><p>B− t curve, where +Bm < +B′m < +B′′m, −Bm < −B′m < −B′′m.</p><p>mB+</p><p>B</p><p>t</p><p>( )b</p><p>mB−</p><p>0</p><p>mB+</p><p>mB+</p><p>mB−</p><p>mB−</p><p>mB+</p><p>B</p><p>t</p><p>mB−</p><p>0</p><p>/ 2T T</p><p>iT</p><p>1iT +iT</p><p>1iT +</p><p>iB</p><p>1iB +</p><p>( )a</p><p>Figure 4. The B− t curves: (a) ∆v̄i = 0, ∆Bi = 0. (b) ∆v̄i > 0, ∆Bi > 0.</p><p>According to the definition of magnetic permeability µ:</p><p>µ = B/H, (7)</p><p>where H represents the magnetic field intensity in the magnetic medium.</p><p>The current through the primary winding iQ is the sum of secondary current i2</p><p>converted to primary side N2 · i2/N1 and the magnetizing current iLm:</p><p>iQ =</p><p>N2 · i2</p><p>N1</p><p>+ iLm, (8)</p><p>where N2 is the number of turns in the secondary winding.</p><p>The excitation current iLm is measured under the no-load; therefore, iLm is a relatively</p><p>small current [26]. When iLm is small, B increases with the increase of iLm, and H is</p><p>proportional to iLm. However, when B increases to the saturation magnetic induction Bm, it</p><p>Electronics 2021, 10, 428 6 of 20</p><p>will not continue to increase,</p><p>while H will continue to increase, according to Equation (7),</p><p>and µ will decrease. Because iLm is inversely proportional to µ, when µ begins to decrease,</p><p>iLm will begin to increase sharply. According to Equation (8), a large current pulse ipeak will</p><p>be generated in iQ due to the sharp increase of iLm. When ipeak is greater than the rated</p><p>current of the IGBT, IGBT may be damaged due to over current. The corresponding B− iLm</p><p>curves is shown in Figure 5.</p><p>i</p><p>Lm</p><p>B</p><p>i</p><p>Lm</p><p>B</p><p>i</p><p>Lm</p><p>B</p><p>i</p><p>Lm</p><p>B</p><p>i</p><p>Lm</p><p>B</p><p>(c)</p><p>(e)</p><p>(b)</p><p>(d)</p><p>(a)</p><p>+B</p><p>r</p><p>-B</p><p>r</p><p>-B</p><p>r</p><p>(0,0)</p><p>(-B</p><p>m</p><p>,-I</p><p>m</p><p>)</p><p>(+B</p><p>m</p><p>,+I</p><p>m</p><p>)</p><p>(-B</p><p>m</p><p>,-I</p><p>m</p><p>)</p><p>(+B</p><p>m</p><p>,+I</p><p>m</p><p>)</p><p>+B</p><p>r +B</p><p>r</p><p>+B</p><p>r (+B</p><p>m</p><p>,+I</p><p>m</p><p>)</p><p>(+B</p><p>m</p><p>,+I</p><p>m</p><p>)</p><p>(+B</p><p>m</p><p>,+I</p><p>m</p><p>)</p><p>(-B</p><p>m</p><p>,-I</p><p>m</p><p>)</p><p>-B</p><p>r</p><p>-B</p><p>r</p><p>(-B</p><p>m</p><p>,-I</p><p>m</p><p>)</p><p>+B</p><p>r</p><p>-B</p><p>r</p><p>(-B</p><p>m</p><p>,-I</p><p>m</p><p>)</p><p>i</p><p>peak</p><p>i</p><p>peak</p><p>Figure 5. The B − iLm curves: (a) No DC Bias. (b) Positive DC Bias. (c) Positive Saturation. (d) Negative DC Bias.</p><p>(e) Negative Saturation.</p><p>When the transformer is in steady state, the corresponding B− iLm curve is symmetri-</p><p>cal about the zero point (0, 0), as shown in Figure 5a. However, if the transformer enters</p><p>the positive DC bias state, the symmetry center will move up from the zero point, as shown</p><p>in Figure 5b. And then, if the transformer enters the negative DC bias, the symmetry center</p><p>will move downward from the zero point, as shown in Figure 5d. When the transformer</p><p>enters the saturation state, the B− iLm curve is distorted and no longer symmetrical, such</p><p>as in Figure 5c, where the transformer enters the positive saturation state, and the B− iLm</p><p>curve is distorted in the first quadrant. Similarly, in Figure 5e, the transformer enters the</p><p>negative saturation state, and the B− iLm curve is distorted in the third quadrant.</p><p>2.2. Derivation of MIVVSPE</p><p>According to the above analysis, the current pulse ipeak produced in the primary</p><p>winding is the result of transformer saturation, not the cause. In fact, the root cause of the</p><p>transformer saturation is that the Integral Value of Volt-Second Product Error (IVVSPE)</p><p>eIVVSPE reaches and exceeds the Maximum Integral Value of Volt-Second Product Er-</p><p>ror (MIVVSPE).</p><p>Electronics 2021, 10, 428 7 of 20</p><p>Therefore, when the transformer enters the DC bias state, after N consecutive switch-</p><p>ing cycles, the Integral Value of Volt-Second Product Error eIVVSPE can be expressed as:</p><p>(eIVVSPE)N = v̄1 + v̄2 + · · ·+ v̄N = ∑N</p><p>i=1 v̄i. (9)</p><p>When the transformer enters the positive critical saturation state, eIVVSPE = MIVVSPE+,</p><p>if (eIVVSPE)N > MIVVSPE+ indicates that the transformer will enter the positive satura-</p><p>tion state. On the contrary, when the transformer will enter the negative critical saturation</p><p>state, eIVVSPE = MIVVSPE−, and, if (eIVVSPE)N < MIVVSPE−, means that the trans-</p><p>former will enter the negative saturation state.</p><p>3. Proposed Suppression Strategy</p><p>To suppress the DC bias and prevent transformer from entering saturation state, a volt-</p><p>second product error integral feedback control mode is proposed in this paper. Different</p><p>from the traditional current feedback control mode in References [15–24], the trigger con-</p><p>dition of this feedback control mode is the Integral Value of Volt-Second Product Error</p><p>eIVVSPE, and the DC bias suppression strategy can be triggered before transformer enters</p><p>the saturation state. When (eIVVSPE)N ≥ MIVVSPE+, the positive DC bias suppression</p><p>strategy will be triggered. When (eIVVSPE)N ≤ MIVVSPE−, the negative DC bias suppres-</p><p>sion strategy will be triggered. Therefore, the volt-second product error integral feedback</p><p>control method proposed in this paper belongs to a active suppression method.</p><p>3.1. Construction of Closed-Loop Controller</p><p>According to the previous analysis, a closed-loop control structure from control</p><p>variable (The duty cycle D0) to feedback variable (The Integral Value of Volt-Second</p><p>Product Error eIVVSPE) is constructed as shown in Figure 6.</p><p>mL</p><p>1L</p><p>DC bias suppression</p><p>strategy</p><p>Integrator</p><p>Circuit</p><p>Fig 7</p><p>Control</p><p>Strategy</p><p>Fig 11</p><p>L</p><p>inv 1v</p><p>VTi</p><p>Lmi</p><p>1i 2i 5D</p><p>6D</p><p>3v</p><p>2v</p><p>outv</p><p>3v</p><p>1 2:N N</p><p>0D</p><p>0D</p><p>1 3:N N</p><p>( )</p><p>1</p><p>N</p><p>IVVSPE iN i</p><p>e v</p><p>=</p><p>=</p><p>Cout</p><p>Figure 6. The block diagram of closed-loop control structure with DC bias suppression strategy.</p><p>3.2. Synchronous Sampling and Integrator Circuit</p><p>In this control diagram, the key of the DC bias suppression strategy is the integral</p><p>calculation of volt-second product error. Therefore, it is necessary to design an efficient</p><p>and reliable long-time no zero drift integrator to measure the DC bias degree. The analog</p><p>integrator has good dynamic response characteristics, but the zero drift of the integrated</p><p>Electronics 2021, 10, 428 8 of 20</p><p>operational amplifier seriously restricts the application of the analog integrator in the</p><p>long-time integration operation.</p><p>To solve this problem, a new long-time no zero drift integrator circuit is proposed</p><p>in Figure 7. In the signal sampling part, the transformer in arc welding inverter is used</p><p>to convert the high-frequency and high-voltage signal v1 into a low-voltage small signal</p><p>v3. In the part of integral operation circuit, the multi-thread parallel integral operation</p><p>logic is constructed in the Field-Programmable Gate Array (FPGA) to improve the cal-</p><p>culation speed of the eIVVSPE, so as to ensure the real-time performance of the DC bias</p><p>suppression strategy.</p><p>FPGA</p><p>Photocoupler</p><p>Photocoupler</p><p>PWM</p><p>Inverter</p><p>PWM</p><p>Rectifier</p><p>Signal Acquisition Signal Preprocessing Integral Operation</p><p>1</p><p>2</p><p>:</p><p>N</p><p>N</p><p>1</p><p>3</p><p>:</p><p>N</p><p>N</p><p>16-Bit, 105 MSPS,</p><p>Dual Analog-to-Digital</p><p>Converter(ADC)</p><p>101IO</p><p>102IO</p><p>103IO</p><p>1v</p><p>2v</p><p>3v</p><p>Analog-to-Digital Conversion Circuit</p><p>Zero Cross Detection Circuit</p><p>Rectifier and</p><p>Step-Down</p><p>Circuit</p><p>0D</p><p>Isolation</p><p>NPN</p><p>+3.3V</p><p>NPN</p><p>+3.3V</p><p>GND</p><p>GND</p><p>1dV</p><p>2dV</p><p>1</p><p>16</p><p>16</p><p>bit</p><p>parallel</p><p>input port</p><p>IO</p><p>IO</p><p></p><p></p><p></p><p></p><p>−</p><p></p><p>(a)</p><p>(b)</p><p>3v 0, , 15DB DB</p><p>Figure 7. Long-time no zero drift digital integrator circuit block diagram.</p><p>The long-time no zero drift digital integrator circuit is mainly composed of (1) Signal</p><p>Acquisition Circuit, (2) Signal Pre-processing Circuit, and (3) Integral Operation Circuit.</p><p>The main functions of each part are as follows:</p><p>1. Signal Acquisition Circuit:</p><p>The main function of this part is to sample the input voltage v1, where f1 = 20 kHz,</p><p>V1 = 537 V. Considering that the main transformer in the arc welding inverter can be</p><p>approximated to an ideal high precision voltage sensor. Therefore, a simple voltage</p><p>detection method is proposed to realize the accurate synchronous sampling for the v1,</p><p>in which an additional winding N3 is wound on the main transformer core to convert</p><p>v1 into a low-voltage small signal v3, where V3 = 12 V, N3 : N1 = 1 : 50. The actual</p><p>waveforms are shown in Figure 8.</p><p>CH1 represents the input voltage waveform v1 of the transformer, and the parameters</p><p>of v1 are: T = 50 us, D+ = D− = D0 = 10%, V1 = 537 V. CH3 represents the</p><p>output voltage waveform v3 of the additional winding, the parameters are: T = 50 us,</p><p>D+ = D− = D0 = 10%, V3 = 12 V. Therefore, there is a very good relationship</p><p>between the waveform v1 and v3, so that the DC bias state, including the direction</p><p>and depth, can be evaluated according to the change of v3.</p><p>2. Signal Pre-processing Circuit:</p><p>The main function of this circuit is to preprocess the sampled signal v3 to obtain the</p><p>DC pulse square wave signals Vd1, Vd2 and the 16-bit parallel signal DB [15 : 0].</p><p>Electronics 2021, 10, 428 9 of 20</p><p>The Zero Cross Detection Circuit (a) is used to convert v3 in the positive half-wave,</p><p>and the duty cycle of the output voltage signal Vd1 is equal to the positive half-wave of</p><p>v3. Similarly, the Zero Cross Detection Circuit (b) is used to convert v3 in the negative</p><p>half-wave, and the duty cycle of the output voltage signal Vd2 is equal to the negative</p><p>half-wave of v3.</p><p>Finally, the Analog-to-Digital</p><p>Conversion (ADC) Circuit is to perform the analog-to-</p><p>digital conversion on the amplitude of v3, the key parameters of the ADC module</p><p>are shown in Table 1. Considering that the analog input range of the ADC module is</p><p>0∼2.7 V p-p, it is necessary to rectify and step-down the input signal v3 to get the DC</p><p>pulse voltage waveform v′3, and then perform the analog-to-digital conversion, where</p><p>the output of the ADC module is a set of 16-bit parallel pulse sequences DB0, . . . , DB15.</p><p>The key waveforms are shown in Figure 9.</p><p>In Figure 9, CH1 is the waveform of the input voltage waveform v3, CH2 and CH3</p><p>represent the output voltage waveform Vd1 and Vd2 of the Zero Cross Detection Circuit</p><p>(a) and (b), respectively, and CH4 represent the output voltage waveform v′3 of the</p><p>Rectifier and Step-Down Circuit.</p><p>3. Integral Operation Circuit:</p><p>The main function of this part is to calculate the integral value of volt-second product</p><p>error. Vd1 and Vd2 is the output voltage of the Zero Cross Detection Circuit (a) and</p><p>(b), respectively. While the 16-bit parallel input ports IO1∼IO16 accepts the output</p><p>of the ADC module. In order to improve the computing speed of eIVVSPE, a parallel</p><p>operation logic is constructed in FPGA, and the parallel thread structure diagram is</p><p>shown in Figure 10.</p><p>CH1</p><p>CH3</p><p>v1(400V/div) T=50us</p><p>V1=537V</p><p>Time:25us/div</p><p>D+=10%</p><p>D-=10%</p><p>-V1=-537V</p><p>V3=12V</p><p>-V3=-12V</p><p>v3(10V/div)</p><p>Figure 8. The waveforms of v1(CH1) and v3(CH3).</p><p>Table 1. The main parameters of the high-speed parallel analog-to-digital converter (ADC).</p><p>Channels Sampling Rate Sampling Bits Input Voltage Range</p><p>1 105 MSPS 16 bit 0∼2.7 V p-p</p><p>Electronics 2021, 10, 428 10 of 20</p><p>Time:25us/div</p><p>CH1</p><p>CH2</p><p>CH3</p><p>CH4</p><p>v3(10V/div)</p><p>B</p><p>D</p><p>C</p><p>A</p><p>-V3=-12V</p><p>V3=12V</p><p>D+=10%</p><p>Ringing Waveform</p><p>Ringing Waveform</p><p>VD1=3.3V</p><p>Vd1(5V/div)</p><p>VD2=3.3V</p><p>v'</p><p>3(5V/div)</p><p>Vd2(5V/div)</p><p>T=50us</p><p>D-=10%</p><p>V'</p><p>3=2.5V</p><p>Figure 9. The key waveforms of the Signal Pre-processing Circuit.</p><p>iT</p><p>D−</p><p>3</p><p>2</p><p>4</p><p>1</p><p>D+</p><p>D−</p><p>D+</p><p>2dV →</p><p>1dV →</p><p>CLK →</p><p>1iT +</p><p>( )</p><p>( )</p><p>1</p><p>IVVSPE</p><p>IV i</p><p>i</p><p>iVSPE</p><p>e</p><p>e v</p><p>−</p><p>= +</p><p>( )</p><p>( )</p><p>1</p><p>1</p><p>IVVSPE</p><p>IVVSP</p><p>i</p><p>iiE</p><p>e</p><p>e v</p><p>+</p><p>+= +</p><p>0</p><p>15</p><p>DB</p><p>DB</p><p>→</p><p>1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p>  1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p>  1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p>  1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p> </p><p>Pn Nn Pn Nn</p><p>1</p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>+</p><p>= =</p><p>− </p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>= =</p><p>− </p><p>Figure 10. The structure diagram of the parallel operation for integral operation.</p><p>The parallel operation logic is composed of 4 threads:</p><p>• Thread 1. Duty cycle counter:</p><p>When the input variable Vd1 or Vd2 changes from Low to High, the 50 MHz</p><p>counter CLK starts counting, and then, if Vd1 or Vd2 changes from High to</p><p>Low, the count result is assigned to nP or nN , the Thread 1 termination. Con-</p><p>sidering that the frequency of the counter is 50 MHz and the switching fre-</p><p>quency is 20 kHz, so that nP and nN are a certain value, ranging from 0 to 2500.</p><p>Electronics 2021, 10, 428 11 of 20</p><p>For example, in Figure 10, the duty cycle of positive and negative half-wave is</p><p>D+ = D− = D0; therefore, the counting results of Vd1 and Vd2 is:{</p><p>nP = 2500 · D+ = 2500 · D0</p><p>nN = 2500 · D− = 2500 · D0</p><p>. (10)</p><p>• Thread 2. Amplitude calculation:</p><p>When Vd1 or Vd2 changes from Low to High, the Amplitude Calculation Thread</p><p>begins to work, the amplitude of v1 is calculated according to the output signals</p><p>DB0∼DB15 of ADC module. In the positive half-wave, the amplitude calculation</p><p>result is stored in register P(Pn1 , . . . , PnP), and then, in the negative half-wave,</p><p>the amplitude calculation result is stored in register N(Nn1 , . . . , NnN ),</p><p>In addition, in the full-bridge DC-DC converter, when the IGBT switches from</p><p>on state to off state, a Ringing Waveform will be generated in the output volt-</p><p>age waveform, as shown in Figure 9. However, the amplitude of the Ringing</p><p>Waveform is relatively small and symmetrical about the zero axis; therefore,</p><p>its influence on the calculation of the volt-second product error can be ignored.</p><p>In Figure 7, the input threshold voltage of the Photocoupler in Figure 7 is about</p><p>0.7V. Therefore, when v3 < 0.7V, the output of the photocoupler is in the cut-off</p><p>state, so that the Ringing Waveform in v3 is filtered out. As shown in Figure 9,</p><p>when IGBT is turned off, Vd1 or Vd2 will change from High to Low (A → B or</p><p>C → D), at this point, both Thread 1 and Thread 2 are terminated.</p><p>• Thread 3. Volt-second product error calculation:</p><p>When Thread 1 and Thread 2 are terminated, according to the definition of</p><p>volt-second product error in Equation (3), the volt-second product error in the</p><p>switching period Ti can be calculated:</p><p>v̄i=</p><p>nP</p><p>∑</p><p>j=1</p><p>Pj −</p><p>nN</p><p>∑</p><p>j=1</p><p>Nj. (11)</p><p>Assume that the amplitude of v1 in the positive and negative half waves is V1,</p><p>then Equation (11) can be further written as:</p><p>v̄i=</p><p>nP</p><p>∑</p><p>j=1</p><p>V1 −</p><p>nN</p><p>∑</p><p>j=1</p><p>V1 = 2500 · (D+ − D1)V1. (12)</p><p>• Thread 4. Integral of volt-second product error:</p><p>According to the calculation result of volt-second product error in Thread 3</p><p>and the definition of integral of volt-second product error in Equation (9),</p><p>the (eIVVSPE)i can be calculated:</p><p>(eIVVSPE)i = (eIVVSPE)i−1 + v̄i . (13)</p><p>3.3. Control Strategy</p><p>The block diagram of the control strategy for DC bias suppression strategy is shown</p><p>in Figure 11.</p><p>In Figure 11, the integral value of volt-second product error eIVVSPE is used to evaluate</p><p>the degree of DC bias, and the relationship between eIVVSPE and DC bias degree can be</p><p>defined as:</p><p>eIVVSPE ∈ (MIVVSPE+,+∞) : DC bias, Positive, Saturation</p><p>eIVVSPE ∈ (0, MIVVSPE+) : DC bias, Positive</p><p>eIVVSPE = 0 : No DC bias</p><p>eIVVSPE ∈ (MIVVSPE−, 0) : DC bias, Negative</p><p>eIVVSPE ∈ (−∞, MIVVSPE−) : DC bias, Negative, Saturation</p><p>. (14)</p><p>Electronics 2021, 10, 428 12 of 20</p><p>According to Equation (14), when the integral value of volt-second product error</p><p>eIVVSPE reaches and exceeds the Maximum Integral Value of Volt-Second Product Error</p><p>MIVVSPE+ or MIVVSPE−, the transformer enters the critical saturation state. In order</p><p>to prevent transformer from entering the saturation state, the DC bias suppression strategy</p><p>proposed in this paper will be triggered. The details are as follows:</p><p>The positive DC bias</p><p>suppression strategy</p><p>The negative DC bias</p><p>suppression strategy</p><p>Positive Saturation State</p><p>Negative Saturation State</p><p>Without Saturation</p><p>OROR</p><p>0D</p><p>( )</p><p>NIVVSPEe MIVVSPE+</p><p>( )</p><p>NIVVSPEe MIVVSPE−</p><p>( )S NIVV PEMIVVSPE e MIVVSPE− +  ( )</p><p>1</p><p>N</p><p>IVVSPE iN i</p><p>e v</p><p>=</p><p>=</p><p>Figure 11. The block diagram of the DC bias suppression strategy.</p><p>1. The positive DC bias suppression strategy.</p><p>When (eIVVSPE)i ≥ MIVVSPE+, the transformer will enter the positive critical satu-</p><p>ration state, in order to prevent the transformer from entering the positive saturation</p><p>state, the positive DC bias suppression strategy is triggered, and the corresponding</p><p>parallel thread sequence block diagram is shown in Figure 12.</p><p>iT</p><p>D−</p><p>3</p><p>2</p><p>4</p><p>1</p><p>D+</p><p>2dV →</p><p>1dV →</p><p>CLK →</p><p>1iT +</p><p></p><p>→</p><p>D D+ − </p><p>D D− + </p><p>1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p> </p><p>Pn Nn</p><p>1</p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>+</p><p>= =</p><p>− </p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>= =</p><p>− </p><p>0</p><p>15</p><p>DB</p><p>DB</p><p>→</p><p>0</p><p>15</p><p>DB</p><p>DB</p><p>→</p><p>Pn Nn</p><p>1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p>  1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p> </p><p>( )</p><p>( )</p><p>1</p><p>i</p><p>ii</p><p>IVVSPE</p><p>IVVSPE</p><p>e</p><p>e MIVV Pv S E+−</p><p>= + </p><p>( )</p><p>( )</p><p>1</p><p>1=0</p><p>IVVSPE</p><p>IV iVSP</p><p>i</p><p>E i</p><p>e</p><p>e v</p><p>+</p><p>+= +</p><p>1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p> </p><p>Figure 12. The block diagram of the parallel operation for positive DC bias suppression strategy.</p><p>In Figure 12, the integral value of volt-second product error increases positively, due</p><p>to the asymmetry of the circuit parameters in the full-bridge DC-DC converter, such as</p><p>the gate drive signal, the turn-on/turn-off delay, and the on-resistance in of the IGBTs,</p><p>so that (eIVVSPE)i ≥ MIVVSPE+. In order to reset (eIVVSPE)i quickly, and prevent</p><p>the transformer from entering the positive saturation state, the duty cycle of v1 in</p><p>the switching period Ti+1 is adjusted, where the positive duty cycle decreases by</p><p>D+ − ∆D, and the negative duty cycle increases by D− + ∆D, D+ = D− = D0;</p><p>Electronics 2021, 10, 428 13 of 20</p><p>therefore, nP=2500(D0 − ∆D), nN=2500(D0</p><p>+ ∆D), so that the integral value of volt-</p><p>second product error will be reset in the switching period Ti+1:</p><p>(eIVVSPE)i+1=(eIVVSPE)i +</p><p>2500(D0−∆D)</p><p>∑</p><p>j=1</p><p>Pj −</p><p>2500(D0+∆D)</p><p>∑</p><p>j=1</p><p>Nj = 0. (15)</p><p>It should be noted that, when using duty cycle modulation technology to achieve DC</p><p>bias suppression, large range step change of duty cycle within a switching period</p><p>should be avoided, especially in one direction; otherwise, the transient dc bias will</p><p>occur [23]. Therefore, in order to avoid this problem, the positive and negative half-</p><p>wave duty cycle is adjusted by equal amplitude in reverse direction, as shown in</p><p>Figure 12.</p><p>2. The negative DC bias suppression strategy.</p><p>When (eIVVSPE)i ≤ MIVVSPE−, the transformer will enter the negative saturation</p><p>state, in order to prevent the transformer from entering the negative saturation state,</p><p>the negative DC bias suppression strategy is triggered, and the corresponding parallel</p><p>thread sequence block diagram is shown in Figure 13.</p><p>iT</p><p>D−</p><p>3</p><p>2</p><p>4</p><p>1</p><p>D+</p><p>2dV →</p><p>1dV →</p><p>CLK →</p><p>1iT +</p><p>( )</p><p>( )</p><p>1</p><p>1 0</p><p>IVVSPE</p><p>IV</p><p>i</p><p>iiVSPE</p><p>e</p><p>e v</p><p>+</p><p>+= + =</p><p></p><p>→</p><p>D D+ +</p><p>D D− − </p><p>( )</p><p>( )</p><p>1</p><p>1</p><p>IVVSPE</p><p>IVVSP</p><p>i</p><p>iiE</p><p>e</p><p>e MIv VVSPE−</p><p>+</p><p>+= + </p><p>Pn Nn Pn Nn</p><p>1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p>  1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p>  1, ,</p><p>Pn</p><p>P</p><p>P P</p><p>=</p><p> </p><p>  1, ,</p><p>Nn</p><p>N</p><p>N N</p><p>=</p><p> </p><p> </p><p>0</p><p>15</p><p>DB</p><p>DB</p><p>→</p><p>0</p><p>15</p><p>DB</p><p>DB</p><p>→</p><p>1</p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>+</p><p>= =</p><p>− </p><p>1 1</p><p>NP</p><p>i</p><p>nn</p><p>j j</p><p>j j</p><p>v</p><p>P N</p><p>= =</p><p>− </p><p>Figure 13. The block diagram of the parallel operation for negative DC bias suppression strategy.</p><p>In Figure 13, the integral value of volt-second product error increases negatively,</p><p>and (eIVVSPE)i ≤ MIVVSPE−. In order to reset (eIVVSPE)i quickly, and prevent</p><p>transformer from entering the negative saturation state, the duty cycle of v1 in the</p><p>switching period Ti+1 is adjusted, where the positive duty cycle increases by D+ +∆D,</p><p>and the negative duty cycle decreases by D− − ∆D, D+ = D− = D0; therefore,</p><p>nP=2500(D0 + ∆D), nN=2500(D0 − ∆D), so that the integral value of volt-second</p><p>product error is reset in the switching period Ti+1:</p><p>(eIVVSPE)i+1=(eIVVSPE)i +</p><p>2500(D0+∆D)</p><p>∑</p><p>j=1</p><p>Pj −</p><p>2500(D0−∆D)</p><p>∑</p><p>j=1</p><p>Nj = 0. (16)</p><p>Electronics 2021, 10, 428 14 of 20</p><p>3.4. Innovation and Advantages</p><p>The innovation is that the main transformer in the full-bridge DC-DC converter is</p><p>used to measure high frequency and high voltage signal v1. Compared with the traditional</p><p>Hall sensor measurement method, due to the magnetic core of the main transformer is</p><p>large enough, the sampling method in Figure 7 has almost no signal distortion problem.</p><p>Therefore, the signal sampling method proposed in this paper simplifies the circuit structure</p><p>and improves the feedback accuracy.</p><p>The advantage is mainly reflected in the ability of the suppression strategy to restrain</p><p>the saturation problem. Compared with the traditional current feedback control method,</p><p>the suppression strategy can only be triggered after the transformer enters the saturation</p><p>state. However, the volt-second product error integral feedback control method proposed</p><p>in this paper will be triggered before saturation, which can completely eliminate the</p><p>saturation problem.</p><p>4. Experimental Verification</p><p>In order to verify the DC bias suppression strategy proposed in this article, a 30 kW</p><p>single-phase full-bridge DC-DC converter for the arc welding platform is established, as</p><p>shown in Figure 14.</p><p>Main</p><p>Transformer</p><p>Output</p><p>Inductance</p><p>Full Bridge</p><p>Rectifier</p><p>Bridge</p><p>PWM&Driver</p><p>ADC</p><p>FPGA</p><p>Synchronous</p><p>Sampling</p><p>Circuit</p><p>X</p><p>W</p><p>T</p><p>Z</p><p>Y</p><p>Figure 14. Experiment platform.</p><p>The relevant parameters of the experiment platform are shown in Table 2. And three</p><p>comparative experiments are given below, to illustrate the advantages of the proposed DC</p><p>bias suppression strategy.</p><p>Table 2. The main parameters of the arc welding platform.</p><p>Symbol Quantity Value</p><p>V1 Full-bridge converter input voltage 380</p><p>√</p><p>2 ≈ 537 V</p><p>Vo Rated output voltage 60 V</p><p>Io Rated output current 500 A</p><p>Po Rated power 30 kW</p><p>N1 : N2 Transformer turns ratio 3:1</p><p>fs Switching frequency 20 kHz</p><p>(0, MIVVSPE+) Positive DC bias correction region +400V1</p><p>(MIVVSPE−, 0) Negative DC bias correction region −400V1</p><p>4.1. No DC Bias Experiment</p><p>In this experiment, the full-bridge DC-DC converter is running in a steady state,</p><p>and the primary input voltage v1 is in a standard AC square wave, where D+ = D− =</p><p>D0 = 10%, V1 = 537 V. The key waveforms are shown in Figure 15.</p><p>Electronics 2021, 10, 428 15 of 20</p><p>CH1</p><p>CH2</p><p>-V1=-537V</p><p>VD1=3.3V</p><p>D=12%</p><p>D=12%</p><p>Vd2(5V/div)</p><p>T=50us</p><p>V1=537V</p><p>CH3</p><p>CH4</p><p>v1(600V/div)</p><p>Time:25us/div</p><p>VD2=3.3V</p><p>IVT=150A</p><p>-IVT=-150A</p><p>iVT(250A/div)</p><p>Vd1(5V/div)</p><p>Figure 15. The key waveform of inverter without DC bias.</p><p>CH1 represents the primary input voltage v1, CH2 and CH3 represents the output</p><p>signals Vd1 and Vd2, and CH4 is the current through the primary winding iQ.</p><p>4.2. DC Bias Experiment</p><p>In practical application, the duty cycle asymmetry is one of the main reasons for</p><p>the saturation fault of arc welding inverter. Therefore, to simulate this case, a duty cycle</p><p>disturbance variable D̂ = 4% is introduced into the negative half-wave from the switching</p><p>period T1, so that the negative half-wave duty cycle is increased to D− = 16%. The key</p><p>waveforms are shown in Figure 16.</p><p>CH1</p><p>CH2</p><p>CH3</p><p>T6 T8</p><p>T9T5T4</p><p>T7</p><p>I</p><p>max</p><p>Negative</p><p>DC</p><p>Bias</p><p>Region</p><p>Negative</p><p>Saturation</p><p>Region</p><p>Deep</p><p>Saturation</p><p>Region</p><p>v1(1000V/div)</p><p>CH4</p><p>iVT(300A/div)</p><p>D-=16%</p><p>D+=12%</p><p>d=3%</p><p>Vd1(5V/div)</p><p>Vd1(5V/div)</p><p>Ipeak8 Ipeak9</p><p>Ipeak7</p><p>Ipeak5</p><p>Ipeak6</p><p>Time:25us/div</p><p>Figure 16. The key waveform of negative DC bias.</p><p>Electronics 2021, 10, 428 16 of 20</p><p>In Figure 16, due to the introduction of D̂, the volt-second product error accumulates</p><p>in the negative direction, the transformer enters negative DC bias state, according to</p><p>Equation (10): {</p><p>nP = 2500 · D+ = 2500 · 12%= 300</p><p>nN = 2500 · D− = 2500 · 16%= 400</p><p>. (17)</p><p>Furthermore, according to Equations (12) and (17), the volt-second product error in</p><p>the switching period Ti can be calculated:</p><p>v̄i=</p><p>300</p><p>∑</p><p>j=1</p><p>V1 −</p><p>400</p><p>∑</p><p>j=1</p><p>V1 = −100V1, i = 1, 2, . . . . (18)</p><p>And then, according to Equations (9) and (18), the integral value of volt-second</p><p>product error in the switching period T4 is:</p><p>(eIVVSPE)4 = ∑4</p><p>i=1 v̄i = 4 · (−100V1) = −400V1. (19)</p><p>Since MIVVSPE− = −400V1, (eIVVSPE)4 ≤ MIVVSPE−. According to Equation (13)</p><p>and the proposed DC bias suppression strategy, we can predict that the transformer</p><p>will enter negative saturation state in T5, and a current pulse will be generated in the</p><p>negative half-wave of iQ and reach the maximum value Ipeak5 at the moment t = T/2+ D−.</p><p>When T/2 + D− < t < T, the switching period enters the negative half-wave continuous</p><p>flow stage, with the rapid attenuation of Ipeak5, a reverse induction electromotive force with</p><p>an equivalent duty cycle of ∆d ≈ 3% will be induced in the transformer, where the induced</p><p>electromotive force belongs to the positive pulse width. Therefore, the counting results of</p><p>Vd1 and Vd2 in T5 is:{</p><p>nP = 2500 · (D+ + ∆d) = 2500 · (12% + 3%)=2500 · 15% = 375</p><p>nN = 2500 · D− = 2500 · 16%= 400</p><p>. (20)</p><p>Then, the volt-second product error in the switching period T5 can be calculated:</p><p>v̄5=</p><p>nP</p><p>∑</p><p>j=1</p><p>Pj −</p><p>nN</p><p>∑</p><p>j=1</p><p>Nj =</p><p>375</p><p>∑</p><p>j=1</p><p>V1 −</p><p>400</p><p>∑</p><p>j=1</p><p>V1 = −25V1. (21)</p><p>Therefore, the actual integral value of volt-second product error in the switching</p><p>period T5 is:</p><p>(eIVVSPE)5 = ∑4</p><p>i=1 v̄i + v̄5 = 4 · (−100V1)− 25V1 = −425V1. (22)</p><p>According to the calculation results of Equation (22), (eIVVSPE)5 ≤ MIVVSPE−.</p><p>Moreover, in Figure 16, after the switching period T4, there is a spike current in the negative</p><p>half-wave of iQ. Therefore, the prediction for transformer saturation is valid.</p><p>4.3. DC Bias Suppression Experiment</p><p>In this experiment, compared with the traditional current feedback control mode,</p><p>the volt-second product error integral feedback control mode is better in suppressing the</p><p>DC bias and can completely eliminate the problem of transformer saturation.</p><p>1. The traditional current feedback control mode.</p><p>In the traditional current feedback control strategy,</p><p>if the current peak Ipeak caused by</p><p>transformer saturation is greater than the preset reference current Ire f , the traditional</p><p>DC bias suppression strategy is triggered, and then the duty cycle modulation method</p><p>is used to correct the saturation state. The experimental results are shown in Figure 17.</p><p>Electronics 2021, 10, 428 17 of 20</p><p>Time:25us/div</p><p>I</p><p>ref</p><p>Negative</p><p>Saturation</p><p>Region</p><p>Deep</p><p>Saturation</p><p>Region</p><p>CH1</p><p>CH3</p><p>T7 T8 T9 T10 T11</p><p>D+=12%</p><p>D-=16% d=3% D+ + D+=30%</p><p>Ipeak 7 Ipeak 8</p><p>Ipeak 9</p><p>iVT(250A/div)</p><p>v1(1000V/div)</p><p>Figure 17. The experimental results of the traditional current feedback control method.</p><p>In Figure 17, in order to compare the experimental results conveniently, the DC bias</p><p>condition is the same as experiment 2, the transformer enters negative DC bias state,</p><p>and when Ipeak9 is greater than Iref, the traditional DC bias suppression strategy is</p><p>triggered, and then, in the next two switching cycles, the positive half-wave duty cycle</p><p>increases to 30%, while the negative duty cycle decreases to 0%; thus, the DC bias</p><p>state is corrected.</p><p>2. The volt-second product error integral feedback control mode.</p><p>Under the same DC bias condition as experiment 2, if the transformer enters the</p><p>critical saturation state, the DC bias suppression strategy proposed in this paper is</p><p>applied, and the experimental results are shown in Figure 18.</p><p>Time:25us/div</p><p>T2 T3 T4 T5 T6</p><p>D+=12%</p><p>D-=16%</p><p>iVT(250A/div)</p><p>CH4</p><p>CH2</p><p>CH3</p><p>CH1</p><p>v1(600V/div)</p><p>Vd1(5V/div)</p><p>Vd2(5V/div)</p><p>Negative DC Bias Region</p><p>D+ + D=20%</p><p>D- - D=4%</p><p>Figure 18. The experimental results of the volt-second product error integral feedback control mode.</p><p>Electronics 2021, 10, 428 18 of 20</p><p>According to Equation (19), (eIVVSPE)4 = −400V1 = MIVVSPE_, the transformer</p><p>enters the negative critical saturation state. In order to prevent the transformer from</p><p>entering the saturation state, the negative DC bias suppression strategy proposed</p><p>in this paper is implemented. Therefore, in the switching cycle T5, the duty cycle</p><p>increment is:</p><p>∆D =</p><p>∣∣∣∣ (eIVVSPE)4</p><p>2 · 2500V1</p><p>∣∣∣∣ = ∣∣∣∣ −400V1</p><p>2 · 2500V1</p><p>∣∣∣∣ = 8%, (23)</p><p>and then, in the switching period T5, the positive duty cycle increases to D+ + ∆D =</p><p>20%, while the negative duty cycle decreases to D− − ∆D = 4%. According to the</p><p>Figure 18, there is no pulse current in the iQ waveform.</p><p>According to the experimental results in Figures 16–18, under the same DC bias condi-</p><p>tion, the DC bias suppression strategy proposed in this paper can completely eliminate</p><p>transformer saturation. Furthermore, when the DC bias suppression strategy is triggered,</p><p>the adjustment mode and depth in duty cycle is based on the preset of MIVVSPE− or</p><p>MIVVSPE+, while the size of MIVVSPE− and MIVVSPE+ is determined by balancing</p><p>the saturation risk and adjustment frequency. Therefore, the DC bias suppression strategy</p><p>proposed in this paper has very good robustness in suppressing transformer saturation</p><p>and can improve the anti-saturation ability of the single-phase full-bridge DC-DC converter.</p><p>5. Conclusions</p><p>A duty cycle modulation method for eliminating DC bias of single-phase full-bridge</p><p>DC-DC converter is proposed in this paper. The magnetic saturation problem of trans-</p><p>former is effectively eliminated, and the operation stability of arc welding inverter is</p><p>improved. Based on the detailed analysis of the saturation mechanism of transformer,</p><p>the conditions for realizing zero DC bias and the closed-loop control model for adjusting</p><p>the Maximum Integral Value of Volt-Second Product Error are given. In order to realize the</p><p>integral operation of volt-second product error of transformer input voltage signal, a novel</p><p>digital integration circuit with long-time no zero drift is proposed. When the Maximum</p><p>Integral Value of Volt-Second Product Error reaches the trigger condition of the DC bias</p><p>suppression strategy, the DC bias can be quickly corrected by adjusting the duty cycle of</p><p>the H-bridge power switch drive signal. The experimental results verify the effectiveness</p><p>of the method in preventing transformer saturation.</p><p>Author Contributions: Conceptualization, B.Q.; methodology, Y.Z. and B.Q.; software, Y.Z. and</p><p>M.Z.; validation, Y.Z.; formal analysis, Y.Z.; investigation, Y.Z.; resources, B.Q.; data curation, Y.Z.,</p><p>B.Q., M.Z., and B.C.; writing–original draft preparation, Y.Z.; writing–review and editing, B.Q.;</p><p>visualization, Y.Z.; supervision, B.Q. and B.C.; project administration, B.Q. All authors have read and</p><p>agreed to the published version of the manuscript.</p><p>Funding: This work was supported by the National Natural Science Foundation of China (Grant</p><p>No. U20B2031, Grant No. 52075024 and Grant No. 52075022).</p><p>Institutional Review Board Statement: All patients involved in this study gave their informed consent.</p><p>Informed Consent Statement: This paper has been approved for publication.</p><p>Data Availability Statement: The data provided in this paper are all true and effective, and have</p><p>been repeatedly verified in experiments.</p><p>Conflicts of Interest: The authors declare no conflict of interest.</p><p>Abbreviations</p><p>The following abbreviations are used in this manuscript:</p><p>MIVVSPE Maximum Integral Value of Volt-Second Product Error</p><p>IGBT Insulated Gate Bipolar Transistor</p><p>FPGA Field-Programmable Gate Array</p><p>Electronics 2021, 10, 428 19 of 20</p><p>References</p><p>1. Paul, A.K. Power electronics help reduce diversity of arc welding process for optimal performance. In Proceedings of the</p><p>2010 Joint International Conference on Power Electronics, Drives and Energy Systems & 2010 Power India, New Delhi, India,</p><p>31 December 2010; pp. 1–7.</p><p>2. Schupp, J.; Fischer, W.; Mecke, H. Welding arc control with power electronics. In Proceedings of the Eighth International</p><p>Conference on Power Electronics and Variable Speed Drives, London, UK, 1 September 2000; pp. 443–450.</p><p>3. Narula, S.; Singh, B.; Bhuvaneswari, G. Power Factor Corrected Welding Power Supply Using Modified Zeta Converter. IEEE J.</p><p>Emerg. Sel. Top. Power Electron. 2016, 4, 617–625. [CrossRef]</p><p>4. Paul, A.K. Simple means of resolving issues of AC-TIG welding equipment. In Proceedings of the 2016 IEEE International</p><p>Conference on Power Electronics, Drives and Energy Systems (PEDES), Thiruvananthapuram, India, 14–17 December 2016;</p><p>pp. 1–6.</p><p>5. Mishima, T.; Nakaoka, M. A Novel High-Frequency Transformer-Linked Soft-Switching Half-Bridge DC–DC Converter With</p><p>Constant-Frequency Asymmetrical PWM Scheme. IEEE Trans. Ind. Electron. 2009, 56, 2961–2969. [CrossRef]</p><p>6. Tan, N.M.L.; Abe, T.; Akagi, H. Design and Performance of a Bidirectional Isolated DC–DC Converter for a Battery Energy</p><p>Storage System. IEEE Trans. Power Electron. 2012, 27, 1237–1248. [CrossRef]</p><p>7. Costinett, D.; Seltzer, D.; Maksimovic, D.; Zane, R. Inherent volt-second balancing of magnetic devices in zero-voltage switched</p><p>power converters. In Proceedings of the 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition</p><p>(APEC), Long Beach, CA, USA, 17–21 March 2013; pp. 9–15.</p><p>8. Li, K.; Wang, Y.; Xu, J.; Wang, J.; Li, R.; Lv, C. A Novel Control Method for Eliminating DC Bias in Dual-Active-Bridge DC-DC</p><p>Converters. In Proceedings of the 2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC),</p><p>Shenzhen, China, 4–7 November 2018; pp. 1–6.</p><p>9. Jinhong, Z.; Wenlin, L.; Yaowu, S. Study on the dynamic process of arc welding inverter. In Proceedings of the IPEMC 2000.</p><p>Third International Power Electronics Motion Control Conference (IEEE Cat. No. 00EX435), Beijing, China, 15–18 August 2000;</p><p>pp. 308–311.</p><p>10. Kwon, S.; Yoo, D.; Jeong, G.; Korea, S. High-Efficiency AC-DC Switch Mode Power Supply Using Full-Bridge Converter Circuit.</p><p>Int. J. Control Autom. 2014, 7, 189–200. [CrossRef]</p><p>11. Krismer, F.; Kolar, J.W. Accurate power loss model derivation of a high-current dual active bridge converter for an automotive</p><p>application. IEEE Trans. Ind. Electron. 2009, 57, 881–891. [CrossRef]</p><p>12. Zhao, B.;Zhao, B.; Song, Q.; Liu, W.; Zhao, Y. Transient DC bias and current impact effects of high-frequency-isolated</p><p>bidirectional</p><p>DC–DC converter in practice. IEEE Trans. Power Electron. 2015, 31, 3203–3216. [CrossRef]</p><p>13. Mei, G.-H.; Liang, W.-J.; Liu, Y.-C.; Sun, Y.-Z.; Wang, D.; Mao, C.-X. Development of the DC current blocking device in</p><p>capacitor-resistor for transformer. High Volt. Eng. 2009, 35, 2581–2585.</p><p>14. Wang, Z.H.; Tong, X.; Qi, W.F. Blocking DC capacitor controllable opening and broken bridge suppression in transformer DC</p><p>magnetic bias. Trans. China Electrotech. Soc. 2013, 28, 120–126.</p><p>15. Hughes, A.; Drury, B. Electric Motors and Drives: Fundamentals, Types and Applications, 3rd ed.; Newnes: Burlington, VT, USA, 2005;</p><p>p. 199.</p><p>16. Gertsman, A.; Ben-Yaakov, S. Zeroing transformer’s DC current in resonant converters with no series capacitors. In Proceedings</p><p>of the 2010 IEEE Energy Conversion Congress and Exposition, Atlanta, GA, USA, 12–16 September 2010; pp. 4028–4034.</p><p>17. Baddipadiga, B.P.; Ferdowsi, M. Dual loop control for eliminating DC-bias in a DC-DC dual active bridge converter. In Proceedings</p><p>of the 2014 International Conference on Renewable Energy Research and Application (ICRERA), Milwaukee, WI, USA, 19–22</p><p>October 2014; pp. 490–495.</p><p>18. Dutta, S.; Bhattacharya, S. A method to measure the DC bias in high frequency isolation transformer of the dual active bridge DC</p><p>to DC converter and its removal using current injection and PWM switching. In Proceedings of the 2014 IEEE Energy Conversion</p><p>Congress and Exposition (ECCE), Pittsburgh, PA, USA, 14–18 September 2014; pp. 1134–1139.</p><p>19. Takagi, K.; Fujita, H. Dynamic control and performance of a dual-active-bridge dc–dc converter. IEEE Trans. Power Electron. 2017,</p><p>33, 7858–7866. [CrossRef]</p><p>20. Kohama, T.; Tokimatsu, S.; Shimamori, H. Elimination of magnetic saturation due to fast dynamic response in DC-DC converter.</p><p>In Proceedings of the 31st International Telecommunications Energy Conference. Incheon, Incheon, Korea, 18–22 October 2009;</p><p>pp. 1–6.</p><p>21. Cho, J.-H.; Park, K.-B.; Park, J.-S.; Moon, G.-W.; Youn, M.-J. Design of a Digital Offset Compensator Eliminating Transformer</p><p>Magnetizing Current Offset of a Phase-Shift Full-Bridge Converter. IEEE Trans. Power Electron. 2011, 27, 331–341. [CrossRef]</p><p>22. Ribeiro, H.S.; Borges, B.V. Solving Technical Problems on the Full-Bridge Single-Stage PFCs. IEEE Trans. Ind. Electron. 2014, 61,</p><p>2264–2277. [CrossRef]</p><p>23. Zhang, B.; Shao, S.; Chen, L.; Wu, X.; Zhang, J. Steady State and Transient DC Magnetic Flux Bias Suppression Methods for a</p><p>Dual Active Bridge Converter. IEEE J. Emerg. Sel. Top. Power Electron. 2019. [CrossRef]</p><p>24. Cuk, S.; Middlebrook, R.D. Advances in switched-mode power conversion part I. IEEE Trans. Ind. Electron. 1983, 1, 10–19.</p><p>[CrossRef]</p><p>http://doi.org/10.1109/JESTPE.2015.2500610</p><p>http://dx.doi.org/10.1109/TIE.2009.2013692</p><p>http://dx.doi.org/10.1109/TPEL.2011.2108317</p><p>http://dx.doi.org/10.14257/ijca.2014.7.6.19</p><p>http://dx.doi.org/10.1109/TIE.2009.2025284</p><p>http://dx.doi.org/10.1109/TPEL.2015.2445831</p><p>http://dx.doi.org/10.1109/TPEL.2017.2773267</p><p>http://dx.doi.org/10.1109/TPEL.2011.2158115</p><p>http://dx.doi.org/10.1109/TIE.2013.2271594</p><p>http://dx.doi.org/10.1109/JESTPE.2019.2947299</p><p>http://dx.doi.org/10.1109/TIE.1983.356697</p><p>Electronics 2021, 10, 428 20 of 20</p><p>25. Kazimierczuk, M.K. Full-Bridge PWM DC–DC Converter. In Pulse-Width Modulated DC-DC Power Converters; Publishing House:</p><p>Wright State University: Dayton, OH, USA, 2015; p. 330.</p><p>26. Heathcote, M.J.; Franklin, D.P. The J&P Transformer Book a Practical Tehnology of the Power Transformer Newnes; Butterworth-</p><p>Heinemann: Great Britain, UK, 1998.</p><p>Introduction</p><p>Generation Mechanism of MIVVSPE</p><p>Saturation Mechanism Analysis</p><p>Derivation of MIVVSPE</p><p>Proposed Suppression Strategy</p><p>Construction of Closed-Loop Controller</p><p>Synchronous Sampling and Integrator Circuit</p><p>Control Strategy</p><p>Innovation and Advantages</p><p>Experimental Verification</p><p>No DC Bias Experiment</p><p>DC Bias Experiment</p><p>DC Bias Suppression Experiment</p><p>Conclusions</p><p>References</p>