Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1585

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14.013P (a) The output is low when an even number of one's exists inputs Draw the truth table for three input even-parity checker Table 1 ABC (even-parity 0 0 0 0 010 011 0 0 0 11 0 0 From table write the Boolean expression Y Thus, the Boolean expression for three-input even parity checker is, Step 2 of 5 (b) The pull- down network can be most directly synthesized by expressing as function complemented variables ny complemented variables are appear the additional are required to generate The number NMOS transistors required for pull-down network is, transistors Draw the pull down network directly from the expression for y A A A A B B B B C Figure Step (c) The Boolean expression can be simplified follows The number NMOS transistors required for down network is, 1+(2x4)+1 =10 transistors Redrew the pull down network directly from the expression Y A A B B B B C C Figure 2 Step 4 of 5 (d) The pull up network dual pull down network The up network can be most directly synthesized by expressing function un-complemented variables and then applying variables the gates of the PMOS transistors variables are appear the additional inverters are required to generate the network Draw the up network for active-low output of even-parity checker B A B C B C A B Y Figure 3 Step Sketch the complete CMOS realization for active low output of even parity checker B A B C B A B Y A A B B B B C C Figure 4 Thus the complete CMOS realization for active-low even parity checker sketched as shown Figure