Digital Design_ Principles and Practices, Chegg Solution Manual_parte_250

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Step of 2 6.048E The letters of A to F is shown in Figure 1: a f b f b f f b f f g g g g e e e e e e d d A C D E F Figure Step of 2 The VHDL program for seven-segment decoder with the enhancements as follows: module Vr7seg SEGE,SEGF,SEGG); input A,B,C,D,ENHEX,ERRDT output reg SEGE,SEGF,SEGG reg 1:7 SEGS, SEGS_L; always @ (A or or C or D or ENHEX or ERRDT begin SEGS SEGS_L if not ENHEX) case ([D,C,B,A}) // Segment pattems abcdefg 0 SEGS_L 7'b0000001 1 SEGS_L 7'b1001111 2 SEGS_L 7'b0010010 3 7'b0000110 4 SEGS_L 7'b1001100 5 SEGS_L 7'b0100100 6 SEGS_L 7'b1100000 no tail 7 SEGS 7'b0001111 8 SEGS 7'b0000000 9 SEGS = 7'b0001100 no tail default = 'b1111111 end case else if not (ENHEX & ERRDT)) case ([D,C,B,A}) SEGS 7'b0000001 SEGS_L 7'b1001111 2: 7'b0010010 3 SEGS 7'b0000110 4 SEGS_L 7'b1001100 5 SEGS 7'b0100100 6 SEGS_L 7'b0100000 tail 7 SEGS_L 7'b0001111 8 SEGS_L 7'b0000000 9 SEGS_L 7'b0000100 tail 10 SEGS_L = 7'b0001001 A 11 SEGS_L 7'b0000000 SEGS_L = 7'b0110001 C SEGS_L 7'b0000001 D 14 SEGS_L = 7'b0110000 E 15 SEGS_L 7'b0100100 F default SEGS_L = end case else case ([D,C,B,A}) 0 SEGS_L 7'b0000001 1 SEGS_L 7'b1001111 2 SEGS_L 7'b0010010 3 SEGS 4 SEGS_L 7'b1001100 SEGS 7'b0100100 6 SEGS_L = 7'b0100000 tail 7 SEGS_L 7'b0001111 8 SEGS_L 7'b0000000 SEGS_L 7'b0000100 // tail SEGS_L 7'b0100100 A 11 SEGS_L 7'b0100100 SEGS_L 7'b0100100 C SEGS_L 7'b0100100 D SEGS_L 7'b0100100 E 15:SEGS_L 7'b0100100 default SEGS_L = 7 b1111111 end case SEGE,SEGF,SEGG SEGS end endmodule