Digital Design_ Principles and Practices, Chegg Solution Manual_parte_234

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Step 8 6.032E A possible definition of gate is is and B1 are but either A2 B2 is 0; Y2 is defined symmetrically. Find gate design for the BUT gate defined, that uses minimum number of transistors when realized CMOS. You may use inverting gates with up to inputs, or OAI transmission gates, or other transistor level tricks Write the output expressions (which need not be two level sums of and draw the logic Step BUT gate definition "Y1 is 1 if A1 and B1 are but either A2 B2 is 0: Y2 is defined Draw the following logical diagram of BUT gate A1 B1 A1 Y1 A2+B2 A2 B1 A1+B1 B2 Y2 A2.B2 Figure BUT gate logical diagram Step 8 Write the expressions for the outputs of BUT gate Write the expression in suitable form to implement in CMOS structure Step Simplify further Draw the following CMOS circuit to implement Y1. A1- -B1 A2 B2 A1B1 A2 B1 B2 Figure CMOS gate level design circuit for Y1 Step of Draw the following Logic Diagram for Y1=A1.B1(A2+B2) A2 B2 Figure 3: Logic Diagram for Write the expression Y2 suitable form to implement in CMOS structure Step of Simplify Y2 Draw the following CMOS circuit to implement A2 -B2 A1 B1 A2B2 A2 B2- B1- Figure CMOS gate level design for Y2 Step of 8 Draw the following Logic Diagram for A2 B2 Y2=(A2.B2)+(A1.B1) A1 B1 Figure 5: Logic diagram for Y2 Logic Diagram for Step Thus, the gate-level design for the BUT gate using CMOS are shown Figure 2, Figure The output expressions are The diagrams are shown Figure Figure