Digital Design_ Principles and Practices, Chegg Solution Manual_parte_214

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Step 1 of 2 6.10DP Consider the circuit given below: 74AHCT00 74AHCT00 74AHCT00 74AHCT00 OUT 74AHCT00 1 12 11 74AHCT00 1 8 4 13 U2 1 10 U2 1 3 2 IN Figure1 Step 2 of 2 For the circuit given in Figure1 both LOW-to-HIGH and HIGH-to-LOW transitions cause positive transitions on the output of three gates (alternate gates) and negative transitions on the output of other three gates. Hence, the total delay will be same in both the cases and is given by, (1) For Substitute 9 for and 9 for t,=3x9+3x9 =27+27 Thus, the minimum propagation delay from IN to OUT for the circuit is 54 ns . Since, and for a 74AHCT00 are equal, the same result is obtained using a single worst case delay of 9 ns.