Digital Design_ Principles and Practices, Chegg Solution Manual_parte_291

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Step 6.094E Write the following VHDL program for the device with functionality of 74x85. library IEEE; use IEEE.std_logic_1164.all; entity comparator is port ( altbin in STD_LOGIC; aeqbin agtbin STD_LOGIC; A (3 downto 0); B inSTD_LOGIC_VECTOR (3 downto agtbout out STD_LOGIC; aeqbout out STD_LOGIC; out STD_LOGIC end comparator; architecture behavioral of comparator is begin begin if(A=B and agtbin='0' and aeqbin='0' and altbin='0') then agtboutB and agtbin='0' and and altbin='0') then agtboutB and agtbin='0' and and altbin='1') then agtboutB and agtbin='0' and aeqbin='1' and altbin='0') then agtboutB and agtbin='1' and and altbin='0') then agtbout