Digital Design_ Principles and Practices, Chegg Solution Manual_parte_290

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Step 1 of 2 6.093E Write the following VHDL program for 8-bit equality and inequaltity checkers. library IEEE; use use entity check is port ( A, B: in STD_LOGIC_VECTOR (7 downto 0); EQ, GT: out STD_LOGIC ); end check; architecture check_arch of check is begin EQ B else '0'; end check_arch; Step 2 of 2 If EQ is 1 then the A and B are equal else they are not equal. Hence, both checkers need the same number of product terms. And even if the device does not have any output polarity control the output is same as the magnitude of the inputs are compared.