Digital Design_ Principles and Practices, Chegg Solution Manual_parte_275

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Step 1 of 1 6.073E 327-6-73E AID: 4132 I 11/05/2014 RID: 1988 22/05/2014 Refer to Table 6-49 from the textbook for the VHDL multiplexer program. Rewrite the VHDL program for 4-input, 8-bit multiplexer including with three-state output control input OE. library IEEE; use entity mux4in8bit is port ( OE : in STD_LOGIC; S: in STD_LOGIC_VECTOR (1 downto 0); -Select inputs A, B, C, D: in STD_LOGIC_VECTOR (7 downto 0); - Data bus inputs Y: out STD_LOGIC_VECTOR (7 downto 0)- Data bus output ); end mux4in8bit; architecture mux4in8p of mux4in8bit is begin process(OE,S, A, B, C, D) begin if(OE='1') then case S is when "00" Y A; when "01" Y