Digital Design_ Principles and Practices, Chegg Solution Manual_parte_255

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Step 1 of 3 6.053E The given Figure 5.3 below, which uses only 74x148 IC and no other gates to resolve priority among eight active-high inputs, 10 to 17, where 10 has the highest priority. Naming of input and output signals: A0-A2 are active high outputs. are active high inputs. If at least one input is asserted, then an AVALID output can be asserted. EO_L is used for cascading with the other Priority Encoder. EN is enable input to select among the many encodes. EO_L is asserted if EN is asserted but no request input is asserted. Step 2 of 3 Logic Diagram: In the below Figure 5.3 the circuit is a priority encoder where is having the highest priority that uses GS output which is a group select output where one or more request inputs are asserted, and has a Enable input that must be asserted for any of its outputs to be asserted. In this example IDLE output is asserted if no inputs are asserted. If at least one input is asserted, then an AVALID output can be asserted as shown in the Figure and EO_L is used for cascading with the other Priority Encoder. Step 3 of 3 The circuit diagram of encoder is shown in Figure 1: 74X148 0 EN 10_L A2_L A1_L Pri 14_L GS_L 15_L AVALID EO_L CASCADING 17_L Figure 1 Thus desired circuit is implemented.