Chegg Solutions for Microelectronic Circuits (Adel S Sedra, Kenneth C Smith) (Z-Library)_parte_1634

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Step of 14.053P The two devices are designed to have equal lengths. The ratio of the widths of the PMOS and NMOS transistors are, 180 3.7 0.75 45 3.7 Determine the value of equivalent capacitance C +Cw The gate drain overlap capacitance per micrometer of gate width is 0.4fF =(0.4)(0.75) =(0.4)(3) =1.2fF Step 8 The effective drain body capacitance per micrometer of gate width is 1.0fF =(1.0)(0.75) =0.75 fF =1.0(3) =3fF Determine the input capacitance of the load inverter. +Cgdov4 = =9.9375fF Step of 8 Determine the equivalent capacitance 84 =18.6875fF Determine the factor a, 2 7 4 2 = 7 4 3.3 3.3 2 = 1.75-0.6364+0.045 =1.726 Step Determine the factor 2 7 4 2 = 4 3.3 3.3 2 = 1.75-0.6364+0.045 1.726 Step 8 Determine the low to high propagation delay. W 1.726x18.6875x10⁻¹⁵ 0.75 =36.2ps Thus, the low to high propagation delay 'PLH is 36.2 ps 36.2 ps Step Determine the high to low propagation delay. 'PHL anC = Thus, the high to low propagation delay 'PHL is 36.2 ps 36.2 ps Step of Determine the propagation Substitute 36.2ps for 'PHL and 36.2ps for 'PLH 36.2 =36.2ps Thus, the propagation delay is 36.2ps Step of 8 The value of capacitance is proportional to the propagation delay. If the propagation delay increases by 50% then the capacitance also increases by 50% Determine the additional load capacitance. 100 50 =9.344 fF Thus, the additional capacitance load is 9.344fF