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Step 1 of 2 8.046E 74169 uses edge triggered J-K flip-flops which constitute to make it 4-bit binary counters. When Parallel Enable PE is LOW, the data on the inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur both CEP and CET must be LOW and PE must be HIGH; UID input then determines the direction of counting. For up counting UID=1 and for down counting UID=0 The terminal count output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the count-down mode or reaches 15 in the count-up mode. The TC output state is not a function of the Count Enable parallel (CEP) input level. Step 2 of 2 The counting sequence is 7, 6, 5, 4, 3, 2, 1, 0, 8, 9, 10, 11, 12, 13, 14, 15, 7, So, the count is initially preloaded to 7 (binary 0111) and the UID is made 0 for down counting. When the count reaches 0 (binary 0000) the parallel preloaded inputs becomes 8 (binary 1000) and now the up counting starts by making UID=1 Now, when the count reaches to 15 (binary 1111) the count starts from 7 (binary 0111) by loading the parallel inputs to 0111, and the desired count sequence is achieved. The circuit connection to the 74x169 is shown in Figure 1. P₀ P₁ P₂ P₃ 0 PE U/D 0 CEP TC 0 CET Clock Q₀ Figure 1 The parallel loading of 7 (binary 0111) and then 8 (binary 1000) is achieved by the XOR SSI IC package.