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Step 1 of 3 6.16DP Propagation delay is the summation of time a gate takes to reflect the change of voltage level (logic level) at the output side for a corresponding change at the input side and the time delay caused by the signal path. Refer Figure X6.9 and Table 6.2 in text book. The propagation delay is counted as follows, using table 6-2 for 74HCT86 Table 1 74HCT Typical Maximum Worst Part no 'PLH (ns) (ns) 'PLH (ns) (ns) (ns) (ns) '86(2 level) 13 13 40 40 40 40 '86(3 level) 13 13 40 40 40 40 Step 2 of 3 The smallest typical delay through one 74HCT86 is 13 ns (for HIGH to LOW transition). Use the rule of thumb which states that "minimum delay is equal to 1/4th to of typical delay. For a typical delay of 13 ns estimate the minimum delay to be 3.5 ns through one gate. Hence, the minimum delay at the output because of all the four gates is 14 ns. Total propagation delay based on our assumption at the input side is calculated by the propagation delay caused by the each gate in the circuit. Calculate the minimum propagation delay when the transition is from low to high. Typical = =(13+13+13+13) ns Thus, the minimum delay estimated is at one-fourth of this, 13 ns. Step 3 of 3 Calculate the minimum propagation delay when the transition is from high to low. Typical HIGH to LOW = =(13+13+13+13) ns The minimum delay estimated is at one-fourth of this, 13 ns. Hence, the estimated minimum propagation delay is 13 ns to 14 ns, which is approximately same as the typical propagation delay.