microinstruction important

Prévia do material em texto

1 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Chapter 4 Lecture 2 
The Microarchitecture Level 
Integer JAVA Virtual Machine 
 
This is a limited version of a hardware implementation to execute the JAVA programming 
language. 
 2 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
The Data Path 
PC Program Counter: Access Data 
in Method Area 
MBR Memory Branch Register: 
Instruction and Instruction 
Parameter 8-bit register 
MAR Memory Address Register: 
Address for external data 
memory space 
MDR Memory Data Register: Data 
input and output to external 
memory 
SP Stack Pointer: Address pointer 
to the top of the system stack 
LV Local Variable: Address pointer 
to the bottom of the local 
variable frame 
CPP Constant Pool Pointer: Pointer 
to the bottom of the constant 
pool 
TOS Top Of Stack: The data value at 
the top of the stack 
OPC Old PC: A scratch or 
temporary register 
typically used for 
branching and the 
temporary storage of old 
PC values in 
computations 
H Holding: A temporary register 
for holding one of the two ALU 
operands 
 3 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Data Movement using Registers 
Loading a Register 
1) MAR provide an address to receive data 
2) MDR inputs data 
3) MDR data is placed on the B bus 
4) B Bus Data passed through ALU to the C Bus 
5) C Bus Data is written into a register 
Saving a Register 
1) Register data is placed on the B bus 
2) B Bus Data passed through ALU to the C Bus 
3) C Bus Data is written into the MDR 
4) MDR data is written at the MAR memory address 
Note: The MAR must hold the correct address value 
Executing a one operand instruction 
1) Register data is placed on the B bus 
2) B Bus Data is modified by the ALU based on the ALU control and output to the C Bus 
3) C Bus Data is written into the appropriate register 
Executing a two operand instruction 
1) Register data is placed on the B bus 
2) B Bus Data passed through ALU to the C Bus 
3) C Bus Data is written into the H register 
4) Register data is placed on the B bus 
5) A & B Bus Data is modified by the ALU based on the ALU control 
6) C Bus Data is written into the appropriate register 
 
 4 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Arithmetic Logic Units (ALU) 
 
Cascadeable 1-Bit ALU: 
AND, OR, INV, Binary Added with Cin and Cout 
Ripple ALU 
 
An 8-bit ALU based on 1-bit ALU building blocks 
 
 5 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Ripple ALU Functions (Your extra homework assignment) 
Number of possible functions: 5 control bits (2^5) plus a carry bit (x2 for adder functions) 
 
 
One-operand instructions do not enable the A Bus input: 
B, NOT(B), B+1, B-1, 0, 1, -1 
Two-operand instructions enable both the A and B Bus inputs: 
A+B, A+B+1, B-A, A AND B, A OR B 
 
 6 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
For a complete table 
F0 F1 ENA ENB INVA INC Function 
AND Logic 
0 0 0 0 0 X 0 
0 0 0 0 1 X 0 
0 0 0 1 0 X 0 
0 0 0 1 1 X B 
0 0 1 0 0 X 0 
0 0 1 0 1 X 0 
0 0 1 1 0 X A AND B 
0 0 1 1 1 X #A AND B 
OR Logic 
0 1 0 0 0 X 0 
0 1 0 0 1 X FFFFs 
0 1 0 1 0 X B 
0 1 0 1 1 X FFFFs 
0 1 1 0 0 X A 
0 1 1 0 1 X #A 
0 1 1 1 0 X A OR B 
0 1 1 1 1 X #A OR B 
INV Logic 
1 0 0 0 0 X FFFFs 
1 0 0 0 1 X FFFFs 
1 0 0 1 0 X #B 
1 0 0 1 1 X #B 
1 0 1 0 0 X FFFFs 
1 0 1 0 1 X FFFFs 
1 0 1 1 0 X #B 
1 0 1 1 1 X #B 
ADD Numeric 
1 1 0 0 0 0 0 
1 1 0 0 0 1 1 
1 1 0 0 1 0 -1 
1 1 0 0 1 1 0 
1 1 0 1 0 0 B 
1 1 0 1 0 1 B+1 
1 1 0 1 1 0 B-1 
1 1 0 1 1 1 B 
1 1 1 0 0 0 A 
1 1 1 0 0 1 A+1 
1 1 1 0 1 0 #A 
1 1 1 0 1 1 -A 
1 1 1 1 0 0 A+B 
1 1 1 1 0 1 A+B+1 
1 1 1 1 1 0 B-A+1 
1 1 1 1 1 1 B-A 
 
 7 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Data Path Timing (glitch based author’s concept) 
 
Text Book Latch Based Concept 
“The load should be edge triggered and fast, so that even if some of the input registers are 
changed, the effects will not be felt on the C bus until long after the registered have been 
loaded.” 
“Also on the rising edge of the pulse, the register driving the B bus stops doing so, in preparation 
for the next cycle.” 
He has timing problems and a concern for a race condition … BAD DESIGN PRACTICES! 
 8 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Alternate “Super-Synchronous” Design Timing Cycle – clean and easy 
Positive Clock Edge 
w x y z 
Negative Clock Edge 
w x y z 
Possible Super-Synchronous Operation 
w Control signal propagation to the components in the CPU 
x A and B Bus propagation times 
y ALU and Shifter input to output propagation times 
z C Bus propagation time and register set-up time 
The subcycles are asynchronous propagation times (if something can complete faster it does, but 
time is allocated to operate slower or at the worst case timing) 
The subcycles are implicit in how signals have to flow … not explicit clock or gate periods 
The super-synchronous operation is consistent with our previous mux-register design! 
 9 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Data Path Propagation 
 
w x y z 
w 
x 
y 
z 
Clock edge 
w
w 
z and next 
clock 
 10 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Memory Operation (Two ports, one for data and one for instructions) 
 
Data Memory Port 
MAR Memory Address Register: Address for external data memory space 
MDR Memory Data Register: Data input and output to external memory 
32-bit Registers – internal word access and word addressing 
 
MAR addressing of 32-bit words using an external Byte wide Memory Addressing Bus 
 
Note: all external data memory is assumed to be perfectly aligned on 4-Byte boundaries. 
Note: The internal machine address is based on 32-bit words, not memory Bytes. 
 
 11 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1.Instruction Memory Port 
 
PC Program Counter: Access Data in Method Area (32-bit register) 
MBR Memory Branch Register: Instruction and Instruction Parameter (8-bit register) 
Byte can be read with or without sign extension (a signed or unsigned integer). 
The instructions consist of 8-bit pieces that are addresses by the PC and loaded into the MBR. 
Reading memories (Cycle latency delays) 
RD#
Add Bus
CPU CLK
Mem Data
MDR
MAR
Data Bus
@MAR Available
Read Latency
 
External Memory Read Latency 
For reads, the data isn’t internally available during the first clock period. It is registered on the 
second. 
For writing, data can output on the same cycle as a write command (WR#). 
(The MDR can provide an output during the first clock period) 
 12 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Reading followed by write memories (Cycle latency delays) 
RD#
Add Bus
CPU CLK
Mem Data
MDR
MAR
Data Bus
@MAR Available
WR#
MDR
Read Latency Write Latency
MAR
Data Bus
 
Accessing Read Data Before a Write (turn around limitation) 
 
 13 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Microinstructions 
Now that the functions have been defined, what about the control. 
Multiple clock cycles execute each instruction: 
 what occurs on each and every clock cycle is defined by a microcontroller with a 
microPC (MPC or PC ) and a microinstruction (MIR or IR) 
 MPC or PC MicroProgram Counter: Internal microcode address register 
 MIR or IR Microinstruction Register: Internal instruction used to control the IJVM 
Each JAVA instruction is translated or expanded into a sequence of microinstructions 
More complex JAVA instructions allowed 
 
IJVM Block Diagram 
 14 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Elements of the microinstructions (All instructions whether explicit or implicit): 
 Operands what is the operand that goes on the B Bus 
 Execution what ALU and shift operation is to occur 
 Results where are the execution results to be stored from the C Bus 
and does it involve memory operations 
 Program Control where is the next instruction determined 
 
Like any “assembly language” instruction: 
Opcode (execution), Operands, Results, next Instruction 
 
 
IJVM Block Diagram 
 15 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
MicroInstructions based on MicroProgram Counter and MicroInstruction Register 
MicroInstruction Register (MIR) Content 
 
The MIR Fields: B Bus, ALU & Shift, C Bus and Ext. Mem., Next MPC 
MIR bit width is: 9+3 = 12-bit next instruction with 8+9+3+4 = 24-bits data paths. Total 36-bits! 
B Field: Encoded selection of register file output to B Bus (only 1 at a time) 
Mem Field: External memory control selection for data and instructions (RD#, WR#,Festch) 
C Field: Bit selection of which registers to write from the C Bus (multiple writes possible) 
ALU Field: Control bits for the ALU and Shift execution elements 
JAM: Microprogram control flow bits; allow branching, explicitly or in new instructions 
Addr: The address to be combined to create the MPC and define the next 
Microinstruction 
 
Encoded B-Bus Selection with a 4:16 Decoder 
B-Bus Instruction Field 
B-Bus Register Selected 
0000 MDR 
0001 PC 
0010 MBR (signed) 
0011 MBRU (unsigned) 
0100 SP 
0101 LV 
0110 CPP 
0111 TOS 
1000 OPC 
1001 Unassigned 
1010 Unassigned 
1011 Unassigned 
1100 Unassigned 
1101 Unassigned 
1110 Unassigned 
1111 Unassigned 
 16 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Example: adding TOS with a memory value @SP-1 and writing back to @SP-1 
MAR=SP-1; rd; % read delay of one clock cycle required 
H=TOS; % use delay to load H register 
MDR=H+MDR; wr; % crate the sum and write on the following clock cycle 
 
 
 17 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Example: adding TOS with a memory value @SP-1 and writing back to @SP-1 
RD#
MAR
Address Bus
CPU CLK
Memory 
Data Bus
MDR
MAR
WR#
SP-1
@SP-1
@SP-1
@SP-1+H
Write 
LatencyRead Latency
MAR=SP-1; rd; % read delay of one clock cycle required
H=TOS; % use delay to load H register
MDR=H+MDR; wr; % crate the sum and write on the following clock cycle
H TOS
@SP-1+H
MDR
H
(1) (2) (3)
 
 18 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Getting the Next Instruction (Microinstruction and IJVM instruction) 
The MPC must have the absolute address of every microinstruction for every clock cycle. 
How does the MPC get updated? 
(1) The next microinstruction address comes from the MBR. (MPC msb=0) 
(2) The next microinstruction address comes from the MIR (MPC msb=0) 
(3) The next microinstruction is a combination of the MIR and JAM bit as the msb 
 
 
Next Instruction Detailed Implementation 
(1) The next microinstruction address comes from the MBR. 
JAMN=0, JAMZ=0, JAMC =1, NEXT_ADDRESS=000h, 
MPC= (MBR AND JAMC) OR NEXT_ADDRESS 
(2) The next microinstruction address comes from the MIR 
JAMN=0, JAMZ=0, JAMC =0, NEXT_ADDRESS=###h, 
MPC= NEXT_ADDRESS 
(3) The next microinstruction is a combination of the MIR and JAM bit as the msb 
JAMC =0, NEXT_ADDRESS=###h, JAMN or JAMZ set to 1 
MPC[7:0]= NEXT_ADDRESS[7:0] 
MPC[8]= (JAMZ AND Z) OR (JAMN AND N) OR NEXT_ADDRESS[8] (opt) 
(1) 
(2&3) 
(3) 
 19 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Next Instruction Detailed Logic Implementation 
MPC[8]= (JAMZ AND Z) OR (JAMN AND N) OR NEXT_ADDRESS[8] (opt) 
MPC[7:0]= (MBR[7:0] AND JAMC) OR NEXT_ADDRESS[7:0] 
Note: address bit MPC[8] is only for “branching decisions” as shown (0= false, 1=true) 
If more MicroInstructions are required, the options shown could be used. 
256 control store locations allocated for branching is not needed. 
Example Using JAMZ 
 
Figure 4-7. A microinstruction with JAMZ set to 1 has two potential successors. 
Instruction fetch – this is an instruction “prefetch for the next instruction” 
PC=PC+1; fetch; goto(MBR); % read next instruction and execute 
 
 20 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
IJVM Programmer’s Model and Organization 
 
Method Area External Program Memory containing the IJVM program to be 
executed. The internal PC is apointer in the Method Area to the next 
instruction to be executed. The method area is accessed using the PC 
with 8-bit instructions and parameters loaded into the MBR. 
Constant Pool External Data Memory containing compiled constants (e.g. values, 
strings, pointers, etc.) required by the Methods to execute programs. 
Local Variable Frame External Data Memory allocated for the storage of variables for the 
method being executed. When a method is invoked, a local variable 
frame of predefined size is established (allocated) for all local 
variables used by the method 
Operand Stack External Data Memory used for the storage of temporary operands that 
are placed on the stack. The Operand Stack maximum size is known 
when a Method is invoked. This allows proper memory allocation and 
deallocation. 
 
Note on the IJVM Theory of operations: 
Data memory is accessed using an indexed offset from known internal register memory pointers 
(i.e. LV local variable, CPP constant pool) 
The local variable frame includes both the local variables and the operand stack. Note that since 
the maximum size of the stack is known, the maximum size of the local variable frame is known. 
 21 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Simplified Example of Doing Arithmetic: a1 = a2 + a3 
 
________ 
________ 
________ 
Figure 4-9. Use of an operand stack for doing an arithmetic computation. 
Read a2; Push 
Read a3;Push 
ADD; 
Pop; Write a1 
Please review HP Calculator or “reverse Polish”, stack based arithmetic 
(more coming in section 5.4.8) 
 
 
Simplified Example of Local Variable Frames 
 
Figure 4-8. Use of a stack for storing local variables. (a) While A is active. (b) After A calls B. 
(c) After B calls C. (d) After C and B return and A calls D. 
Process A Active 
Process A Calls Process B; Process B has 4 local variables 
Process B Calls Process C; Process C has 2 local variables 
Process C Completes and returns to B 
Process B Completes and returns to A 
Process A Calls Process D; Process D has 5 local variables 
Inherent “temporary” memory allocation and deallocation using stack frames! 
 22 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
IJVM Basic Instruction Set Architecture 
Hex Mnemonic Meaning 
 Basic Stack Operations Data Movement Instructions 
0x10 BIPUSH byte Push byte onto stack 
0x13 LDC_W index Push constant from constant pool onto stack 
0x15 ILOAD varnum Push local variable onto stack 
0x36 ISTORE varnum Pop word from stack and store in local variable 
0x57 POP Delete word on top of stack 
0x59 DUP Copy top word on stack and push onto stack 
0x5F SWAP Swap the two top words on the stack 
 
 Operand Arithmetic ALU Instructions 
0x60 IADD Pop two words from stack; push their sum 
0x64 ISUB Pop two words from stack; push their difference 
0x7E IAND Pop two words from stack; push Boolean AND 
0x80 IOR Pop two words from stack; push Boolean OR 
0x84 IINC varnum const Add a constant to a local variable 
 
 Branching Flow Control Instructions 
0x99 IFEQ offset Pop word from stack and branch if it is zero 
0x9B IFLT offset Pop word from stack and branch if it is less than zero 
0x9F IF_ICMPEQ offset Pop two words from stack; branch if equal 
0xA7 GOTO offset Unconditional branch 
 
 Misc. Other Instructions 
0x00 NOP Do nothing 
0xC4 WIDE Prefix instruction; next instruction has a 16-bit index 
 
 Special Operations Subroutine/ISR Control Instructions 
0xB6 INVOKEVIRTUAL disp Invoke a method 
0xAC IRETURN Return from method with integer value 
The operands byte, const, and varnum are 1 byte. 
The operands disp, index, and offset are 2 bytes. 
20 Instructions shown (more are possible) 
 10 Instructions with just opcodes 
 3 Instructions requiring 1 byte 
 7 instructions requiring 2 bytes 
 
 23 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Compiling JAVA to IJVM and operating with the stacks 
 
(a) A Java fragment. (b) Java assembly language. (c) The IJVM program. 
 
 
The stack after each instruction. 
 24 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Implementing IJVM Instructions 
A sequence of microinstructions is required to execute each IJVM instruction or 
macroinstruction. The sequence for each instruction is predefined and the microprogramming 
code is stored in internal microcode memory. 
The microinstructions may be thought of as a micro-assembly language (MAL). 
The microcode is defined using a symbolic language or pseudo-code that identify every MIR 
field required for each and every microinstruction. The microinstruction code must define every 
internal CPU action that occurs during an internal microinstruction cycle. 
This may be referred to as register transfer notation (RTN) or register transfer language 
(RTL) 
The symbolic microcode consists of a label, an operation, and comments. 
 The label is used to assign the address of the microinstruction in the microcode space. 
 The operation field symbolically represents all MIR control functions. 
 The comment field is used to describe the code, machine state, or machine operations. 
Allowed ALU Operations 
 
Source and Destination: any allowable B-bus or C-bus registers in the MIR. 
Note: this symbolic code defines the A-bus, B-bus, C-bus, and ALU MIR fields. For a complete 
instruction, we must also include; fetch, memory read and write, the JAMX bits and the next 
microinstruction field. 
Illegal Ops: (1) subtraction is SOURCE-H and (2) only one value on B-Bus, use H register 
 25 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Conceptual Execution 
 
 
Instruction Operation Example 
IADD (0x60h) 
Pop two words from stack; push their sum 
 26 of 32 ECE 3570 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
JAVA: IADD 
MAL: main1 and iadd1(0x015) to iadd3 
 
Things to do: 
Increment the PC to the next instruction and fetch the next instruction. 
Use the TOS register value (avoid reading the stack @SP) and move it to the H register. 
Decrement the SP (SP=SP-1), request the data at the new SP (using MAR=SP) and read in the 
data (to the MDR) at the new SP location. 
Add the two registered values (H and MDR). Put the result into TOS register and write it to the 
memory at the new SP address (MDR using MAR=SP). 
Note: there are memory access delays that must also be accounted for! 
 
Label Operations Comments 
main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode (0x60h); 
get next byte; dispatch 
iadd1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
iadd2 H = TOS H = top of stack 
iadd3 MDR = TOS = MDR + H; wr; 
goto main1 
Add top two words; write to top of 
stack 
main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode (0x60h);get next byte; dispatch 
 
 
 
 27 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, 
Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
Executing the JAVA IADD Instruction in Mic-1 
Cycle 0 1 2 3 4 5 
MPC main1 iadd1 iadd2 iadd3 main1 
INST PC= PC+1; 
fetch; goto 
(MBR) 
MAR= SP = 
SP-1; rd 
H= TOS MDR= TOS= 
MDR+H; wr; 
goto main1 
PC= PC+1; 
fetch; goto 
(MBR) 
 
Next MPC gt (iadd1) iadd2 iadd3 main1 gt (MBR) 
PC 
fetch 
PC PC+1 
fetch 
 
MBR iadd1 INST 
MAR 
rd/wr 
 SP-1 
rd 
SP-1 SP-1 
wr 
 
MDR (@SP-1) MDR+H 
SP SP SP-1 
LV 
CPP 
TOS (@SP) MDR+H 
H TOS (@SP) 
 
 
 
 28 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
The IJVM MAL 
IJVM Microinstruction 1 (MIC-1) Architecture Language (1 of 4) 
main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; 
dispatch 
nop1 goto main1 Do nothing 
iadd1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
iadd2 H = TOS H = top of stack 
iadd3 MDR = TOS = MDR + H; wr; 
goto main1 
Add top two words; write to top of 
stack 
isub1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
isub2 H = TOS H = top of stack 
isub3 MDR = TOS = MDR ��H; wr; 
goto main1 
Do subtraction; write to top of 
stack 
iand1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
iand2 H = TOS H = top of stack 
iand3 MDR= TOS = MDR AND H; wr; 
goto main1 
Do AND; write to new top of stack 
ior1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
ior2 H = TOS H = top of stack 
ior3 MDR = TOS = MDR OR H; wr; 
goto main1 
Do OR; write to new top of stack 
dup1 MAR = SP = SP + 1 Increment SP and copy to MAR 
dup2 MDR = TOS; wr; goto main1 Write new stack word 
pop1 MAR = SP = SP-1; rd Read in next-to-top word on stack 
pop2 Wait for new TOS to be read from 
memory 
pop3 TOS = MDR; goto main1 Copy new word to TOS 
swap1 MAR = SP-1; rd Set MAR to SP-1; read 2nd word 
from stack 
swap2 MAR = SP Set MAR to top word 
swap3 H = MDR; wr Save TOS in H; write 2nd word to 
top of stack 
swap4 MDR = TOS Copy old TOS to MDR 
swap5 MAR = SP-1; wr Set MAR to SP-1; write as 2nd 
word on stack 
swap6 TOS = H; goto main1 Update TOS 
 
 
 29 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
IJVM Microinstruction 1 (MIC-1) Architecture Language (2 of 4) 
bipush1 SP = MAR = SP + 1 MBR = the byte to push onto stack 
bipush2 PC = PC + 1; fetch Increment PC, fetch next opcode 
bipush3 MDR = TOS = MBR; wr; goto 
main1 
Sign-extend constant and push on 
stack 
iload1 H = LV MBR contains index; copy LV to 
H 
iload2 MAR = MBRU + H; rd MAR = address of local variable 
to push 
iload3 MAR = SP = SP + 1 SP points to new top of stack; 
prepare write 
iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top 
of stack 
iload5 TOS = MDR; goto main1 Update TOS 
istore1 H = LV MBR contains index; Copy LV to 
H 
istore2 MAR = MBRU + H MAR = address of local variable 
to store into 
istore3 MDR = TOS; wr Copy TOS to MDR; write word 
istore4 SP = MAR = SP-1; rd Read in next-to-top word on stack 
istore5 PC = PC + 1; fetch Increment PC; fetch next opcode 
istore6 TOS = MDR; goto main1 Update TOS 
wide1 PC = PC+ 1; fetch; goto (MBR 
OR 0x100) 
Multiway branch with high bit set 
wide_iload1 PC = PC + 1; fetch MBR contains 1st index byte; 
fetch 2nd 
wide_iload2 H = MBRU << 8 H = 1st index byte shifted left 8 
bits 
wide_iload3 H = MBRU OR H H = 16-bit index of local variable 
wide_iload4 MAR = LV + H; rd; goto iload3 MAR = address of local variable 
to push 
wide_istore1 PC = PC + 1; fetch MBR contains 1st index byte; 
fetch 2nd 
wide_istore2 H = MBRU << 8 H = 1st index byte shifted left 8 
bits 
wide_istore3 H = MBRU OR H H = 16-bit index of local variable 
wide_istore4 MAR = LV + H; goto istore3 MAR = address of local variable 
to store into 
ldc_w1 PC = PC + 1; fetch MBR contains 1st index byte; 
fetch 2nd 
ldc_w2 H = MBRU << 8 H = 1st index byte << 8 
ldc_w3 H = MBRU OR H H = 16-bit index into constant pool
ldc_w4 MAR = H + CPP; rd; goto iload3 MAR = address of constant in pool
 
 
 30 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
IJVM Microinstruction 1 (MIC-1) Architecture Language (3 of 4) 
iinc1 H = LV MBR contains index; Copy LV to 
H 
iinc2 MAR = MBRU + H; rd Copy LV + index to MAR; Read 
variable 
iinc3 PC = PC + 1; fetch Fetch constant 
iinc4 H = MDR Copy variable to H 
iinc5 PC = PC + 1; fetch Fetch next opcode 
iinc6 MDR = MBR + H; wr; goto main1 Put sum in MDR; update variable 
goto1 OPC = PC - 1 Save address of opcode. 
goto2 PC = PC + 1; fetch MBR = 1st byte of offset; fetch 
2nd byte 
goto3 H = MBR << 8 Shift and save signed first byte in 
H 
goto4 H = MBRU OR H H = 16-bit branch offset 
goto5 PC = OPC + H; fetch Add offset to OPC 
goto6 goto main1 Wait for fetch of next opcode 
iflt1 MAR = SP = SP - 1; rd Read in next-to-top word on stack 
iflt2 OPC = TOS Save TOS in OPC temporarily 
iflt3 TOS = MDR Put new top of stack in TOS 
iflt4 N = OPC; if (N) goto T; else goto 
F 
Branch on N bit 
ifeq1 MAR = SP = SP - 1; rd Read in next-to-top word of stack 
ifeq2 OPC = TOS Save TOS in OPC temporarily 
ifeq3 TOS = MDR Put new top of stack in TOS 
ifeq4 Z = OPC; if (Z) goto T; else goto F Branch on Z bit 
if_icmpeq1 MAR = SP = SP - 1; rd Read in next-to-top word of stack 
if_icmpeq2 MAR = SP = SP - 1 Set MAR to read in new top-of-
stack 
if_icmpeq3 H = MDR; rd Copy second stack word to H 
if_icmpeq4 OPC = TOS Save TOS in OPC temporarily 
if_icmpeq5 TOS = MDR Put new top of stack in TOS 
if_icmpeq6 Z = OPC - H; if (Z) goto T; else 
goto F 
If top 2 words are equal, goto T, 
else goto F 
T OPC = PC - 1; fetch; goto goto2 Same as goto1; needed for target 
address 
F PC = PC + 1 Skip first offset byte 
F2 PC = PC + 1; fetch PC now points to next opcode 
F3 goto main1 Wait for fetch of opcode 
 
 
 31 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, Structured 
Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
IJVM Microinstruction 1 (MIC-1) Architecture Language (4 of 4) 
invokevirtual1 PC = PC + 1; fetch MBR = index byte 1; inc. PC, get 
2nd byte 
invokevirtual2 H = MBRU << 8 Shift and save first byte in H 
invokevirtual3 H = MBRU OR H H = offset of method pointer from 
CPP 
invokevirtual4 MAR = CPP + H; rd Get pointer to method from CPP 
area 
invokevirtual5 OPC = PC + 1 Save Return PC in OPC 
temporarily 
invokevirtual6 PC = MDR; fetch PC points to new method; get 
param count 
invokevirtual7 PC = PC + 1; fetch Fetch 2nd byte of parameter count 
invokevirtual8 H = MBRU << 8 Shift and save first byte in H 
invokevirtual9 H = MBRU OR H H = number of parameters 
invokevirtual10 PC = PC + 1; fetch Fetch first byte of # locals 
invokevirtual11 TOS = SP - H TOS = address of OBJREF - 1 
invokevirtual12 TOS = MAR = TOS + 1 TOS = addressof OBJREF (new 
LV) 
invokevirtual13 PC = PC + 1; fetch Fetch second byte of # locals 
invokevirtual14 H = MBRU << 8 Shift and save first byte in H 
invokevirtual15 H = MBRU OR H H = # locals 
invokevirtual16 MDR = SP + H + 1; wr Overwrite OBJREF with link 
pointer 
invokevirtual17 MAR = SP = MDR; Set SP, MAR to location to hold 
old PC 
invokevirtual18 MDR = OPC; wr Save old PC above the local 
variables 
invokevirtual19 MAR = SP = SP + 1 SP points to location to hold old 
LV 
invokevirtual20 MDR = LV; wr Save old LV above saved PC 
invokevirtual21 PC = PC + 1; fetch Fetch first opcode of new method. 
invokevirtual22 LV = TOS; goto main1 Set LV to point to LV Frame 
ireturn1 MAR = SP = LV; rd Reset SP, MAR to get link pointer 
ireturn2 Wait for read 
ireturn3 LV = MAR = MDR; rd Set LV to link ptr; get old PC 
ireturn4 MAR = LV + 1 Set MAR to read old LV 
ireturn5 PC = MDR; rd; fetch Restore PC; fetch next opcode 
ireturn6 MAR = SP Set MAR to write TOS 
ireturn7 LV = MDR Restore LV 
ireturn8 MDR = TOS; wr; goto main1 Save return value on original top 
of stack 
 
 
 32 of 32 ECE 357 
Notes and figures are based on or taken from materials in the course textbook: A.S. Tanenbaum, 
Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, 1999. ISBN 0-13-095990-1. 
A “blank” instruction page for practice. 
Executing the JAVA Instructions in Mic-1 
Cycle 0 1 2 3 4 5 6 
MPC main1 
INST PC= PC+1; 
fetch; goto 
(MBR) 
 
Next MPC gt (MBR) 
PC 
fetch 
PC PC+1 
fetch 
 
MBR uInst Next Inst 
MAR 
rd/wr 
 
MDR 
SP 
LV 
CPP 
TOS 
H