Eletrônica Digital SG - Atividade Prática Final

Prévia do material em texto

INSTRUÇÕES: 
 
❖ Esta Avaliação contém 1 (uma) questão, totalizando 10 (dez) pontos; 
❖ Baixe o arquivo disponível com a Atividade Pratica; 
❖ Você deve preencher dos dados no Cabeçalho para sua identificação: 
o Nome / Data de entrega. 
❖ As respostas devem ser digitadas abaixo de cada pergunta; 
❖ Ao terminar grave o arquivo com o nome Atividade Prática; 
o Quando solicitado 
❖ Envio o arquivo pelo sistema no local indicado; 
❖ Em caso de dúvidas consulte o seu Tutor. 
 
 
 
 
 Eletrônica Digital 
 
 Avaliação Pratica 
O projeto de circuitos digitais baseados em elementos discretos ou em linguagens de des-
crição de hardware (hardware description language – HDL), em geral, integra tanto elementos 
combinacionais quanto sequenciais. Nesse contexto, um projetista deve ter a capacidade de es-
colher a abordagem que melhor se adequa ao perfil das partes do seu projeto e, assim, realizar 
uma implementação consistente. 
Neste Desafio, você, como um profissional da área, deverá desenvolver um circuito digital 
em HDL contendo elementos com características combinacionais e sequenciais. 
 
 
 
 
Aluno (a): Data:
http://lrq.sagah.com.br/uasdinamicas/uploads/layouts/1805992475_155558835086143ae1998e257b622b3a1e20e2e5a8345f3a26.jpg
 
 
Circuito desenvolvido no software Multisim. 
 
 
** Projeto3. ** 
* 
* NI Multisim to SPICE Netlist Export 
* Generated by: atuniati 
* Wed, Feb 03, 2021 08:02:25 
* 
 
*## Multisim Component R9 ##* 
rR9 15 22 150 vresR9 
.model vresR9 r( ) 
 
*## Multisim Component R8 ##* 
rR8 14 21 150 vresR8 
.model vresR8 r( ) 
 
*## Multisim Component R7 ##* 
rR7 13 20 150 vresR7 
.model vresR7 r( ) 
 
*## Multisim Component R6 ##* 
rR6 12 19 150 vresR6 
.model vresR6 r( ) 
 
*## Multisim Component R5 ##* 
rR5 11 18 150 vresR5 
.model vresR5 r( ) 
 
*## Multisim Component R4 ##* 
rR4 10 17 150 vresR4 
.model vresR4 r( ) 
 
*## Multisim Component R3 ##* 
rR3 9 16 150 vresR3 
.model vresR3 r( ) 
 
*## Multisim Component R2 ##* 
 
 
rR2 1 2 150 vresR2 
.model vresR2 r( ) 
 
*## Multisim Component U2 ##* 
* !!!BEGIN-INTERACT 
* ( External state variables ) 
* : i_on ++++f2 ; 
* 
* ( Internal state variables ) 
* 0.0 VARIABLE r1Cur 
* 0.0 VARIABLE r2Cur 
* 0.0 VARIABLE r3Cur 
* 0.0 VARIABLE r4Cur 
* 0.0 VARIABLE r5Cur 
* 0.0 VARIABLE r6Cur 
* 0.0 VARIABLE r7Cur 
* 
* : RESET 
* 0 20 0 SET_SUBCOMP_PRP 
* 0 19 0 SET_SUBCOMP_PRP 
* 0 18 0 SET_SUBCOMP_PRP 
* 0 17 0 SET_SUBCOMP_PRP 
* 0 16 0 SET_SUBCOMP_PRP 
* 0 15 0 SET_SUBCOMP_PRP 
* 0 14 0 SET_SUBCOMP_PRP 
* 0.0 ==>_*r1Cur 
* 0.0 ==>_*r2Cur 
* 0.0 ==>_*r3Cur 
* 0.0 ==>_*r4Cur 
* 0.0 ==>_*r5Cur 
* 0.0 ==>_*r6Cur 
* 0.0 ==>_*r7Cur 
* ; 
* 
* :ON_USER_UPDATE 
* RESET 
* ; 
* 
* :OUT_DATA 
* GET_INSTANCE Vsource ::V V1 i ==>_*r1Cur 
* GET_INSTANCE Vsource ::V V2 i ==>_*r2Cur 
* GET_INSTANCE Vsource ::V V3 i ==>_*r3Cur 
* GET_INSTANCE Vsource ::V V4 i ==>_*r4Cur 
* GET_INSTANCE Vsource ::V V5 i ==>_*r5Cur 
* GET_INSTANCE Vsource ::V V6 i ==>_*r6Cur 
* GET_INSTANCE Vsource ::V V7 i ==>_*r7Cur 
* i_on *r1Cur f.< if 
* 1 20 0 SET_SUBCOMP_PRP 
* else 
* 0 20 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r2Cur f.< if 
* 1 17 0 SET_SUBCOMP_PRP 
* else 
* 0 17 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r3Cur f.< if 
 
 
* 1 16 0 SET_SUBCOMP_PRP 
* else 
* 0 16 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r4Cur f.< if 
* 1 18 0 SET_SUBCOMP_PRP 
* else 
* 0 18 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r5Cur f.< if 
* 1 14 0 SET_SUBCOMP_PRP 
* else 
* 0 14 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r6Cur f.< if 
* 1 15 0 SET_SUBCOMP_PRP 
* else 
* 0 15 0 SET_SUBCOMP_PRP 
* endif 
* i_on *r7Cur f.< if 
* 1 19 0 SET_SUBCOMP_PRP 
* else 
* 0 19 0 SET_SUBCOMP_PRP 
* endif 
* 
* ; 
* 
* :BEGIN_PLOT 
* RESET 
* ; 
* 
* 
*!!!END-INTERACT 
 
xU2 16 17 18 19 20 21 22 0 seven_segmentU2 
 
.subckt seven_segmentU2 1 2 3 4 5 6 7 10 
V1 1 1a DC 0 
V2 2 2a DC 0 
V3 3 3a DC 0 
V4 4 4a DC 0 
V5 5 5a DC 0 
V6 6 6a DC 0 
V7 7 7a DC 0 
D1 1a 10 DLEDSEG 
D2 2a 10 DLEDSEG 
D3 3a 10 DLEDSEG 
D4 4a 10 DLEDSEG 
D5 5a 10 DLEDSEG 
D6 6a 10 DLEDSEG 
D7 7a 10 DLEDSEG 
.MODEL DLEDSEG D ( 
+ IS=2.560e-014 N=3.007e+000 RS=8.513e-003 
+ BV=6.100e+001 IBV=6.000e-006 
+ EG=1.110e+000 XTI=3.000e+000 
+ CJO=3.238e-011, M=3.388e-001 VJ=3.250e-001 
+ FC=5.000e-001 KF=0.000e+000 AF=1.000e+000 ) 
 
 
.ends 
 
*## Multisim Component R1 ##* 
* !!!BEGIN-INTERACT 
* : increment ++++f4 ; 
* : tresistance ++++f6 ; 
* 0.0 constant mindval 
* 100.0 constant maxdval 
* tresistance VARIABLE resistance 
* 50.0 VARIABLE setting 
* 0 VARIABLE num_stored 
* 0.0 VARIABLE setresval 
* 0.0 VARIABLE zeroadj 
* 0.0 VARIABLE setfactor 
* 0 VARIABLE flag 
* 
* :MAP_KEYBOARD_INPUT ++++k1 1 ++++K1 -1 ; 
* 
* : UPDATE_SETTINGS 
* *flag 0 = if 
* LOAD_FICL_VARIABLES 
* ==>_*num_stored 
* ==>_*num_stored 
* *num_stored 0 > if 
* ==>_*setting 
* ==>_*setresval 
* *setresval tresistance f./ ==>_*setfactor 
* *setresval SET_INSTANCE Resistor ::R R1 resistance 
* endif 
* 1 ==>_*flag 
* endif 
* 0.01 *setting f.* ==>_*zeroadj 
* *zeroadj PERCENT SET_ANIMATION_TEXT 
* 0.00001 0.999999 *zeroadj f.min f.max ==>_*setfactor 
* *setfactor tresistance f.* resistance GRADUAL_CHANGE_AT_RUN 
* *setfactor tresistance f.* *setting 2 0 
* STORE_FICL_VARIABLES 
* ; 
* 
* :GRADUAL_CHANGE_AT_RUN locals| ref value | 
* value SET_INSTANCE Resistor ::R R1 resistance 
* ; 
* 
* :KEYBOARD_INPUT locals| shift_state | 
* shift_state (float) increment f.* *setting f.+ ==>_*setting 
* mindval maxdval *setting f.min f.max ==>_*setting 
* UPDATE_SETTINGS 
* ; 
* 
* :BEGIN_PLOT 
* UPDATE_SETTINGS 
* ; 
* 
* :BEGIN_ANALYSIS 
* UPDATE_SETTINGS 
* ; 
* 
 
 
* : INIT_SLIDER 
* maxdval mindval 3 IMOUSE_SET 
* ; 
* 
* : ON_IMOUSE_EVENT locals| eType fValue | 
* eType 9 = if 
* -1 
* fValue ==>_*setting 
* else 
* 0 
* endif 
* UPDATE_SETTINGS 
* ; 
* 
* : GET_INTERACT_VALUE locals| eType | 
* eType 0 = if 
* *setting 
* else eType 1 = if 
* mindval 
* else eType 2 = if 
* maxdval 
* else eType 3 = if 
* increment 
* else 
* 0 
* endif endif endif endif 
* ; 
* 
* : SET_INTERACT_VALUE locals| eType fValue | 
* eType 0 = if 
* fValue ==>_*setting 
* endif 
* UPDATE_SETTINGS 
* ; 
* 
* :ON_USER_UPDATE 
* UPDATE_SETTINGS 
* INIT_SLIDER 
* ; 
* 
* !!!END-INTERACT 
xR1 2 3 VariableResistorR1 
.subckt VariableResistorR1 1 2 
R1 1 2 50e-12 
.ends 
 
*## Multisim Component C1 ##* 
cC1 3 0 1e-06 
 
*## Multisim Component U3 ##* 
aU3 [dU3.notLE 
+ dU3.notBI 
+ dU3.notLT 
+ 8 
+ 7 
+ 6 
+ 5] 
 
 
+ [dU3.YA 
+ dU3.YB 
+ dU3.YC 
+ dU3.YD 
+ dU3.YE 
+ dU3.YF 
+ dU3.YG 
+ dU3.VSS 
+ dU3.VDD] 4511B_10__CMOS_5V_IC__1 
 
xU3.notLT 1 dU3.notLT U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_RCV__NON__1 
 
xU3.notBI U3.PinVoltage--3.1 dU3.notBI U3.PinVoltage--15.1 U3.PinVoltage--7.0 
CMOS_RCV__NON__1 
 
xU3.notLE U3.PinVoltage--4.0 dU3.notLE U3.PinVoltage--15.1 U3.PinVoltage--7.0 
CMOS_RCV__NON__1 
 
xU3.YE dU3.YE 13 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YD dU3.YD 12 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YC dU3.YC 11 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YB dU3.YB 10 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YA dU3.YA 9 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YG dU3.YG15 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
xU3.YF dU3.YF 14 U3.PinVoltage--15.1 U3.PinVoltage--7.0 CMOS_DRV__NON__1 
 
*## Multisim Component U1 ##* 
aU1 [dU1.1CLK 
+ dU1.not1CLK 
+ dU1.1RST 
+ U1_OPEN_2CLK 
+ U1_OPEN_not2CLK 
+ U1_OPEN_2RST] 
+ [5 
+ 6 
+ 7 
+ 8 
+ U1_OPEN_2A 
+ U1_OPEN_2B 
+ U1_OPEN_2C 
+ U1_OPEN_2D 
+ dU1.VSS 
+ dU1.VDD] 4518IC__CMOS_5V_IC__1 
 
xU1.1CLK U1.PinVoltage--0.0 dU1.1CLK U1.PinVoltage--15.1 U1.PinVoltage--7.0 
CMOS_RCV__NON__1 
 
xU1.not1CLK 4 dU1.not1CLK U1.PinVoltage--15.1 U1.PinVoltage--7.0 CMOS_RCV__NON__1 
 
xU1.1RST U1.PinVoltage--6.0 dU1.1RST U1.PinVoltage--15.1 U1.PinVoltage--7.0 
CMOS_RCV__NON__1 
 
 
*## Multisim Component A1 ##* 
xA1 0 3 4 1 A1_OPEN_CON A1.PinVoltage--5.3 2 1 IDEAL_TIMER__MIXED_VIRTUAL__1 
 
*## Multisim Component V1 ##* 
vV1 1 0 dc 6 ac 0 0 
+ distof1 0 0 
+ distof2 0 0 
 
.MODEL 4511B_10__CMOS_5V_IC__1 d_chip ( behaviour= " 
+;4511 BCD to 7-segment latch/decoder/driver @10V 
+/INPUTS ~EL ~BI ~LT DD DC DB DA 
+/OUTPUTS OA OB OC OD OE OF OG 
+/TABLE 19 
+;~EL ~BL ~LT DCBA OA OB OC OD OE OF OG 
+ H X X XXXX OA OB OC OD OE OF OG 
+ X X L XXXX H H H H H H H 
+ X L H XXXX L L L L L L L 
+ L H H LLLL H H H H H H L 
+ L H H LLLH L H H L L L L 
+ L H H LLHL H H L H H L H 
+ L H H LLHH H H H H L L H 
+ L H H LHLL L H H L L H H 
+ L H H LHLH H L H H L H H 
+ L H H LHHL L L H H H H H 
+ L H H LHHH H H H L L L L 
+ L H H HLLL H H H H H H H 
+ L H H HLLH H H H L L H H 
+ L H H HLHL L L L L L L L 
+ L H H HLHH L L L L L L L 
+ L H H HHLL L L L L L L L 
+ L H H HHLH L L L L L L L 
+ L H H HHHL L L L L L L L 
+ L H H HHHH L L L L L L L 
+/delay 28 
+;input output Rise time Fall time 
+ DA OA 270n 310n 
+ DA OB 270n 310n 
+ DA OC 270n 310n 
+ DA OD 270n 310n 
+ DA OE 270n 310n 
+ DA OF 270n 310n 
+ DA OG 270n 310n 
+ DB OA 270n 310n 
+ DB OB 270n 310n 
+ DB OC 270n 310n 
+ DB OD 270n 310n 
+ DB OE 270n 310n 
+ DB OF 270n 310n 
+ DB OG 270n 310n 
+ DC OA 270n 310n 
+ DC OB 270n 310n 
+ DC OC 270n 310n 
+ DC OD 270n 310n 
+ DC OE 270n 310n 
+ DC OF 270n 310n 
+ DC OG 270n 310n 
+ DD OA 270n 310n 
 
 
+ DD OB 270n 310n 
+ DD OC 270n 310n 
+ DD OD 270n 310n 
+ DD OE 270n 310n 
+ DD OF 270n 310n 
+ DD OG 270n 310n 
+") 
 
.MODEL 4518IC__CMOS_5V_IC__1 d_chip ( behaviour= " 
+;4518 DUAL BCD COUNTER @5V 
 
+/INPUTS 1CLK ~1CLK 1RST 2CLK ~2CLK 2RST 
+/OUTPUTS 1A 1B 1C 1D 2A 2B 2C 2D 
 
+/MODULE COUNTER00 
 
+/INPUTS CP0 ~CP1 MR 
+/OUTPUTS O0 O1 O2 O3 
+/WIRES CP 
+/module CNTL_4518 
+/inputs A ~B 
+/outputs CP 
+/table 4 
+; inputs output 
+;A ~B CP 
+ L L H 
+ H L H 
+ L H L 
+ H H H 
+/endmodule 
+/instance CNTL_4518 CP0 ~CP1 CP 
+; 
+/module BCD_4518 
+/INPUTS CP MR 
+/OUTPUTS O0 O1 O2 O3 
+;clock input_number edge{+|-} number_of_flags sync_entries async_entries 
+/clock CP + 4 3 2 
+; CP MR FFFF F0 F1 F2 F3 
+ X X HLLH L L L L 
+ X X XXXX F+0 F+1 F+2 F+3 
+ X X XXXX F0 F1 F2 F3 
+; CP MR FFFF F0 F1 F2 F3 
+ X H XXXX L L L L 
+ X L XXXX F0 F1 F2 F3 
+/TABLE 1 
+;CP MR F0 F1 F2 F3 O0 O1 O2 O3 
+ X X X X X X F0 F1 F2 F3 
+/endmodule 
+/instance BCD_4518 CP MR O0 O1 O2 O3 
+/delay 12 
+;input output Rise time Fall time 
+ CP0 O0 240n 240n 
+ CP0 O1 240n 240n 
+ CP0 O2 240n 240n 
+ CP0 O3 240n 240n 
+ ~CP1 O0 240n 240n 
+ ~CP1 O1 240n 240n 
 
 
+ ~CP1 O2 240n 240n 
+ ~CP1 O3 240n 240n 
+ MR O0 X 150n 
+ MR O1 X 150n 
+ MR O2 X 150n 
+ MR O3 X 150n 
+/constraint 7 
+; Name Event From Event To Min/Max Time 
+ 'PULSE WIDTH' HL CP0 LH CP0 MIN 60n 
+ 'PULSE WIDTH' LH ~CP1 HL ~CP1 MIN 60n 
+ 'PULSE WIDTH' LH MR HL MR MIN 30n 
+ 'SETUP' LH ~CP1 LH CP0 MIN 50n 
+ 'SETUP' HL CP0 HL ~CP1 MIN 50n 
+ 'RECOVERY' HL MR LH CP0 MIN 50n 
+ 'RECOVERY' HL MR HL ~CP1 MIN 50n 
 
+/endmodule 
 
+/instance COUNTER00 1CLK ~1CLK 1RST 1A 1B 1C 1D 
+/instance COUNTER00 2CLK ~2CLK 2RST 2A 2B 2C 2D 
 
+") 
 
.SUBCKT CMOS_DRV__NON__1 1 2 3 4 
* CMOS Driver Model 1 = D/A input, 2 = out 3= VCC 4 = VSS(GND) 
*#L1 
aDAC1in [1] [2] aDAC1 
.MODEL aDAC1 dac_bridge (out_low= 0 out_high = 5.0 out_undef = 0) 
*#L1 
 
.ENDS 
 
.SUBCKT CMOS_RCV__NON__1 1 2 3 4 
* CMOS LOAD Model 1 = input, 2 = A/D out 3 = VCC 4 = VSS(GND) 
*#L1 
aADC1in [1] [2] ADC1 
.MODEL ADC1 adc_bridge (in_low= 2.5 in_high = 2.5) 
*#L1 
 
.ENDS 
 
.subckt IDEAL_TIMER__MIXED_VIRTUAL__1 0 2 3 4 5 6 7 8 
rn1 8 5 5k 
rn2 5 51 5k 
rn3 51 0 5k 
aop1 %vd(5 6) 56 op 
aop2 %vd(2 51) 52 op 
.model op limit (gain= 3000, 
+ out_upper_limit=5, 
+ out_lower_limit=-5, 
+ limit_range=1 fraction=true) 
aadc1 [56 52] [r s] ADC1 
.MODEL ADC1 adc_bridge (in_low= 3.5 in_high = 3.5 rise_delay= 1e-12 fall_delay= 1e-12) 
anand1 [r Q2] Q1 nand1 
anand2 [s Q1] Q2 nand1 
.model nand1 d_nand(rise_delay=1n) 
adac1 [q1 q2] [66 62] DAC1 
 
 
rad3 66 0 1 
rad4 62 0 1 
aadc4 [4] [40] ADC1 
ainv2 40 41 inv1 
adlatch q1 2u 41 3d Qb Qc dlt 
.model dlt d_dlatch(rise_delay=1e-12) 
apu1 2u pullup1 
.model pullup1 d_pullup(load=10e-12) 
apd1 3d pulldown1 
.model pulldown1 d_pulldown(load=10e-12) 
ainv1 Qb 31 inv1 
.model inv1 d_inverter(rise_delay=1e-12) 
adac72 [Qb] [72] DAC1 
adac31 [31] [32] DAC1 
r30 32 0 1g 
b1 3 0 v=(v(32)*v(8)/5) 
r3 3 0 1g 
.MODEL DAC1 dac_bridge (out_low= 0.0 out_high= 5.0 out_undef=0.5) 
rad5 72 0 1meg 
mdis 7 72 0 0 mdis 
.MODEL mdis nmos (VTO=1.29 PHI=0.4 LAMBDA=5 KP=4.3m LD=12.8u GAMMA =3) 
.ends