mc542-A-03-2s07

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MC542
3.1
2007
Prof. Paulo Cesar Centoducatte
ducatte@ic.unicamp.br
www.ic.unicamp.br/~ducatte
MC542
Organização de Computadores
Teoria e Prática
MC542
3.2
MC542
Arquitetura de Computadores
Micro-Arquitetura
“DDCA” - (Capítulo 7)
“COD” - (Capítulo)
MC542
3.3
Micro-Arquitetura
• Micro-Arquitetura
– Introdução
– Recursos
– MIPS Mono-Ciclo
» Lw
» Sw
» R-Type
» Beq
» j
– MIPS Múlti-Ciclos
» Lw
» Sw
» R-Type
» Beq
» j
MC542
3.4
Introdução
• Micro-arquitetura: como está
implementada a arquitetura em
hardware
• Processador:
– Datapath: blocos funcionais
– Controle: sinais de controle
Physics
Devices
Analog
Circuits
Digital
Circuits
Logic
Micro-
architecture
Architecture
Operating
Systems
Application
Software
electrons
transistors
diodes
amplifiers
filters
AND gates
NOT gates
adders
memories
datapaths
controllers
instructions
registers
device drivers
programs
MC542
3.5
Micro-Arquitetura
• Múltiplas implementações para uma mesma
arquitetura:
– Single-cycle
» Cada instrução é executada em um único ciclo
– Multicycle
» A execução de cada instrução é dividida em uma série de 
passos menores
– Pipelined
» A execução de cada instrução é dividida em uma série de 
passos menores
» Múltiplas instruções (parte de) executando ao mesmo
tempo.
MC542
3.6
Micro-Arquitetura
• Program execution time
Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)
• Definições:
– Cycles/instruction = CPI
– Seconds/cycle = clock period
– 1/CPI = Instructions/cycle = IPC
• Desafios na implementação de uma micro-arquitetura
– Custo
– Power
– Desempenho
MC542
3.7
Micro-Arquitetura
• Processador MIPS (Microprocessor without Interlolocked 
Pipeline Stages)
– Vamos implementar um sub conjunto das instruções
MIPS:
– R-type instructions: and, or, add, sub, slt
– Memory instructions: lw, sw
– Branch instructions: beq
MC542
3.8
Micro-Arquitetura
• Estado da Arquitetura
– Determina o estado do Processador em um dado instante de 
tempo
PC
32 registradores
Memória
MC542
3.9
Micro-Arquitetura
• Elementos de estados do MIPS:
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
A RD
Data
Memory
WD
WE
PCPC'
CLK
32 32
32 32
32
32
32
32
32
32
5
5
5
MC542
3.10
Processador MIPS Single-Cycle
• Datapath
• Controle
MC542
3.11
Processador MIPS Single-Cycle
• Execução de lw
1: Fetch da Instrução
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
A RD
Data
Memory
WD
WEPC
PC'
Instr
CLK
MC542
3.12
Processador MIPS Single-Cycle
• Execução de lw
2: Lê o operando fonte do RF
Instr
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
A RD
Data
Memory
WD
WE
PCPC'
25:21
CLK
MC542
3.13
Processador MIPS Single-Cycle
• Execução de lw
3: Sign-extend o imediato
SignImm
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
A RD
Data
Memory
WD
WE
PCPC' Instr
25:21
15:0
CLK
MC542
3.14
Processador MIPS Single-Cycle
• Execução de lw
4: Calcula o endereço efetivo de memória
SignImm
CLK
A RD
Instruction
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
A RD
Data
Memory
WD
WE
PCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA Zero
CLK
ALUControl
2:0
A
L
U
010
MC542
3.15
Processador MIPS Single-Cycle
• Execução de lw
5: Lê o dado da memória e o escreva no RF
A1
A3
WD3
RD2
RD1
WE3
A2
SignImm
CLK
A RD
Instruction
Memory
CLK
Sign Extend
Register
File
A RD
Data
Memory
WD
WE
PCPC' Instr
25:21
15:0
SrcB
20:16
ALUResult ReadData
SrcA
RegWrite
Zero
CLK
ALUControl
2:0
A
L
U
0101
MC542
3.16
Processador MIPS Single-Cycle
• Execução de lw
6: Determina o endereço da próxima instrução
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
A RD
Data
Memory
WD
WE
PCPC' Instr
25:21
15:0
SrcB
20:16
ALUResult ReadData
SrcA
PCPlus4
Result
RegWrite
Zero
CLK
ALUControl
2:0
A
L
U
0101
MC542
3.17
Processador MIPS Single-Cycle
• Execução de sw
• Precisa escrever o valor do registrador na memória
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
A RD
Data
Memory
WD
WE
PCPC' Instr
25:21
20:16
15:0
SrcB
20:16
ALUResult ReadData
WriteData
SrcA
PCPlus4
Result
MemWriteRegWrite
Zero
CLK
ALUControl
2:0
A
L
U
10100
MC542
3.18
Processador MIPS Single-Cycle
• Instruções R-Type: add, sub, and, or, ….
• Escrever ALUResult no RF
– Escreve em rd e não em rt
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PCPC' Instr
25:21
20:16
15:0
SrcB
20:16
15:11
ALUResult ReadData
WriteData
SrcA
PCPlus4
WriteReg4:0
Result
RegDst MemWrite MemtoRegALUSrcRegWrite
Zero
CLK
ALUControl
2:0
A
L
U
0
varies1 001
MC542
3.19
Processador MIPS Single-Cycle
• Instrução beq
• Determina se os conteúdos dos registradores são
iguais
• Calcula o endereço alvo do desvio (sign-extended 
immediate + PC+4)
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
RegDst Branch MemWrite MemtoRegALUSrcRegWrite
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
0
1100 x0x 1
MC542
3.20
Processador MIPS Single-Cycle - or
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
001
0
0
1
0
0
1
0
MC542
3.21
Processador MIPS Single-Cycle - sw
+
+
A
L
U
MC542
3.22
Processador MIPS Single-Cycle
• Unidade de Controle
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
MC542
3.23
Processador MIPS Single-Cycle
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
Opcode5:0
Control
Unit
ALUControl2:0Funct5:0
Main
Decoder
ALUOp1:0
ALU
Decoder
RegWrite
Control Unit
MC542
3.24
Processador MIPS Single-Cycle
• ALU
A & B000
A | B001
A + B010
not used011
A & B100
A | ~B101
A - B110
SLT111
FunctionF2:0
ALU
N N
N
3
A B
Y
F
MC542
3.25
Processador MIPS Single-Cycle
• ALU
+
2 01
A B
C
out
Y
3
01
F
2
F
1:0
[N-1] S
NN
N
N
N NNN
N
2
Z
e
ro
E
x
te
n
d
MC542
3.26
Processador MIPS Single-Cycle
• ALU Decoder
Not Used11
Look at Funct10
Subtract01
Add00
MeaningALUOp1:0 
111 (SLT)101010 (slt)1X
001 (Or)100101 (or)1X
000 (And)100100 (and)1X
110 (Subtract)100010 (sub)1X
010 (Add)100000 (add)1X
110 (Subtract)XX1
010 (Add)X00
ALUControl2:0FunctALUOp1:0
MC542
3.27
Processador MIPS Single-Cycle
• Decodificador Principal
01X010X0000100beq
00X101X0101011sw
00000101100011lw
10000011000000R-type
ALUOp1:
0
MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction
MC542
3.28
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: addi
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResultReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
MC542
3.29
Processador MIPS Single-Cycle
• Decodificador Principal
00000101001000addi
01X010X0000100beq
00X101X0101011sw
00100101100011lw
10000011000000R-type
ALUOp1:0MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction
MC542
3.30
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: j
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
MC542
3.31
Processador MIPS Single-Cycle
• Extendendo a Funcionalidade: j
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542
3.32
Processador MIPS Single-Cycle
• Decodificador Principal
1XXX0XXX0000100j
0
0
0
0
0
Jump
00000101001000addi
01X010X0000100beq
00X101X0101011sw
00100101100011lw
10000011000000R-type
ALUOp1:0MemtoRegMemWriteBranchAluSrcRegDstRegWriteOp5:0Instruction
MC542
3.33
Processador MIPS Single-Cycle
• Desempenho: Quão rápido é o processador?
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542
3.34
Processador MIPS Single-Cycle
• O cycle time é limitado pelo caminho crítico: lw
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
1
010
0
1
0
1
0 0
MC542
3.35
Processador MIPS Single-Cycle
• Caminho crítico
Tc = tpcq_PC + tmem + max(tRFread, tsext) + tmux + tALU + tmem + tmux + tRFsetup
• Na maioria das implementações os caminhos limitantes
são: memória, ALU, register file. Assim,
Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup
MC542
3.36
Processador MIPS Single-Cycle
30tpcq_PCRegister clock-to-Q
Delay (ps)ParameterElement
20tsetupRegister setup
25tmuxMultiplexer
200tALUALU
250tmemMemory read
150tRFreadRegister file read
20tRFsetupRegister file setup
Tc = tpcq_PC + 2tmem + tRFread + 2tmux + tALU + tRFsetup
= [30 + 2(250) + 150 + 2(25) + 200 + 20] ps
= 950 ps
MC542
3.37
Processador MIPS Single-Cycle
• Para um programa 100 bilhões de instruções executando em um 
processador MIPS single-cycle,
Execution Time = (# instructions)(cycles/instruction)(seconds/cycle)
= (100 × 109)(1)(950 × 10-12 s)
= 95 seconds
MC542
3.38
Processador MIPS Multicycle
• Datapath
• Controle
MC542
3.39
Processador MIPS Multicycle
• Blocos Básicos
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
PCPC'
WD
WE
CLK
EN
A
L
U
Restrição de Projeto: 
Somente 1 pode ser usado por vez
MC542
3.40
Processador MIPS Multicycle
• Datapath
– datapath para o lw
Exemplo: lw $s4, 27($t2)
• Fetch da Instrução
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
PCPC' Instr
CLK
WD
WE
CLK
EN
IRWrite
MC542
3.41
Processador MIPS Multicycle
• Leitura do operando fonte do RF (rs)
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Register
File
PCPC' Instr
25:21
CLK
WD
WE
CLK CLK
A
EN
IRWrite
MC542
3.42
Processador MIPS Multicycle
• Sign-Extend o Imediato
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
PCPC' Instr
25:21
15:0
CLK
WD
WE
CLK CLK
A
EN
IRWrite
MC542
3.43
Processador MIPS Multicycle
• Soma do Base Address ao Offset
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
PCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA
ALUOut
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK CLK
A CLK
EN
IRWrite
MC542
3.44
Processador MIPS Multicycle
• Carga do dado a partir da Memória
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
PCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA
ALUOut
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
Data
CLK
CLK
A CLK
EN
IRWriteIorD
0
1
MC542
3.45
Processador MIPS Multicycle
• Escrita do Dado no Register File
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
PCPC' Instr
25:21
15:0
SrcB
20:16
ALUResult
SrcA
ALUOut
RegWrite
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
Data
CLK
CLK
A CLK
EN
IRWriteIorD
0
1
MC542
3.46
Processador MIPS Multicycle
• Incremento do PC de 4
PCWrite
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1PCPC' Instr
25:21
15:0
SrcB
20:16
ALUResult
SrcA
ALUOut
ALUSrcARegWrite
CLK
ALUControl2:0
A
L
U
WD
WE
CLK
Adr
Data
CLK
CLK
A
00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorD
0
1
MC542
3.47
Processador MIPS Multicycle
• Datapath também para sw
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB
20:16
ALUResult
SrcA
ALUOut
MemWrite ALUSrcARegWrite
CLK
ALUControl2:0
A
L
U
WD
WE
CLK
Adr
Data
CLK
CLK
A
00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorDPCWrite
B
MC542
3.48
Processador MIPS Multicycle
• Datapath para instruções R-Type
0
1
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB20:16
15:11
ALUResult
SrcA
ALUOut
RegDstMemWrite MemtoReg ALUSrcARegWrite
CLK
ALUControl2:0
A
L
U
WD
WE
CLK
Adr
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB1:0IRWriteIorDPCWrite
MC542
3.49
Processador MIPS Multicycle
• Datapath para beq
SignImm
b
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0
IRWriteIorD PCWrite
PCEn
MC542
3.50
Processador MIPS Multicycle
• Datapath para o Processador Multicycle
ImmExt
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0
IRWriteIorD PCWrite
PCEn
MC542
3.51Processador MIPS Multicycle
• Controle para o Processador Multicycle
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
MC542
3.52
Processador MIPS Multicycle
• Unidade de controle
ALUSrcA
PCSrc
Branch
ALUSrcB
1:0
Opcode
5:0
Control
Unit
ALUControl2:0Funct5:0
Main
Controller
(FSM)
ALUOp
1:0
ALU
Decoder
RegWrite
PCWrite
IorD
MemWrite
IRWrite
RegDst
MemtoReg
Register
Enables
Multiplexer
Selects
MC542
3.53
Processador MIPS Multicycle
• Unidade de Controle
– Finite state machine
– Diagrama de transição de estados para lw
MC542
3.54
Processador MIPS Multicycle
• Fetch da Instrução
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
0
1 1
0
X
X
0
0
01
010
0
1
0
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S0: Fetch
MC542
3.55
Processador MIPS Multicycle
• Decodificação da Instrução
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
Reset
S0: Fetch S1: Decode
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
X
0 0
0
X
X
0
X
XX
XXX
X
0
0
MC542
3.56
Processador MIPS Multicycle
• Cálculo do endereço efetivo
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Reset
S0: Fetch
S2: MemAdr
S1: Decode
Op = LW
or
Op = SW
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
X
0 0
0
X
X
0
1
10
010
X
0
0
MC542
3.57
Processador MIPS Multicycle
• Leitura da Memória e 
Escrita no RF IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
Op = LW
or
Op = SW
Op = LW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
MC542
3.58
Processador MIPS Multicycle
• Diagrama de transição de estados para sw
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
IorD = 1
MemWrite
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
Op = LW
or
Op = SW
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
MC542
3.59
Processador MIPS Multicycle
• Diagrama de transição de estados para R-type
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
RegDst = 1
MemtoReg = 0
RegWrite
IorD = 1
MemWrite
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
Op = LW
or
Op = SW
Op = R-type
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
MC542
3.60
Processador MIPS Multicycle
• Diagrama de transição de estados para beq
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
RegDst = 1
MemtoReg = 0
RegWrite
IorD = 1
MemWrite
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op = LW
or
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
MC542
3.61
Processador MIPS Multicycle
• FSM de Controle
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
RegDst = 1
MemtoReg = 0
RegWrite
IorD = 1
MemWrite
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op = LW
or
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
MC542
3.62
Processador MIPS Multicycle
• Extendendo a Funcionalidade para addi
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
MC542
3.63
Processador MIPS Multicycle
• FSM de Controle para addi
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 0
IRWrite
PCWrite
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
RegDst = 1
MemtoReg = 0
RegWrite
IorD = 1
MemWrite
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op = LW
or
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
Writeback
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
RegDst = 0
MemtoReg = 0
RegWrite
Op = ADDI
S9: ADDI
Execute
S10: ADDI
Writeback
MC542
3.64
Processador MIPS Multicycle
• Extendendo a Funcionalidade para j
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
RegDst BranchMemWrite MemtoReg ALUSrcARegWrite
Zero
PCSrc
1:0
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0
IRWriteIorD PCWrite
PCEn
00
01
10
<<2
25:0 (jump)
31:28
27:0
PCJump
MC542
3.65
Processador MIPS Multicycle
• FSM de Controle para j
IorD = 0
AluSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 00
IRWrite
PCWrite
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
IorD = 1
RegDst = 1
MemtoReg = 0
RegWrite
IorD = 1
MemWrite
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCSrc = 01
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op = LW
or
Op = SW
Op = R-type
Op = BEQ
Op = LW
Op = SW
RegDst = 0
MemtoReg = 1
RegWrite
S4: Mem
WritebackALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
RegDst = 0
MemtoReg = 0
RegWrite
Op = ADDI
S9: ADDI
Execute
S10: ADDI
Writeback
PCSrc = 10
PCWrite
Op = J
S11: Jump
MC542
3.66
Processador MIPS Multicycle
• Desempenho: Quão rápido é o processador?
• Instruções gastam números diferentes de ciclos:
– 3 ciclos: beq, j
– 4 ciclos: R-Type, sw, addi
– 5 ciclos: lw
• O CPI deve ser a média ponderada
• SPECINT2000 benchmark: 
– 25% loads
– 10% stores 
– 11% branches
– 2% jumps
– 52% R-type
Average CPI = (0.11 + 0.2)(3) + (0.52 + 0.10)(4) + (0.25)(5) = 4.12
MC542
3.67
Processador MIPS Multicycle
• Caminho Crítico
Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1 0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
to
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
MC542
3.68
Processador MIPS Multicycle
30tpcq_PCRegister clock-to-
Q
Delay (ps)ParameterElement
20tsetupRegister setup
25tmuxMultiplexer
200tALUALU
250tmemMemory read
150tRFreadRegister file read
20tRFsetupRegister file setup
Tc = tpcq_PC + tmux + max(tALU + tmux, tmem) + tsetup
= tpcq_PC + tmux + tmem + tsetup
= [30 + 25 + 250 + 20] ps
= 325 ps
MC542
3.69
Processador MIPS Multicycle
• Para um programa que executa 100 bilhões de instruções em um 
MIPS multicycle,
• CPI = 4.12
• Tc = 325 ps
Execution Time = (# instructions) × CPI × Tc
= (100 × 109)(4.12)(325 × 10-12)
= 133.9 seconds
• Ele é mais lento do que o MIPS single-cycle (95 segundos). Por
que?
– Os passos não tem o mesmo tamanho
– Overhead do seqüenciamento de cada passo (tpcq + tsetup= 50 ps)
MC542
3.70
Revisão: Processador MIPS Single Cycle
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
MC542
3.71
Revisão: Processador MIPS Multicycle
ImmExt
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB20:16
15:11
<<2
ALUResult
SrcA
ALUOut
Zero
CLK
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
ENEN
00
01
10
<<2
25:0 (Addr)
31:28
27:0
PCJump
5:0
31:26
Branch
MemWrite
ALUSrcA
RegWrite
Op
Funct
Control
Unit
PCSrc
CLK
ALUControl
2:0
ALUSrcB
1:0IRWrite
IorD
PCWrite
PCEn
R
e
g
D
s
t
M
e
m
to
R
e
g