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hp Processing Tools Window Help projeto1911 projeto1911.vhd Compilation Report projeto19 267 268 1 IEEE; 2 3 use logic 4 entity is 5 port ( 6 in std logic; 7 in td_logic; 8 CLK: in std logic; 9 in std_logic; 10 led2: in std_logic; 11 led3: in std 12 led4: in std_logic; 13 led5: in std_logic; 14 led6: in std_logic; 15 led7: in std logic; 16 led8: in std logic; 17 signal Q: buffer std logic; 18 signal Qb: buffer std_logic); 19 end entity; 20 21 architecture portas of projeto1911 is 22 begin 23 process(CLK) 24 begin 25 if and then 26 27 if (J and K then Q ute) 28 elsif (J and K then Q > Find... Find Next ply clock uncertainty to any clock-to-clock transfers.